SPC5675KFF0MMM2

Qorivva 32-bit MCUs Qorivva MPC567xK Family Automotive safety and chassis control applications Overview on-chip redundancy is offered for the critical with up to 512 KB SRAM and 2 MB flash, the The MPC5675K is a Qorivva 32-bit components of the MCU (CPU core, DMA MPC567xK provides enough data handling controller, interrupt controller, crossbar bus headroom to manage these applications. system, memory protection unit, flash memory Additional peripherals such as quad ADC, DDR, and RAM controllers, peripheral bus bridge, PDI and FEC help at the system level. embedded MCU designed for automotive safety and chassis applications such as advanced driver assistance systems (ADAS) with radar, CMOS imaging, LIDAR and ultrasonic sensing functionality. system timers and watchdog timer). Lock step redundancy checking units are implemented at Additionally, there is a trend towards safety assessment for ADAS systems. The safety The MPC567xK MCU is part of the each output of this sphere of replication (SoR). SafeAssure program, which is designed A comprehensive suite of hardware and assists with assessment and a reduction to help system manufacturers more easily software development tools is available to of common faults. achieve compliance with functional safety help simplify and speed system design. standards. Part of the MPC5500/5600 Development support is available from leading family, the MPC5675K contains the Book E tool vendors, providing compilers, debuggers compliant core built on Power Architecture® and simulation development environments. technology with variable length encoding architecture of the Qorivva MPC567xK Development Tools Compilers Freescale CodeWarrior IDE (freescale.com/CodeWarrior) (VLE). This core complies with the Power Features Architecture embedded category, and is The Qorivva MPC567xK features a dual-core 100 percent user mode compatible with 180 MHz Qorivva MCU, with up to 2 MB the original PowerPC user instruction set flash and 512 KB SRAM, plus a feature set architecture. It offers system performance optimized for ADAS and chassis control up to four times that of its MPC5561 P&E Micro applications. Lauterbach The ADAS market is growing fast. As Green Hills Software predecessor, while bringing you the reliability and familiarity of proven Power Architecture technology. historically premium applications such as RADAR and camera-based assistance systems All devices in this family are built around a proliferate into the mid range, there is a need to dual-core safety platform with an innovative reduce system cost. safety concept targeting systems with ISO 26262, ASIL-D safety integrity levels. In order to minimize additional software and module level features to reach this target, MPC567xK has a decoupled parallel mode where the two e200 cores may be separated in order to run parallel processing tasks. Together Green Hills Software Wind River Diab Debuggers Runtime Software Flash and FEE drivers Software core self test AUTOSAR MCU Abstraction Layer AUTOSAR OS Specifications Features Type MPC5673K MPC5674K MPC5675K 2×e200z7d (SoR) in lock-step or decoupled operation Core Architecture • Up to 180 MHz Power Architecture Execution speed 0–150 MHz (+2% FM) 0–180 MHz (+2% FM) 0–180 MHz (+2% FM) Nominal platform frequency (in 1:1, 1:2, and 1:3 modes) 0–75 MHz (+2% FM) 0–90 MHz (+2% FM) 0–90 MHz (+2% FM) ISA dual e200z7 core • 16 KB D cache and 16 KB I cache CPU • Safety enhanced cores + SPE2 + MMU + HW/SW monitoring Buses • Up to 2 MB flash with ECC XBAR 16 KB, 4-way with EDC (SoR) Data cache 16 KB, 4-way with EDC (SoR) Memory Yes (SoR) Core bus 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data Master x slave ports Static RAM • 4 x 16 KB EEPROM flash with ECC Code flash memory Yes (SoR) 256 KB (ECC) 384 KB (ECC) 512 KB (ECC) 1 MB 1.5 MB 2 MB Data flash memory • Dual crossbar with MPUs Analog-to-digital converter I/O CRC unit • 4 x FlexCAN (32 message buffers each) Cross triggering unit • 1 x FlexRay (64 msg. buffers) Deserial serial peripheral interface • 1 x Fast Ethernet controller Digital I/Os • 4 x LINFlex (SCI) DRAM controller 64 KB2 257 pin pkg: 4 x 12-bit (22 external channels), 473 pin pkg: 4 x 12-bit (up to 34 external channels) Two (three contexts each) Two modules Two modules (three chip selects) • 3 x I C eTimer • 3 x DSPI External bus interface • 3 x FlexPWM (3 x 12 channels) Three modules (three chip selects) ≥16 No Yes Enhanced direct memory access 2 Two modules, 32 channels each Three modules, six channels each One module, 16-bit data + address or 32-bit data with address bus muxed Fast ethernet controller Modules • 2 x CTU One module Fault collection and control unit One module FlexCAN Four modules (32 message buffers each) FlexPWM Three modules (each 4 x 3 channels) FlexRay • External bus interface (slave only) I 2C • Parallel digital interface Interrupt controller • MDDR interface LINFlex SafeAssure Program: Functional Safety. Simplified Optional Two modules Three modules Yes (SoR) Three modules Four modules Parallel data interface One module Periodic interrupt timer One module, four channels Software watchdog timer Yes (SoR) System timer module Yes (SoR) Temperature sensor Freescale’s SafeAssure functional safety One module Wakeup unit program is designed to help system Crossbar switch manufacturers more easily achieve system Clock monitor unit compliance with functional safety standards: Clock output International Standards Organization (ISO) Yes Instruction cache MPU Memory • Quad ADC (11 channels each, 12-bit) Yes Instruction set VLE • Dual parallel or lock step configuration • 3 x eTimer (3 x 6 channels) 64 entries (SoR) Instruction set PPC VLE + MMU • Up to 512 KB SRAM with ECC Harvard Clocking 26262 and 61508. The program highlights Frequency-modulated phase-locked loop Yes Three modules, two are user-configurable Three modules Two modules Two modules (system and auxiliary) IRCOSC—16 MHz One XOSC 4 MHz–40 MHz One Freescale solutions—hardware and Power management unit Yes software—that are optimally designed 1.2V low-voltage detector (LVD12) One Supply to support functional safety 1.2V high-voltage detector (HVD12) One 2.7V low-voltage detector (LVD27) Four implementations and come with a rich Debug Nexus set of enablement collateral. Packages MAPBGA 257 pins, 473 pins Temperature Ambient See the TA recommended operating condition in the device data sheet For more information, visit Class 3+ (for cores and SRAM ports) freescale.com/SafeAssure. For more information, visit freescale.com/Qorivva Freescale, the Freescale logo and Qorivva are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SafeAssure and the SafeAssure logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © Freescale Semiconductor, Inc. 2012. All rights reserved. Document Number: MPC567XKUPDTFS / REV 0