SPC5676RDK3MVY1

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5676R Rev. 4, 16 Feb 2016 MPC5676R MPC5676R Microcontroller Data Sheet TEPBGA–416 27 mm x 27 mm On-chip modules available within the family include the following features: • Two identical dual issue, 32-bit CPU core complexes (e200z7), each with – Power Architecture embedded specification compliance – Instruction set enhancement allowing variable length encoding (VLE), optional encoding of mixed 16-bit and 32-bit instructions, for code size footprint reduction – Signal processing extension (SPE) instruction support for digital signal processing (DSP) – Single-precision floating point operations (FPU) – 16 KB I-Cache and 16 KB D-Cache – Hardware cache coherency between cores • 16 Hardware semaphores • 3 channel CRC module • 6MB on-chip flash – Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation • 384KB on-chip general-purpose SRAM including 48KB of standby RAM • Two multi-channel direct memory access controllers (eDMA) – 64 channels per eDMA • Dual core Interrupt controller (INTC) • Phase-locked loop with FM modulation (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters • External Bus Interface (EBI) for calibration and application development • System integration unit (SIU) with error correction status module (ECSM) • Four protected port output pins (PPO) • Boot assist module (BAM) supports serial bootload via CAN or SCI • Three second-generation enhanced time processor units (eTPU2) • • • • • • • • • • – Up to 96 eTPU2 channels (32 channels per eTPU2) – total of 36 KB code RAM – total of 9 KB parameter RAM Enhanced modular input output system supporting 32 unified channels (eMIOS) with each channel capable of single action, double action, pulse width modulation (PWM) and modulus counter operation Two enhanced queued analog-to-digital converter (eQADC) modules with – two separate analog converters per eQADC module – support for a total of 64 analog input pins, expandable to 176 inputs with off-chip multiplexers – one absolute reference ADC channel – interface to twelve hardware decimation filters – enhanced ‘Tap’ command to route any conversion to two separate decimation filters – Temperature sensor Five deserial serial peripheral interface (DSPI) modules Three enhanced serial communication interface (eSCI) modules Four controller area network (FlexCAN) modules Dual-channel FlexRay controller Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard. Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1) On-chip voltage regulator controller regulates supply voltage down to 1.2 V for core logic Self Test capability This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2016. All rights reserved. TEPBGA–516 27mm x 27mm Table of Contents 1 2 3 4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 MPC5676R Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.1 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6 3.2 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .7 3.3 Pin Muxing and Reset States . . . . . . . . . . . . . . . . . . . . .8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2.1 General Notes for Specifications at Maximum Junction Temperature . . . . . . . . . . . . 11 4.3 EMI (Electromagnetic Interference) Characteristics . . .12 4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .13 4.5.1 Regulator Example . . . . . . . . . . . . . . . . . . . . . .16 4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .18 4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.6.3 Power Sequencing and POR Dependent on VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .20 4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .23 4.7.2 I/O Pad VDD33 Current Specifications . . . . . . . 24 4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 25 4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 27 4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 29 4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 31 4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.11.1 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . 32 4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 33 4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 34 4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 35 4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 36 4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.12.5 External Bus Interface (EBI) Timing . . . . . . . . . 41 4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 46 4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.1 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6 Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 59 Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 MPC5676R Microcontroller Data Sheet, Rev. 4 2 Freescale Semiconductor Ordering Information 1 Ordering Information 1.1 Orderable Parts Figure 1 and Table 1describe and list the orderable part numbers for the MPC5676R. M PC 5676R D K2 M VU 1 R Qualification status Core code Device number (Optional) Dual-core identifier Fab/Revision Temperature range Package identifier Operating frequency Tape and reel status Temperature Range M = –40 °C to 125 °C Package Identifier VU = 416 TEPBGA Pb-Free VY = 516 TEPBGA Pb-Free Operating Frequency 1 = 2 x 180 MHz Tape and Reel Status R = Tape and reel (blank) = Trays Qualification Status P = Pre qualification M = Fully spec. qualified, general market flow S = Fully spec. qualified, automotive flow Note: Not all options are available on all devices. Refer to Table 1. Figure 1. MPC5676R Orderable Part Number Description Table 1. Orderable Part Numbers NXP Part Number1 Speed (MHz)2 Package Description Operating Temperature3 Nominal Max4 (fMAX) Min (TL) Max (TH) SPC5676RDK2MVU1R MPC5676R 416 package Lead-free (Pb-free) 180 184 –40 °C 125 °C SPC5676RDK2MVY1R MPC5676R 516 package Lead-free (Pb-free) 180 184 –40 °C 125 °C 1 All packaged devices are PPC5676R, rather than MPC5676R or SPC5676R, until product qualifications are complete. The unpackaged device prefix is PCC, rather than SCC, until product qualification is complete. Not all configurations are available in the PPC parts. 2 For the operating mode frequency of various blocks on the device, see Table 28. 3 The lowest ambient operating temperature is referenced by TL; the highest ambient operating temperature is referenced by TH. 4 Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 180 MHz parts allow for 180 MHz system clock + 2% FM. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 3 MPC5676R Blocks 2 MPC5676R Blocks 2.1 Block Diagram The following figure shows a top-level block diagram of the MPC5676R. The purpose of the block diagram is to show the general interconnection of functional modules through the crossbar switch and from the Dual Interrupt Controller, and provide an indication of the modules that connect to external pins. For clarity, the following modules are omitted from the diagram: PMU, SWT, STM, PIT, ECSM, DTS, and CRC. MPC5676R Power Architecture e200z7 Core Power Architecture e200z7 Core SPE SPE VLE VLE MMU MMU Dual Interrupt Controller eDMA2 64 Channels eDMA2 64 Channels 16K I-Cache 16K I-Cache 16K D-Cache JTAG Nexus IEEE-ISTO 5001-2003 16K D-Cache EBI (Calibration) FlexRay Crossbar Switch MPU FlexCAN FlexCAN FlexCAN FlexCAN DSPI DSPI eTPU2 32 Channel Semaphores Boot Assist Module eQADC eQADC 12 x DECFILT PPO ADC ADC 12KB Code RAM SIUB I/O BridgeB DSPI DSPI 3KB Data RAM 384KB SRAM (48KB S/B) FMPLL ADC ADC 24KB Code RAM eTPU2 32 Channel STCU DSPI eMIOS eTPU2 32 32 Channel Channel 6KB Data RAM I/O BridgeA eSCI eSCI eSCI 6MB SIUA FLASH AMux LEGEND ADC – Analog to Digital Convertor AMux – Analog Pin Multiplexer D-Cache – Data Cache DECFILT– Decimation Filter DSPI – Deserial/Serial Peripheral Interface EBI – External Bus Interface eDMA2 – Enhanced Direct Memory Access controller version 2 eMIOS – Enhanced Modular I/O System eQADC – Enhanced Queued Analog to Digital Converter eSCI – Enhanced Serial Communications Interface eTPU2 – Enhanced Time Processing Unit version 2 FlexCAN– Flexible Controller Area Network controller FMPLL – Frequency Modulated Phase Lock Loop clock generator I-Cache IRC JTAG MMU MPU PPO S/B SIUA SIUB SPE SRAM STCU VLE – Instruction Cache – Internal RC Oscillator – Joint Test Action Group controller – Memory Management Unit – Memory Protection Unit – Protected Port Output – Stand-by – System Integration Unit A – System Integration Unit B – Signal Processing Engine – Static RAM – Self Test Control Unit – Variable Length instruction Encoding Figure 2. MPC5676R Block Diagram MPC5676R Microcontroller Data Sheet, Rev. 4 4 Freescale Semiconductor Pin Assignments 3 Pin Assignments 3.1 416-ball TEPBGA Pin Assignments Figure 3 shows the 416-ball TEPBGA pin assignments. CAUTION This ball map is preliminary and subject to change. Do not use it for board design. 1 A VSS 2 3 4 VDD RSTOUT ANA0 5 ANA4 6 7 8 9 10 11 ANA8 VDD TEST ANA1 ANA5 REF– ANA10 ANA14 VDDA_A1 VSSA_A1 BYPCA C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 B VDDEH1 VSS 12 REF– VRL_A VRH_A ANA11 ANA15 VDDA_A0 BYPCA1 13 AN28 14 15 16 17 18 19 20 21 22 23 24 25 AN32 AN36 VDDA_B0 REF– VRL_B VRH_B ANB7 BYPCB1 ANB11 ANB14 ANB17 ANB21 ANB23 ANB8 ANB10 ANB15 ANB18 ANB22 AN24 AN27 AN29 AN33 VDDA_B1 VSSA_B0 REF– ANB6 BYPCB ANA9 ANA13 ANA17 ANA19 ANA21 ANA23 AN26 AN30 AN34 AN37 AN38 ANB0 ANB4 ANB5 ANB12 ANB16 ANB19 ANA7 ANA12 ANA16 ANA18 ANA20 ANA22 AN25 AN31 AN35 AN39 ANB1 ANB2 ANB3 ANB9 ANB13 ANB20 VSS 26 VSS A VSS TCRCLKC B ETPUC0 ETPUC1 C VSS VDDEH7 ETPUC2 ETPUC3 D VDDEH7 ETPUC4 ETPUC5 ETPUC6 E E ETPUA23 ETPUA24 ETPUA25 ETPUA26 ETPUC7 ETPUC8 ETPUC9 ETPUC10 F F ETPUA19 ETPUA20 ETPUA21 ETPUA22 MPC5676R 416-ball TEPBGA G ETPUA15 ETPUA16 ETPUA17 ETPUA18 ETPUC11 ETPUC12 ETPUC13 ETPUC14 G (as viewed from top through the package) H ETPUA11 ETPUA12 ETPUA14 ETPUA13 ETPUC15 ETPUC16 ETPUC17 ETPUC18 H J ETPUA7 ETPUA8 ETPUA9 ETPUA10 ETPUC19 ETPUC20 ETPUC21 ETPUC22 J K ETPUA3 ETPUA4 ETPUA5 ETPUA6 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC23 ETPUC24 ETPUC25 ETPUC26 K L TCRCLKA ETPUA0 ETPUA1 ETPUA2 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC27 ETPUC28 ETPUC29 ETPUC30 L M VDD33_1 TXDA VSS VSS VSS VSS VSS VSS VSS VSS ETPUC31 ETPUB15 ETPUB14 VDDEH7 M VDDE2 VSS VSS VSS VSS VSS VSS VSS VDDEH6 ETPUB11 ETPUB12 ETPUB13 N N RXDB RXDA VSTBY BOOT– CFG1 WKPCFG VDD P TXDB PLLCFG1 PLLCFG2 VDDEH1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB7 ETPUB8 ETPUB9 ETPUB10 P R JCOMP RESET PLLCFG0 RDY VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS ETPUB3 ETPUB4 ETPUB5 ETPUB6 R T VDDE2 MCKO MSEO1 EVTI VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS TCRCLKB ETPUB0 ETPUB1 ETPUB2 T U EVTO MSEO0 MDO0 MDO1 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB19 ETPUB18 ETPUB17 ETPUB16 U V MDO2 MDO3 MDO4 MDO5 ETPUB26 ETPUB22 ETPUB21 ETPUB20 V W MDO6 MDO7 MDO8 VDDE2 REGSEL ETPUB25 ETPUB24 ETPUB23 W Y MDO9 MDO10 MDO11 MDO15 ETPUB29 ETPUB28 ETPUB27 REGCTL Y AA MDO12 MDO13 MDO14 VDD33_2 VDD33_3 ETPUB30 VDDREG VSSSYN AA TDO TCK TMS VDD TDI VDD VSS AD ENGCLK VDD VSS AB AC VDDE2 AE AF VDD VSS 1 VSS VDD ETPUB31 VSSFL EXTAL AB VDDE2 PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4 VDD FR_A_ FR_B_ EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNTXD SCKC TX TX PCSA5 SOUTA SCKA PCSB0 PCSB3 EMIOS2 FR_A_ FR_B_ PCSA4 PCSA0 PCSA3 SCKB RX RX FR_A_ FR_B_ VDDE2 TX_EN TX_EN VDDEH3 PCSB5 2 3 EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1 4 5 6 SINA 7 SINB EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0 VSS RXDC PCSC3 SINC VDD VDDEH6 XTAL AC VSS PCSC2 PCSC5 VDD VDDSYN AD VSS VDD AE PCSB2 SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA CNTXC SOUTC VDDEH4 TXDC PCSC4 VDDEH5 VSS AF 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 3. MPC5676R 416-ball TEPBGA (full diagram) MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 5 Pin Assignments 3.2 516-ball TEPBGA Pin Assignments Figure 4 shows the 516-ball TEPBGA pin assignments. 5 6 A 1 VDD RSTOUT ANA0 2 3 4 ANA4 ANA9 ANA11 ANA15 VDDA_A0 7 8 9 10 B VDDEH1 VSS 11 12 13 14 AN28 AN29 AN36 VDDA_B0 AN24 AN27 AN30 AN32 VDDA_B1 VSSA_B0 REF– BYPCB REF– VRL_A VRH_A BYPCA1 15 16 17 18 19 20 21 ANB5 ANB9 ANB12 ANB18 ANB21 VSS ANB4 ANB8 ANB10 ANB13 ANB19 ANB22 VSS ANB11 REF– VRL_B VRH_B BYPCB1 22 VDD TEST ANA1 ANA5 ANA10 ANA14 VDDA_A1 VSSA_A1 REF– BYPCA C ETPUA30 ETPUA31 VSS VDD ANA2 ANA6 ANA7 ANA13 ANA17 ANA19 ANA21 ANA22 AN25 AN31 AN34 AN39 AN37 ANB0 ANB7 ANB6 D ETPUA27 ETPUA28 ETPUA29 VSS VDD ANA3 ANA8 ANA12 ANA16 ANA18 ANA20 ANA23 AN26 AN33 AN35 AN38 ANB1 ANB2 ANB3 ANB14 ANB16 ANB17 E ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS VDD VSS VSS VSS VSS VSS VSS VSS VSS ANB23 F ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS VDDE8 VSS VSS VSS VSS VDDE8 VSS VSS VSS VDDE8 VDDE8 VDDE10 VDDE10 VSS H ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16 ANB15 ANB20 VSS VSS 24 VSS 25 26 A VSS B ETPUC0 ETPUC1 C VDDEH7 ETPUC2 ETPUC3 D VDDEH7 ETPUC4 ETPUC5 ETPUC6 E VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10 F VDDE10 MPC5676R 516-ball TEPBGA G ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18 23 ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15 G ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21 H (as viewed from top through the package) ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27 J J ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12 RXDA TCRCLKA ETPUA6 ETPUA10 VSS VSS VSS VSS VSS VSS VSS VSS ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15 K BOOT– BOOT– L PLLCFG1 PLLCFG2 CFG1 CFG0 RXDB ETPUA0 VSS VSS VSS VSS VSS VSS VSS VSS VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10 L M VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG VSS VSS VSS VSS VSS VSS VSS VSS D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7 M VDDE2 VSS VSS VSS VSS VSS VSS VSS VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4 N VDDE10 ETPUB13 D_OE K TXDB TXDA N D_WE0 D_WE2 D_WE3 VDD RESET VDDE8 D_ALE D_DAT0 D_DAT1 P P D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS R D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS T VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11 T U D_CS2 JCOMP RDY MCKO MSEO1 MSEO0 VDDE2 VDDE2 VDDE2 VSS VSS VSS VSS VSS ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6 U V MDO2 EVTI EVTO MDO0 W MDO4 MDO5 MDO6 VDDE2 MDO8 Y MDO7 MDO9 MDO10 MDO11 MDO12 TDO TCK TMS VDD TDI VDD VSS AD ENGCLK VDD VSS AC VDDE2 AE VDD VSS VSS ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18 W MDO1 ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL Y VSS 1 2 VDDE9 VDDE9 SCKA VDDE2 PCSA1 SOUTA SCKB SINB VDDE9 VDD33_4 CNRXB EMIOS23 EMIOS31 VSS D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9 PCSB3 VDDEH3 VDDEH4 VDD SINA PCSB1 4 5 6 7 8 VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA VSS EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1 FR_A_ FR_B_ PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD SCKC TX TX FR_A_ FR_B_ PCSA4 PCSB5 RX RX 3 SOUTB VDD33_4 PCSA5 FR_A_ FR_B_ VDDEH3 PCSA2 PCSB4 PCSB0 VDDE2 TX_EN TX_EN AF D_RD_ WR R ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0 V MDO3 AA MDO13 MDO14 MDO15 VDD33_1 VDDE8 AB ETPUB9 ETPUB12 ETPUB14 ETPUB15 D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0 VDD ETPUB30 VSSFL EXTAL AB VSS RXDC PCSC3 SINC 10 11 12 13 14 15 16 17 18 19 20 21 22 VSS PCSC2 PCSC5 D_ D_TA D_ADD24 D_ADD27 CLKOUT EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC 9 VDD VDDEH6 XTAL 23 VDD VDDSYN AD VSS VDD PCSC4 VDDEH5 24 AC 25 AE AF 26 Figure 4. MPC5676R 516-ball TEPBGA (full diagram) MPC5676R Microcontroller Data Sheet, Rev. 4 6 Freescale Semiconductor Electrical Characteristics 3.3 Pin Muxing and Reset States See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties. 4 Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5676R. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. 4.1 Maximum Ratings Table 2. Absolute Maximum Ratings1 Spec Characteristic 1 1.2 V Core Supply Voltage3 2 SRAM Standby Voltage Symbol Min Max2 Unit VDD –0.3 1.65 4 V VSTBY –0.3 5.5 5,6 V VDDSYN –0.3 4.5 6,7 V 3 Clock Synthesizer Voltage 4 I/O Supply Voltage (I/O buffers and predrivers) VDD33 –0.3 4.5 6,7 V 5 Analog Supply Voltage (reference to VSSA8) VDDA9 –0.3 5.5 5,6 V 6 I/O Supply Voltage (fast I/O pads) VDDE –0.3 4.5 6 V 7 I/O Supply Voltage (medium I/O pads) VDDEH –0.3 5.5 5,6 V 8 Voltage Regulator Input Supply Voltage VDDREG –0.3 5.55,6 V 9 Analog Reference High Voltage (reference to VRL10) VRH11 –0.3 5.5 5,6 V 10 VSS to VSSA8 Differential Voltage VSS – VSSA –0.1 0.1 V 11 VREF Differential Voltage VRH – VRL –0.3 5.5 5,6 V 12 VRL to VSSA Differential Voltage VRL – VSSA –0.3 0.3 V 13 VDD33 to VDDSYN Differential Voltage VDD33 – VDDSYN –0.1 0.1 V 14 VSSSYN to VSS Differential Voltage VSSSYN – VSS –0.1 0.1 V 13 13 12 (per pin, applies to all 15 Maximum Digital Input Current digital pins) 16 Maximum Analog Input Current 14 (per pin, applies to all analog pins) IMAXD IMAXA –3 –3 9,13 3 3 9,13 mA mA MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 7 Electrical Characteristics Table 2. Absolute Maximum Ratings1 (continued) Spec Characteristic Symbol Min Max2 17 Maximum Operating Temperature Range 15 – Die Junction Temperature TJ –40.0 150.0 o 18 Storage Temperature Range Tstg –55.0 150.0 o 19 Maximum Solder Temperature 16 Pb-free package SnPb package Tsdr Moisture Sensitivity Level 17 MSL 20 Unit C C o C — — 260.0 245.0 — 3 — 1 Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. 3 1.2 V ±10% for proper operation. This parameter is specified at a maximum junction temperature of 150 °C. 4 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 5 6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining. 6 Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 7 4.5 V for 10 hours cumulative time, 3.3 V +10% for time remaining. 8 MPC5676R has two analog power supply pins on the pinout: VDDA_A and VDDA_B. 9 MPC5676R has two analog ground supply pins on the pinout: VSSA_A and VSSA_B. 10 MPC5676R has two analog low reference voltage pins on the pinout: VRL_A and VRL_B. 11 MPC5676R has two analog high reference voltage pins on the pinout: VRH_A and VRH_B. 12 Total injection current for all pins must not exceed 25 mA at maximum operating voltage. 13 Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or VDDEH supply when under this stress condition. 14 Total injection current for all analog input pins must not exceed 15 mA. 15 Lifetime operation at these specification limits is not guaranteed. 16 Solder profile per CDF-AEC-Q100. 17 Moisture sensitivity per JEDEC test method A112. 4.2 Thermal Characteristics Table 3. Thermal Characteristics, 416-pin TEPBGA Package1 Characteristic Symbol Value Unit Junction to Ambient 2,3 Natural Convection (Single layer board) RJA 24 °C/W Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) RJA 16 °C/W RJMA 18 °C/W Junction to Ambient (@200 ft./min., Single layer board) MPC5676R Microcontroller Data Sheet, Rev. 4 8 Freescale Semiconductor Electrical Characteristics Table 3. Thermal Characteristics, 416-pin TEPBGA Package1 (continued) Characteristic Junction to Ambient (@200 ft./min., Four layer board 2s2p) Junction to Board 5 Junction to Case 6 Junction to Package Top 7 Natural Convection 1 2 3 4 5 6 7 Symbol Value Unit RJMA 13 °C/W RJB 8 °C/W RJC 4 °C/W JT 3 °C/W Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. Table 4. Thermal Characteristics, 516-pin TEPBGA Package1 Characteristic 1 2 3 4 5 6 Symbol Value Unit Junction to Ambient 2,3 Natural Convection (Single layer board) RJA 24 °C/W Junction to Ambient 2,4 Natural Convection (Four layer board 2s2p) RJA 17 °C/W Junction to Ambient (@200 ft./min., Single layer board) RJMA 19 °C/W Junction to Ambient (@200 ft./min., Four layer board 2s2p) RJMA 14 °C/W Junction to Board 5 RJB 9 °C/W Junction to Case 6 RJC 5 °C/W Junction to Package Top 7 Natural Convection JT 2 °C/W Thermal characteristics are targets based on simulation that are subject to change per device characterization. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 9 Electrical Characteristics 7 4.2.1 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. General Notes for Specifications at Maximum Junction Temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJA * PD) Eqn. 1 where: TA = ambient temperature for the package (oC) RJA = junction to ambient thermal resistance (oC/W) PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA Eqn. 2 where: RJA = junction to ambient thermal resistance (oC/W) RJC = junction to case thermal resistance (oC/W) RCA = case to ambient thermal resistance (oC/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) Eqn. 3 where: TT = thermocouple temperature on top of the package (oC) JT = thermal characterization parameter (oC/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. MPC5676R Microcontroller Data Sheet, Rev. 4 10 Freescale Semiconductor Electrical Characteristics References: Semiconductor Equipment and Materials International 3081 Zanker Road San Jose, CA 95134 (408) 943-6900 MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC specifications are available on the WEB at http://www.jedec.org. • • • C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic Packaging and Production, pp. 53-58, March 1998. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220. 4.3 EMI (Electromagnetic Interference) Characteristics To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go to www.nxp.com and perform a keyword search for “radiated emissions.” The following tables list the values of the device's radiated emissions operating behaviors. Table 5. EMC Radiated Emissions Operating Behaviors: 416 BGA Symbol VRE_TEM VRE_TEM 1 2 3 4 5 Description Radiated emissions, electric field and magnetic field Radiated emissions, electric field and magnetic field fOSC fSYS Frequency band (MHz) Level (max.) VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 °C 416 BGA EBI off CLK off FM off 40 MHz crystal 180 MHz (fEBI_CAL = 46 MHz) 0.15–50 26 50–150 30 150–500 34 500–1000 30 IEC and SAE level VDD = 1.2 V VDDE = 3.3 V VDDEH = 5 V TA = 25 °C 416 BGA EBI off CLK off FM on4 40 MHz crystal 180 MHz (fEBI_CAL = 46 MHz) Conditions Unit Notes dBV 1 I2 — 1, 3 0.15–50 24 dBV 1 50–150 25 150–500 25 500–1000 21 IEC and SAE level K5 — 1,3 Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. I = 36 dBV Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM (GTEM) Cell Method. “FM on” = FM depth of ±2% K = 30 dBV MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 11 Electrical Characteristics 4.4 ESD Characteristics Table 6. ESD Ratings1,2 Spec Characteristic Symbol Value Unit 1 ESD for Human Body Model (HBM) VHBM 2000 V 2 ESD for Charged Device Model (CDM) VCDM 750 (corners) 500 (other) V 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 4.5 PMC/POR/LVI Electrical Specifications Table 7. PMC Operating conditions Spec Name 1 VDDREG 2 Parameter Condition Min Typ Max Unit Supply voltage VDDREG LDO5V / SMPS5V mode 5 V nominal1 4.5 5 5.5 V VDDREG Supply voltage VDDREG LDO3V mode 3 V nominal1 3.0 3.3 3.6 V 3 VDD33 Supply voltage VDDSYN / LDO3V mode VDD33 3.3 V nominal2 3.0 3.3 3.6 V 4 VDD Supply voltage VDD 1.2 V nominal3 1.14 1.2 1.32 V — 1 Voltage should be higher than maximum VLVDREG to avoid LVD event Applies to both VDD33 (flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum VLVD33 to avoid LVD event 3 Voltage should be higher than maximum V LVD12 to avoid LVD event 2 NOTE In the following table, “untrimmed” means “at reset” and “trimmed” means “after reset”. Table 8. PMC Electrical Specifications Spec Name Symbol Condition Min Typ Max Unit 1 Nominal bandgap reference voltage VBG — 0.59 0.620 0.65 V 1a Bandgap reference voltage during power on reset — — VBG – 5% VBG VBG + 5% V 1b Bandgap reference voltage at nominal voltage / nominal temperature after power on reset — — VBG – 2% VBG VBG + 2% V MPC5676R Microcontroller Data Sheet, Rev. 4 12 Freescale Semiconductor Electrical Characteristics Table 8. PMC Electrical Specifications Spec Name Symbol Condition Min Typ Max Unit ppm/C 1c Bandgap reference voltage / temperature dependence after power on reset — — — 300 — 1d Bandgap reference voltage / voltage dependence (VDDREG) after power on reset — — — 1500 — 2 Nominal VRC regulated 1.2V output VDD1 VDD12OUT — — 1.2 — 2a VRC 1.2V output variation at reset (unloaded)2 — At POR VDD12OUT – 8% VDD12OUT VDD12OUT + 10% 2b VRC 1.2V output variation after reset(REGCTL load max. 20mA, VDD load max. 1A) — After POR VDD12OUT – 5% VDD12OUT VDD12OUT + 10% 2c Trimming step Vdd1p2 VSTEPV12 — — 10 — mV 3 POR rising VDD 1.2V VPORC — - 0.7 — V 3a POR VDD 1.2V variation — — VPORC – 30% VPORC VPORC + 30% 3b POR 1.2V hysteresis — — — 75 — mV 4 Nominal rising LVD 1.2V3 VLVD12 — — 1.100 — V 4a LVD 1.2V variation before band gap trim4 — At POR VLVD12 – 6% VLVD12 VLVD12 + 6% 4b LVD 1.2V variation after band gap trim4 — After POR VLVD12 – 3% VLVD12 VLVD12 + 3% 4c LVD 1.2V Hysteresis — — 15 20 25 mV 4d Trimming step LVD 1.2V VLVDSTEP12 — — 10 — mV 5 VRC 1.2V max DC output current IREGCTL — — — 20 mA 6 Voltage regulator 1.2V current consumption VDDREG — — — 3 — mA 7 Nominal Vreg 3.3V output5 VDD33OUT — — 3.3 — V 7a Vreg 3.3V output variation at reset (unloaded)6 — At POR VDD33OUT – 6% VDD33OUT VDD33OUT + 10% 7b Vreg 3.3V output variation after reset (max. load 60mA) — After POR VDD33OUT – 5% VDD33OUT VDD33OUT + 10% 7c Trimming step VDDSYN VSTEPV33 — — 30 — mV 8 Nominal rising LVD 3.3V7 VLVD33 — — 2.950 — V 8a LVD 3.3V variation before band gap trim6 — At POR VLVD33 – 5% VLVD33 VLVD33 + 5% 8b LVD 3.3V variation after bad gap trim6 — After POR VLVD33 – 3% VLVD33 VLVD33 + 3% V MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 13 Electrical Characteristics Table 8. PMC Electrical Specifications Spec Name Symbol Condition Min Typ Max Unit — — — 30 — mV VLVDSTEP33 — — 30 — mV 8c LVD 3.3V Hysteresis 8d Trimming step LVD 3.3V 9 Vreg 3.3V minimum peak DC output current supplied by regulator without causing VLVD338 IDD33 — 60 — — mA 10 Voltage regulator 3.3V current consumption VDDREG9 — — — 2 — mA 11 POR rising on VDDREG VPORREG — — 2.00 — V 11a POR VDDREG variation — — 11b POR VDDREG hysteresis — — — 250 — mV 12 Nominal rising LVD VDDREG VLVDREG LDO3V / LDO5V mode — 2.950 — V 12a LVD VDDREG variation at reset10 — At POR VLVDREG – 5% VLVDREG VLVDREG + 5% 12b LVD VDDREG variation after reset10 — After POR VLVDREG – 3% VLVDREG VLVDREG + 3% 12c LVD VDDREG Hysteresis — LDO3V / LDO5V mode — 30 — mV 12d Trimming step LVD VDDREG VLVDSTEPREG LDO3V / LDO5V mode — 30 — mV 13 Nominal rising LVD VDDREG VLVDREG SMPS5V mode — 4.360 — V 13a LVD VDDREG variation at reset10 — At POR VLVDREG – 5% VLVDREG VLVDREG + 5% 13b LVD VDDREG variation after reset10 — After POR VLVDREG – 3% VLVDREG VLVDREG + 3% 14 SMPS regulator output resistance11 — — — 15 25 Ohm 15 SMPS regulator clock frequency — After POR 1.0 1.5 — MHz 16 SMPS regulator overshoot at start-up12 — GBD/GBC13 — 1.32 1.4 V 17 SMPS maximum output current, as required by SoC14 — — — 1.0 — A 18 Voltage variation on current step (20% to 80% of maximum current with 4 usec constant time)14 — GBD/GBC13 — — 0.1 V VPORREG – 30% VPORREG VPORREG + 30% MPC5676R Microcontroller Data Sheet, Rev. 4 14 Freescale Semiconductor Electrical Characteristics 1 Nominal internal regulator output voltage is 1.27V Voltage should be higher than maximum VLVD12 to avoid LVD event 3 ~VDD12OUT *0.87 4 Rising VDD 5 Nominal internal regulator output voltage is 3.4V 6 Rising VDDSYN 7 ~VDD33OUT *0.872 8 VDDSYN 9 Except IDD33 10 Rising VDDREG 11 Pull up to VDDREG when high, pull down to VSSREG when low. 12 Depends on external device, can be as high as 1.6V for short time ( 40 MHz C3225X7R1E106M capacitor 22 uF — 25 V TDK high capacitance ceramic SMD (on VDD close to coil) C3225X7R1E225K capacitor C3225X7R1E106M 4.6 From 0.4V to 0.6 V 2 to 6 x 2.2 uF — 25 V TDK ceramic SMD (on VDD close to MCU) capacitor 6 x 0.1 uF — 20 V Ceramic -One capacitor for each VDD pin capacitor 22 uF — 25 V Supply decoupling cap—close to n-MOS drain resistor 20 K Pull down for power n—MOS gate Power Up/Down Sequencing There is no power sequencing required among power sources during power up and power down in order to operate within specification as long as the following two rules are met: • • When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG. When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the internal 3.3V regulator. The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up each VDDE/VDDEH first and then power up VDD. For power down, drop VDD to 0 V first, and then drop all VDDE/VDDEH supplies. There is no limit on the fall time for the power supplies. Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc., the state of the I/O pins during power up/down varies according to Table 11 and Table 12. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 17 Electrical Characteristics Table 11. Power Sequence Pin States for MH and AE pads 1 VDD VDD33 VDDE MH Pad MH+LVDS Pads1 AE/up-down Pads High High High Normal operation Normal operation Normal operation — Low High Pin is tri-stated (output buffer, input buffer, and weak pulls disabled) Outputs driven high Pull-ups enabled, pull-downs disabled Low High Low Output low, pin unpowered Outputs disabled Output low, pin unpowered Low High High Pin is tri-stated (output buffer, input buffer, and weak pulls disabled) Outputs disabled Pull-ups enabled, pull-downs disabled MH+LVDS pads are output-only. Table 12. Power Sequence Pin States for F and FS pads 1 4.6.1 VDD VDD33 VDDE F and FS pads low low high Outputs drive high low high — Outputs Disabled high low low Outputs Disabled high low high Outputs drive high high high low Normal operation - except no drive current and input buffer output is unknown.1 high high high Normal Operation The pad pre-drive circuitry will function normally but since VDDE is unpowered the outputs will not drive high even though the output pmos can be enabled. Power-Up If VDDE/VDDEH is powered up first, then a threshold detector tristates all drivers connected to VDDE/VDDEH. There is no limit to how long after VDDE/VDDEH powers up before VDD must power up. If there are multiple VDDE/VDDEH supplies, they can be powered up in any order. For each VDDE/VDDEH supply not powered up, the drivers in that VDDE/VDDEH segment exhibit the characteristics described in the next paragraph. If VDD is powered up first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDD powers up before VDDE/VDDEH must power up. The rise times on the power supplies are to be no faster than 25 V/millisecond. 4.6.2 Power-Down If VDD is powered down first, then all drivers are tristated. There is no limit to how long after VDD powers down before VDDE/VDDEH must power down. If VDDE/VDDEH is powered down first, then all pads are loaded through the drain diodes to VDDE/VDDEH. This presents a heavy load that pulls the pad down to a diode above VSS. Current injected by external devices connected to the pads must meet the current injection specification. There is no limit to how long after VDDE/VDDEH powers down before VDD must power down. MPC5676R Microcontroller Data Sheet, Rev. 4 18 Freescale Semiconductor Electrical Characteristics There are no limits on the fall times for the power supplies. 4.6.3 Power Sequencing and POR Dependent on VDDA During power up or down, VDDA can lag other supplies (of magnitude greater than VDDEH/2) within 1 V to prevent any forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between VDDA and VDDEH is more than 1 V, the following will result: • • • • 4.7 Triggers POR (ADC monitors on VDDEH1 segment which powers the RESET pin) if the leakage current path created, when VDDA is sufficiently low, causes sufficient voltage drop on VDDEH1 node monitored crosses low-voltage detect level. If VDDA is between 0–2 V, powering all the other segments (especially VDDEH1) will not be sufficient to get the part out of reset. Each VDDEH will have a leakage current to VDDA of a magnitude of ((VDDEH – VDDA – 1 V(diode drop)/200 KOhms) up to (VDDEH/2 = VDDA + 1 V). . Each VDD has the same behavior; however, the leakage will be small even though there is no current limiting resistor since VDD = 1.32 V max. DC Electrical Specifications Table 13. DC Electrical Specifications1 Spec Characteristic Symbol Min Max Unit 1 Core Supply Voltage (External Regulation) VDD 1.14 1.322, 3 V 1a Core Supply Voltage (Internal Regulation)4 VDD 1.08 1.32 V 2 I/O Supply Voltage (fast I/O pads) VDDE 3.0 3.62 V 3 I/O Supply Voltage (medium I/O pads) VDDEH 3.0 5.252 V 4 3.3 V I/O Buffer Voltage VDD33 3.0 3.62 V 5 Analog Supply Voltage VDDA 4.75 5.252 V 6a SRAM Standby Voltage low range VSTBY_LOW 0.955 1.2 V 6b SRAM Standby Voltage high range VSTBY_HIGH 2 6 V 7 Voltage Regulator Control Input Voltage6 VDDREG 2.77 5.52 V 8 Clock Synthesizer Operating Voltage8 VDDSYN 3.0 3.62 V 9 Fast I/O Input High Voltage Hysteresis enabled Hysteresis disabled VIH_F VDDE + 0.3 V Fast I/O Input Low Voltage Hysteresis enabled Hysteresis disabled VIL_F Medium I/O Input High Voltage Hysteresis enabled Hysteresis disabled VIH_S 10 11 0.65 × VDDE 0.55 × VDDE VSS – 0.3 V 0.35 × VDDE 0.40 × VDDE VDDEH + 0.3 V 0.65 × VDDEH 0.55 × VDDEH MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 19 Electrical Characteristics Table 13. DC Electrical Specifications1 (continued) Spec 12 Characteristic Medium I/O Input Low Voltage Hysteresis enabled Hysteresis disabled Symbol Min VIL_S VSS – 0.3 Max Unit V 0.35 × VDDEH 0.40 × VDDEH 13 Fast I/O Input Hysteresis VHYS_F 0.1 × VDDE — V 14 Medium I/O Input Hysteresis VHYS_S 0.1 × VDDEH — V 15 Analog Input Voltage VINDC VSSA – 0.1 VDDA + 0.1 V 9 16 Fast I/O Output High Voltage VOH_F 0.8 × VDDE — V 17 Medium I/O Output High Voltage10 VOH_S 0.8 × VDDEH — V 18 Fast I/O Output Low Voltage9 VOL_F — 0.2 × VDDE V 19 Medium I/O Output Low Voltage VOL_S — 0.2 × VDDEH1 V 0 0.15 × VDDEH 11 Load Capacitance (Fast I/O)12 DSC(PCR[8:9]) = 0b00 DSC(PCR[8:9]) = 0b01 DSC(PCR[8:9]) = 0b10 DSC(PCR[8:9]) = 0b11 CL 21 Input Capacitance (Digital Pins) 22 20 — — — — 10 20 30 50 pF pF pF pF CIN — 7 pF Input Capacitance (Analog Pins) CIN_A — 10 pF 23 Input Capacitance (Digital and Analog Pins13) CIN_M — 12 pF 24 Operating Current 1.2 V Supplies @ fsys = 180 MHz VDD (including VDDF current)@1.32 V VSTBY14 @1.2 V and 85oC VSTBY @6.0 V and 85oC VDDF15 (P/E) VDDF15 (Read) VDDF15 (RWW) VDDF15 (Standby) VDDF15 (Disabled) IDD — — — — — — — — 1.016 0.10 0.15 3617 5017 9017 0.2017 0.1017 A mA mA mA mA mA mA mA note18 720 3221 6.421 4021 3.421 0.1021 mA mA mA mA mA mA mA 5022 1.0 22 mA mA mA 25 26 IDDSTBY IDDSTBY6 IDDFPE IDDFREAD IDDFRWW IDDplTANDBY IDDFDISABLED Operating Current 3.3 V Supplies @ fsys = 180 MHz VDD3318 VDDSYN VFLASH19 (P/E) VFLASH19 (Read) VFLASH19 (RWW) VFLASH19 (Standby) VFLASH19 (Disabled) IDDFLASHSTANDBY IDDFLASHDISABLED — — — — — — — Operating Current 5.0 V Supplies @ fsys = 180 MHz VDDA Analog Reference Supply Current (Transient) VDDREG IDDA IREF IREG — — — IDD33 IDDSYN IDDFLASHPE IDDFLASHREADS IDDFLASHRWW MPC5676R Microcontroller Data Sheet, Rev. 4 20 Freescale Semiconductor Electrical Characteristics Table 13. DC Electrical Specifications1 (continued) Spec 27 28 29 Characteristic Operating Current VDDE/VDDEH23 Supplies VDDE2 VDDEH1 VDDEH3 VDDEH4 VDDEH5 VDDEH6 VDDEH7 Fast I/O Weak Pull Up/Down Current24 3.0 V–3.6 V Medium I/O Weak Pull Up/Down Current25 3.0 V–3.6 V 4.5 V–5.5 V 30 I/O Input Leakage Current26 31 DC Injection Current (per pin) 32 Analog Input Current, Channel Off27, AN[0:7], AN38, AN39 Analog Input Current, Channel Off, all other analog inputs AN[x] = -/+ 150nA Symbol Min Max Unit IDD2 IDD1 IDD3 IDD4 IDD5 IDD6 IDD7 — — — — — — — note23 mA mA mA mA mA mA mA IACT_F 42 158 A 15 35 95 200 A A IINACT_D –2.5 2.5 A IIC –1.0 1.0 mA IINACT_A –250 250 nA –150 150 nA VSS – VSSA –100 100 mV VRL VSSA VSSA + 100 mV VRL – VSSA –100 100 mV VRH VDDA – 100 VDDA mV VRH – VRL 4.75 5.25 V VSSSYN – VSS –100 100 mV TA (TL to TH) –40.0 125.0 C — — 25 V/ms IACT_S 33 VSS Differential Voltage 34 Analog Reference Low Voltage 35 VRL Differential Voltage 36 Analog Reference High Voltage 37 VREF Differential Voltage 38 VSSSYN to VSS Differential Voltage 39 Operating Temperature Range—Ambient (Packaged) 40 Slew rate on power supply pins 41 Weak Pull-Up/Down Resistance28,29 200 k Option RPUPD200K 130 280 k 42 Weak Pull-Up/Down Resistance28,29 100 k Option RPUPD100K 65 140 k 43 Weak Pull-Up/Down Resistance28 (5 k Option) 5 V ± 10% supply 3.3 V ± 10% supply 1.4 1.7 5.2 7.7 –2.5 2.5 44 Pull-Up/Down Resistance Matching Ratios (100K/200K) (Pull-up and pull-down resistances both enabled and settings are equal) RPUPD5K RPUPDMATCH k % 1 These specifications are design targets and subject to change per device characterization. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 3 2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining. 2 MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 21 Electrical Characteristics 4 Assumed with DC load. VSTBY below 0.95 V the RAM will not retain states, but will be operational. VSTBY can be 0 V when bypass standby mode. 6 Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with VDDREG = 4.5 V (min). 7 2.7 V minimum operating voltage allowed during vehicle crank for system with VDDREG = 3.0 V (min). Normal operating voltage should be either VDDREG = 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected. 8 Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.” 9 I OH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for {00,01,10,11} drive mode with VDDE= 3.0 V. 10 IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDEH = 4.5 V; IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDEH = 3.0 V 11 IOL_S= 2 mA 12 Applies to D_CLKOUT, external bus pins, and Nexus pins. 13 Applies to the FCK, SDI, SDO, and SDS_B pins. 14 VSTBY current specified at 1.0 V at a junction temperature of 85 oC. VSTBY current is 700 µA maximum at a junction temperature of 150 oC. 15 VDDF pin is shorted to VDD on the package substrate. 16 Preliminary. Specification pending typical and/or high-use Runidd pattern simulation as well as final silicon characterization. 1.0 A based on transistor count estimate at Worst Case (wcs) process and temperature condition. 17 Typical values from the simulation. 18 Power requirements for the V DD33 supply depend on the frequency of operation and load of all I/O pins, and the voltages on the I/O segments. See Section 4.7.2, “I/O Pad VDD33 Current Specifications,” for information on both fast (F, FS) and medium (MH) pads. Also refer to Table 15 for values to calculate power dissipation for specific operation. 19 VFLSH pin is shorted to V DD33 on the package substrate. 20 This value is a target that is subject to change. 21 Typical values from the simulation. 22 These value allows a 5 V 20 mA reference to supply ADC + REF. 23 Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad power. Also refer to Table 14 for values to calculate power dissipation for specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment. 24 Absolute value of current, measured at V and V . IL IH 25 Absolute value of current, measured at V and V . IL IH 26 Weak pull up/down inactive. Measured at V DDE = 3.6 V and VDDEH = 5.25 V. Applies to pad types F and MH. 27 Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 oC, in the ambient temperature range of 50 to 125 oC. Applies to pad types AE and AE/up-down. 28 This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics. 29 When the pull-up and pull-down of the same nominal 200 k or 100 k value are both enabled, assuming no interference from external devices, the resulting pad voltage will be 0.5*VDDEH ± 2.5%. 5 4.7.1 I/O Pad Current Specifications The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from Table 14 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 14. The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.” MPC5676R Microcontroller Data Sheet, Rev. 4 22 Freescale Semiconductor Electrical Characteristics Table 14. VDDE/VDDEH I/O Pad Average DC Current1 Spec Pad Type Symbol Frequency (MHz) Load2 (pF) Voltage (V) Drive/Slew Rate Select Current (mA) 1 Medium IDRV_MH 50 50 5.25 11 16.0 2 20 50 5.25 01 6.3 3 3.0 50 5.25 00 1.1 4 2.0 200 5.25 00 2.4 66 10 3.6 00 6.5 6 66 20 3.6 01 9.4 7 66 30 3.6 10 10.8 8 66 50 3.6 11 33.3 9 66 10 1.98 00 2.0 10 66 20 1.98 01 3.0 11 66 30 1.98 10 4.4 12 66 50 1.98 11 15.1 66 50 3.6 11 12.0 50 50 3.6 10 6.2 15 33.33 50 3.6 01 4.0 16 20 50 3.6 00 2.4 17 20 200 3.6 00 8.9 5 13 14 1 2 Fast Fast w/ Slew Control IDRV_FC IDRV_FSR These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only. All loads are lumped. 4.7.2 I/O Pad VDD33 Current Specifications The power consumption of the VDD33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all input and output pin VDD33 currents for all I/O segments. The VDD33 current draw on fast speed pads can be calculated from Table 15 dependent on the voltage, frequency, and load on all F type pins. The VDD33 current draw on medium pads can be calculated from Table 15 dependent on voltage and independent on the frequency and load on all MH type pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in Table 15. The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.” MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 23 Electrical Characteristics Table 15. VDD33 Pad Average DC Current1 Spec Pad Type Symbol Frequency (MHz) Load2 (pF) VDD33 (V) VDDE (V) Drive/Slew Rate Select Current (mA) 1 Medium I33_MH — — 3.6 5.5 — 0.0007 2 Fast I33_FC 66 10 3.6 3.6 00 0.92 3 66 20 3.6 3.6 01 1.14 4 66 30 3.6 3.6 10 1.50 5 66 50 3.6 3.6 11 2.19 6 66 10 3.6 1.98 00 0.70 7 66 20 3.6 1.98 01 0.90 8 66 30 3.6 1.98 10 1.08 9 66 50 3.6 1.98 11 1.52 66 50 3.6 3.6 11 0.74 50 50 3.6 3.6 10 0.52 12 33.33 50 3.6 3.6 01 0.36 13 20 50 3.6 3.6 00 0.19 14 20 200 3.6 3.6 00 0.19 10 Fast w/ Slew Control 11 I33_FSR 1 These are average IDD33 for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input pins only for the medium pads. 2 All loads are lumped. 4.7.3 LVDS Pad Specifications LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI module. Table 16. DSPI LVDS Pad Specification 1, 2 (VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH) Spec Characteristic Symbol Min Typical Max Unit fLVDSCLK — — 40 MHz 215 170 260 — 400 320 480 Data Rate 1 Data Frequency Driver Specs 2 mV Differential Output Voltage SRC=0b00 or 0b11 SRC=0b01 SRC=0b10 VOD 3 Common Mode Voltage (LVDS), VOS VOS 1.075 1.2 1.325 V 4 Rise/Fall Time tR or tF — — 2.5 ns 5 Delay, Z to Normal (High/Low) tDZ — — 100 ns MPC5676R Microcontroller Data Sheet, Rev. 4 24 Freescale Semiconductor Electrical Characteristics Table 16. DSPI LVDS Pad Specification 1, 2 (continued) (VDD33 = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, TA = TL to TH) 6 Differential Skew between Positive and Negative LVDS Pair I tphla – tplhb I or I tplhb – tphla I tSkew — — 0.5 ns RLoad 95 100 105 ohm — — — 32 pF Termination 7 Termination Resistance3 8 Load 1 These are typical values that are estimated from simulation. These specifications are subject to change per device characterization. 3 The termination resistance spec is not meant to specify the receiver termination requirements. They are there to establish the measurement criteria for the specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination resistance can vary from 90 to 132  . 2 4.8 Oscillator and FMPLL Electrical Characteristics Table 17. FMPLL Electrical Specifications1 (VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Spec 1 2 Characteristic PLL Reference Frequency Range2 (Normal Mode) Crystal Reference (PLLCFG2 = 0b0) Crystal Reference (PLLCFG2 = 0b1) External Reference (PLLCFG2 = 0b0) External Reference(PLLCFG2 = 0b1) PLL Frequency 4 Enhanced Mode Symbol Min Max Unit fref_crystal fref_crystal fref_ext fref_ext 8 40 8 40 20 403 20 40 fPLL fvco(min)  64 fmax MHz MHz 3 Loss of Reference Frequency5 fLOR 100 1000 kHz 4 Self Clocked Mode Frequency6 fSCM 4 16 MHz 5 PLL Lock Time7 tLPLL — 0.4 V — V 2 Crystal Mode: Internal Differential Amplifier Noise Rejection Vcrystal_diff_amp_nr — | Vextal – Vxtal | < 0.2 V V 3 EXTAL Input High Voltage Bypass mode, External Reference VIHEXT ((VDD33/2) + 0.4 V) — V 4 EXTAL Input Low Voltage Bypass mode, External Reference VILEXT — (VDD33/2) – 0.4 V V 5 XTAL Current3 IXTAL 1 3 mA 6 Total On-chip stray capacitance on XTAL CS_XTAL — 1.5 pF MPC5676R Microcontroller Data Sheet, Rev. 4 26 Freescale Semiconductor Electrical Characteristics Table 18. Oscillator Electrical Specifications1 (continued) (VDDSYN = 3.0 V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH) Spec Characteristic Symbol Min Max Unit CS_EXTAL — 1.5 pF CL See crystal spec See crystal spec pF 7 Total On-chip stray capacitance on EXTAL 8 Crystal manufacturer’s recommended capacitive load 9 Discrete load capacitance to be connected to EXTAL CL_EXTAL — (2 × CL – CS_EXTA 4 L – CPCB_EXTAL ) pF 10 Discrete load capacitance to be connected to XTAL CL_XTAL — (2 × CL – CS_XTAL – CPCB_XTAL4) pF 1 All values given are initial design targets and subject to change. This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode. In that case, Vextal – Vxtal  400 mV criterion has to be met for oscillator’s comparator to produce output clock. 3 I xtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. 4 C PCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively. 2 4.9 eQADC Electrical Characteristics Table 19. eQADC Conversion Specifications (Operating) Spec Characteristic Symbol Min Max Unit fADCLK 2 16 MHz 1 ADC Clock (ADCLK) Frequency 2 Conversion Cycles CC 2 + 13 128 + 14 ADCLK cycles 3 Stop Mode Recovery Time1 TSR 10 — s 4 Resolution2 — 1.25 — mV INL8 –44 44 LSB5 3 5 INL: 8 MHz ADC Clock 6 INL: 16 MHz ADC Clock3 INL16 –84 84 LSB 7 DNL: 8 MHz ADC Clock3 DNL8 –34 34 LSB 8 DNL: 16 MHz ADC Clock3 DNL16 –34 34 LSB 1004 LSB 9 Offset Error without Calibration OFFNC 04 10 Offset Error with Calibration OFFWC –44 44 LSB 11 Full Scale Gain Error without Calibration GAINNC –1204 04 LSB 12 Full Scale Gain Error with Calibration GAINWC –44,6 44,6 LSB IINJ –1 1 m EINJ — +44 Counts TUE8 — +44,6 Counts Current 7, 8, 9, 10 13 Disruptive Input Injection 14 Incremental Error due to injection current11, 12 15 TUE value at 8 MHz 13, 14 (with calibration) MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 27 Electrical Characteristics Table 19. eQADC Conversion Specifications (Operating) (continued) Spec Characteristic Symbol Min Max Unit — +8 Counts –4 –8 –316 –316 4 8 316 316 –5 –8 –3 –3 5 8 3 3 –7 –8 –4 –4 7 8 4 4 16 TUE value at 16 MHz 13, 14 (with calibration) TUE16 17 Variable gain amplifier accuracy (gain=1)15 INL, 8 MHz ADC INL, 16 MHz ADC DNL, 8 MHz ADC DNL, 16 MHz ADC GAINVGA1 Variable gain amplifier accuracy (gain=2)15 INL, 8 MHz ADC INL, 16 MHz ADC DNL, 8 MHz ADC DNL, 16 MHz ADC GAINVGA2 Variable gain amplifier accuracy (gain=4)15 INL, 8 MHz ADC INL, 16 MHz ADC DNL, 8 MHz ADC DNL, 16 MHz ADC GAINVGA4 18 19 Counts17 Counts Counts 1 Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms. 2 At V RH – VRL = 5.12 V, one count = 1.25 mV without using pregain. 3 INL and DNL are tested from V RL + 50 LSB to VRH – 50 LSB. 4 New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully included. 5 At V RH – VRL = 5.12 V, one LSB = 1.25 mV. 6 The value is valid at 8 MHz, it is ±8 counts at 16 Mhz. 7 Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than VRH and $000 for values less than VRL. Other channels are not affected by non-disruptive conditions. 8 Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage. 9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = VDDA + 0.5 V and VNEGCLAMP = –0.3 V, then use the larger of the calculated values. 10 Condition applies to two adjacent pins at injection limits. 11 Performance expected with production silicon. 12 All channels have same 10 k < Rs < 100 kChannel under test has Rs = 10 k, I INJ=IINJMAX,IINJMIN. 13 The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors. 14 TUE does not apply to differential conversions. 15 Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of 1, 2, or 4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated. 16 Guaranteed 10-bit mono tonicity. 17 At V RH – VRL = 5.12 V, one LSB = 1.25 mV. MPC5676R Microcontroller Data Sheet, Rev. 4 28 Freescale Semiconductor Electrical Characteristics 4.9.1 ADC Internal Resource Measurements Table 20. Power Management Control (PMC) Specification Spec Characteristic Symbol Min Typical Max Unit PMC Normal Mode 1 Bandgap 0.62 V ADC0 channel 145 VADC145 0.59 0.62 0.65 V 2 Bandgap 1.2 V ADC0 channel 146 VADC146 1.10 1.22 1.34 V 3 Vreg1p2 Feedback ADC0 channel 147 VADC147 VDD/2.147 VDD / 2.045 VDD/1.943 V 4 LVD 1.2 V ADC0 channel 180 VADC180 VDD/1.863 VDD / 1.774 VDD/1.685 V 5 Vreg3p3 Feedback ADC0 channel 181 VADC181 Vreg3p3 / 5.733— Vreg3p3 / 5.460 Vreg3p3 / 5.187 V 6 LVD 3.3 V ADC0 channel 182 VADC182 Vreg3p3 / 4.996 Vreg3p3 / 4.758 Vreg3p3 / 4.520 V 7 LVD 5.0 V ADC0 channel 183 — LDO mode — SMPS mode VADC183 VDDREG / 4.996 VDDREG / 7.384 VDDREG / 4.520 VDDREG / 6.680 V VDDREG / 4.758 VDDREG/7.032 Table 21. Standby RAM Regulator Electrical Specifications Spec Characteristic Symbol Min Typ Max Unit Normal Mode 1 Standby Regulator Output ADC1 channel 194 VADC194 — 1.2 — V 2 Standby Source Bias ADC1 channel 195 VADC195 150 — 360 mV Table 22. ADC Band Gap Reference / LVI Electrical Specifications Spec Characteristic Symbol Min Typ Max Unit 1 4.75 LVD (from VDDA) ADC1 channel 196 VADC196 — 4.75 — V 2 ADC Bandgap ADC0 channel 45 ADC1 channel 45 VADC45 — 1.220 — V MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 29 Electrical Characteristics Table 23. Temperature Sensor Electrical Specifications Spec 1 Characteristic 1 Slope –40 C to 100 C ±1.0 C 100 C to 150 C ±1.6 C ADC0 channel 128 ADC1 channel 128 2 Accuracy –40 C to 150 C ADC0 channel 128 ADC1 channel 128 Symbol Min Typ Max Unit VSADC128 1 — 5.8 — mV/ C — -20 — +20 C Slope is the measured voltage change per °C. 4.10 C90 Flash Memory Electrical Characteristics Table 24. Flash Program and Erase Specifications (Pending Si characterization) Spec 1 Characteristic Double Word (64 bits) Program Time4 Time4 Symbol Typ1 Initial Max2 Lifetime Max3 Unit tdwprogram 38 — 500 s tpprogram 45 160 500 s 2 Page (128 bits) Program 3 16 KB Block Pre-program and Erase Time t16kpperase 270 1000 5000 ms 4 48 KB Block Pre-program and Erase Time t48kpperase 625 1500 5000 ms 5 64 KB Block Pre-program and Erase Time t64kpperase 800 1800 5000 ms 6 128 KB Block Pre-program and Erase Time t128kpperase 1500 2600 7500 ms 7 256 KB Block Pre-program and Erase Time t256kpperase 3000 5200 15000 ms 1 Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 oC. These values are characterized, but not tested. 2 Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supply values and operation at 25 oC. These values are verified at production test. 3 Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These values are characterized, but not tested. 4 Program times are actual hardware programming times and do not include software overhead. NOTE The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1) before leaving the factory. MPC5676R Microcontroller Data Sheet, Rev. 4 30 Freescale Semiconductor Electrical Characteristics Table 25. Flash Memory AC Timing Specifications1 Value Symbol Parameter Unit Min Typ Max Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low — — 100 ns TDONE Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared — — 5 ns TPSRT Time between program suspend resume and the next program suspend request.2 100 — — Time between erase suspend resume and the next erase suspend request.3 10 — — TRES TESRT s ms 1 This parameter is guaranteed by characterization before qualification rather than 100% tested. Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during Program operation). The minimum time between suspends to ensure this does notoccur is TPSRT. 3 If Erase suspend rate is less than T ESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase time but reduces cycling figure due to overstress. 2 Table 26. Flash EEPROM Module Life Spec Characteristic Symbol Min Typical1 Unit 1 Number of Program/Erase cycles per block for 16 KB and 64 KB blocks over the operating temperature range (TJ) P/E 100,000 — cycles 2 Number of Program/Erase cycles per block for 128 KB and 256 KB blocks over the operating temperature range (TJ) P/E 1,000 100,000 cycles 3 Minimum Data Retention at 85 °C ambient temperature2 Blocks with 0–1,000 P/E cycles Blocks with 1,001–10,000 P/E cycles Blocks with 10,001–100,000 P/E cycles 20 10 1–5 — Retention years 1 Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional information on the NXP definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 2 Ambient temperature averaged over duration of application, not to exceed product operating temperature range. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 31 Electrical Characteristics Table 27. BIUCR1/BIUCR3 Settings Maximum Frequency (MHz) Spec 1 Core fsys Platform fplatf 180 MHz 90 MHz Default setting after reset: APC = RWSC WWSC 0b010 0b111 DPFEN1 IPFEN1 PFLIM2 BFEN3 0b01 0b0 0b1 0b0 0b1 0b00 0b01 0b1x 0b0 0b1 0b11 0b00 0b00 0b00 0b0 1 For maximum flash performance, set to 0b1. For maximum flash performance, set to 0b10. 3 For maximum flash performance, set to 0b1. 2 4.11 AC Specifications 4.11.1 Clocking Modes There are two main modes of operating frequency settings: • • Double 2:1 (Core:Platform) Mode—the core is running at the system frequency setting while the platform and eTPU are running at half the core frequency (system frequency divided by 2). eTPU Mode—the core and eTPU are running at the system frequency setting while the platform is running at half the core frequency (system frequency divided by 2). Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings. Table 28. MPC5676R Block Operating Frequency1, 2 Spec Blocks 1 Cores 2 Platform 3 eTPU 4 EBI Double Mode Freq (MHz) eTPU Mode Freq (MHz) fsys (tcycsys = 1/fsys) fsys = 180 fsys = 180 fplatf (tcyc = 1/fplatf) fsys / 2 fsys / 2 feTPU fsys / 2 fsys febi fsys / 4 fsys / 4 Symbol 1 The values in the table are specified at VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.5 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. 2 Up to the maximum frequency rating of the device (refer to Table 1). The f sys speed is the nominal maximum frequency. MPC5676R Microcontroller Data Sheet, Rev. 4 32 Freescale Semiconductor Electrical Characteristics 4.11.2 Pad AC Specifications Table 29. Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)1 Spec Pad SRC/DSC Out Delay2,4 L  H/H  L (ns) 1 Medium5 00 152/165 70/74 50 205/220 96/96 200 28/34 12/15 50 52/59 28/31 200 12/12 5.3/5.9 50 32/32 22/22 200 2 3 01 4 5 11 6 Fast6 7 00 10 01 20 9 10 10 11 11 Fast with Slew Rate 13 00 01 14 15 10 16 17 11 18 2 3 4 5 6 Load Drive (pF) 8 12 1 Rise/Fall3,4 (ns) 2.5 1.2 30 50 40/40 16/16 50 50/50 21/21 200 13/13 5/5 50 19/19 8/8 200 8/8 2.4/2.4 50 12/12 5/5 200 5/5 1.1/1/1 50 8/8 2.6 200 19 Pull Up/Down (3.6 V max) — — 7500 50 20 Pull Up/Down (5.25 V max) — 6000 5000/5000 50 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.02 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 4.75 V to 5.25 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. This parameter is guaranteed by characterization before qualification rather than 100% tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock. Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock. Table 30. Derated Pad AC Specifications (VDDEH = 3.3 V)1 Spec Pad SRC/DSC Out Delay2,3 L  H/H  L (ns) Rise/Fall4,3 (ns) Load Drive (pF) 1 Medium5 00 200/210 86/86 50 270/285 120/120 200 37/45 15.5/19 50 69/82 38/43 200 18/17 7.6/8.5 50 46/49 30/34 200 2 3 01 4 5 6 11 MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 33 Electrical Characteristics 1 2 3 4 5 These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDDEH = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. This parameter is supplied for reference and is not guaranteed by design and not tested. Delay and rise/fall are measured to 20% or 80% of the respective signal. This parameter is guaranteed by characterization before qualification rather than 100% tested. Out delay is shown in Figure 7. Add a maximum of one system clock to the output delay for delay with respect to system clock. VDDEn / 2 VDDEHn / 2 Pad Data Input Rising Edge Output Delay Falling Edge Output Delay VOH Pad Output VOL Figure 7. Pad Output Delay 4.12 4.12.1 AC Timing Generic Timing Diagrams The generic timing diagrams in Figure 8 and Figure 9 apply to all I/O pins with pad types F and MH. See Table 39 for the pad type for each pin. MPC5676R Microcontroller Data Sheet, Rev. 4 34 Freescale Semiconductor Electrical Characteristics D_CLKOUT VDDE / 2 A B I/O Outputs VDDEn / 2 VDDEHn / 2 A – Maximum Output Delay Time B – Minimum Output Hold Time Figure 8. Generic Output Delay/Hold Timing D_CLKOUT VDDE / 2 B A I/O Inputs VDDEn / 2 VDDEHn / 2 A – Minimum Input Setup Time B – Minimum Input Hold Time Figure 9. Generic Input Setup/Hold Timing 4.12.2 Reset and Configuration Pin Timing Table 31. Reset and Configuration Pin Timing1 Spec 1 Characteristic Symbol Min Max Unit 1 RESET Pulse Width tRPW 10 — tcyc2 2 RESET Glitch Detect Pulse Width tGPW 2 — tcyc2 3 PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid tRCSU 10 — tcyc2 4 PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid tRCH 0 — tcyc2 Reset timing specified at: VDDEH = 3.0 V to 5.25 V, VDD = 1.08 V to 1.32 V, TA = TL to TH. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 35 Electrical Characteristics 2 See Notes on tcyc on Table 28. 2 RESET 1 RSTOUT 3 PLLCFG BOOTCFG WKPCFG 4 Figure 10. Reset and Configuration Pin Timing 4.12.3 IEEE 1149.1 Interface Timing Table 32. JTAG Pin AC Electrical Characteristics1 Spec Characteristic Symbol Min Max Unit 1 TCK Cycle Time tJCYC 100 — ns 2 TCK Clock Pulse Width (Measured at VDDE / 2) tJDC 40 60 ns 3 TCK Rise and Fall Times (40%–70%) tTCKRISE — 3 ns 4 TMS, TDI Data Setup Time tTMSS, tTDIS 5 — ns 5 TMS, TDI Data Hold Time tTMSH, tTDIH 25 — ns 6 TCK Low to TDO Data Valid tTDOV — 10 ns 7 TCK Low to TDO Data Invalid tTDOI 0 — ns 8 TCK Low to TDO High Impedance tTDOHZ — 20 ns 9 JCOMP Assertion Time tJCMPPW 100 — ns 10 JCOMP Setup Time to TCK Low tJCMPS 40 — ns 11 TCK Falling Edge to Output Valid tBSDV — 50 ns MPC5676R Microcontroller Data Sheet, Rev. 4 36 Freescale Semiconductor Electrical Characteristics Table 32. JTAG Pin AC Electrical Characteristics1 (continued) Spec 1 Characteristic Symbol Min Max Unit 12 TCK Falling Edge to Output Valid out of High Impedance tBSDVZ — 50 ns 13 TCK Falling Edge to Output High Impedance tBSDHZ — 50 ns 14 Boundary Scan Input Valid to TCK Rising Edge tBSDST 50 — ns 15 TCK Rising Edge to Boundary Scan Input Invalid tBSDHT 50 — ns JTAG timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 33 for functional specifications. TCK 2 2 3 1 3 Figure 11. JTAG Test Clock Input Timing MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 37 Electrical Characteristics TCK 4 5 TMS, TDI 6 8 7 TDO Figure 12. JTAG Test Access Port Timing TCK 10 JCOMP 9 Figure 13. JTAG JCOMP Timing MPC5676R Microcontroller Data Sheet, Rev. 4 38 Freescale Semiconductor Electrical Characteristics TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 14. JTAG Boundary Scan Timing 4.12.4 Nexus Timing Table 33. Nexus Debug Port Timing1 Spec Characteristic Symbol Min Max Unit 1 MCKO Cycle Time tMCYC 22 8 tCYC 2 MCKO Duty Cycle tMDC 40 60 % 3 MCKO Low to MDO Data Valid3 tMDOV –0.1 0.2 tMCYC 4 MCKO Low to MSEO Data Valid3 tMSEOV –0.1 0.2 tMCYC 5 MCKO Low to EVTO Data Valid3 tEVTOV –0.1 0.2 tMCYC 6 EVTI Pulse Width tEVTIPW 4.0 — tTCYC 7 EVTO Pulse Width tEVTOPW 1 — tMCYC 8 TCK Cycle Time tTCYC 44 — tCYC 9 TCK Duty Cycle tTDC 40 60 % 10 TDI, TMS Data Setup Time tNTDIS, tNTMSS 8 — ns MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 39 Electrical Characteristics Table 33. Nexus Debug Port Timing1 (continued) Spec Characteristic 11 TDI, TMS Data Hold Time 12 TCK Low to TDO Data Valid 5 13 RDY Valid to MCKO 14 TDO hold time after TCLK low 1 2 3 4 5 Symbol Min Max Unit TNTDIH, tNTMSH 5 — ns tNTDOV 0 10 ns — — — — tNTDOH 1 — ns All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending on the system frequency, not to exceed maximum Nexus AUX port frequency. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. Lower frequency is required to be fully compliant to standard. The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly. 1 2 MCKO 3 4 5 MDO MSEO EVTO Output Data Valid 7 EVTI 6 Figure 15. Nexus Timings MPC5676R Microcontroller Data Sheet, Rev. 4 40 Freescale Semiconductor Electrical Characteristics 8 9 TCK 10 11 TMS, TDI 14 12 TDO Figure 16. Nexus TCK, TDI, TMS, TDO Timing 4.12.5 External Bus Interface (EBI) Timing Table 34. Bus Operation Timing 1 66 MHz (Ext. Bus Freq)2 3 Spec 1 Characteristic D_CLKOUT Period Symbol tC Min Max 15.2 — Unit Notes ns Signals are measured at 50% VDDE. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 41 Electrical Characteristics Table 34. Bus Operation Timing 1 (continued) 66 MHz (Ext. Bus Freq)2 3 Spec Characteristic Symbol Unit Min Max Notes 2 D_CLKOUT Duty Cycle tCDC 45% 55% tC 3 D_CLKOUT Rise Time tCRT — —4 ns 4 D_CLKOUT Fall Time tCFT — —4 ns 5 D_CLKOUT Posedge to Output Signal Invalid or High Z (Hold Time) tCOH 1.0/1.5 — ns Hold time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 1.0 ns EBTS = 1: 1.5 ns tCOV — 8.5/9.0 ns Output valid time selectable via SIU_ECCR[EBTS] bit: EBTS = 0: 8.5 ns EBTS = 1: 9.0 ns tCIS 5.0/4.5 — ns Input setup time selectable via SIU_ECCR[EBTS] bit: EBTS = 0; 5.0ns EBTS = 1; 4.5ns tCIH 1.0 — ns D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3] 6 D_CLKOUT Posedge to Output Signal Valid (Output Delay) D_ADD[9:30] D_BDIP D_CS[0:3] D_DAT[0:15] D_OE D_RD_WR D_TA D_TS D_WE[0:3]/D_BE[0:3] 7 Input Signal Valid to D_CLKOUT Posedge (Setup Time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 8 D_CLKOUT Posedge to Input Signal Invalid (Hold Time) D_ADD[9:30] D_DAT[0:15] D_RD_WR D_TA D_TS 9 D_ALE Pulse Width tAPW 6.5 — ns The timing is for Asynchronous external memory system. 10 D_ALE Negated to Address Invalid tAAI 2.0/1.0 5 — ns The timing is for Asynchronous external memory system. ALE is measured at 50% of VDDE. MPC5676R Microcontroller Data Sheet, Rev. 4 42 Freescale Semiconductor Electrical Characteristics 1 2 3 4 5 EBI timing specified at VDD = 1.08 V to 1.32 V, VDDE = 3.0 V to 3.6 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with DSC = 0b10. Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM). Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency. The maximum external bus frequency is 66 MHz. Refer to Fast pad timing in Table 29 and Table 30. ALE hold time spec is temperature dependant. 1.0ns spec applies for temperature range -40 to 0 C. 2.0ns spec applies to temperatures > 0 C. This spec has no dependency on SIU_ECCR[EBTS] bit. VOH_F VDDE / 2 D_CLKOUT VOL_F 3 2 2 4 1 Figure 17. D_CLKOUT Timing MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 43 Electrical Characteristics VDDE / 2 D_CLKOUT 6 5 5 Output Bus VDDE / 2 6 5 5 Output Signal VDDE / 2 6 Output Signal VDDE / 2 Figure 18. Synchronous Output Timing MPC5676R Microcontroller Data Sheet, Rev. 4 44 Freescale Semiconductor Electrical Characteristics D_CLKOUT VDDE / 2 7 8 Input Bus VDDE / 2 7 8 Input Signal VDDE / 2 Figure 19. Synchronous Input Timing ipg_clk D_CLKOUT D_ALE D_TS D_ADD/D_DAT DATA ADDR 9 10 Figure 20. ALE Signal Timing MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 45 Electrical Characteristics 4.12.6 External Interrupt Timing (IRQ Pin) Table 35. External Interrupt Timing1 Spec Characteristic 1 IRQ Pulse Width Low 2 IRQ Pulse Width High 3 IRQ Edge to Edge Time 3 Symbol Min Max Unit tIPWL 3 — tcyc2 tIPWH 3 — tcyc2 tICYC 6 — tcyc2 1 IRQ timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH. 2 See Notes on tcyc Table 28. 3 Applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 2 1 3 Figure 21. External Interrupt Timing 4.12.7 eTPU Timing Table 36. eTPU Timing1 Spec 1 2 Characteristic eTPU Input Channel Pulse Width eTPU Output Channel Pulse Width Symbol Min Max Unit tICPW 4 — tcyc2 tOCPW 13 — tcyc2 1 eTPU timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 200 pF with SRC = 0b00. 2 See Notes on t cyc Table 28. 3 This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). MPC5676R Microcontroller Data Sheet, Rev. 4 46 Freescale Semiconductor Electrical Characteristics eTPU Input and TCRCLK 1 2 eTPU Output Figure 22. eTPU Timing 4.12.8 eMIOS Timing Table 37. eMIOS Timing1 Spec Characteristic Symbol Min Max Unit 1 eMIOS Input Pulse Width tMIPW 4 — tcyc2 2 eMIOS Output Pulse Width tMOPW 13 — tcyc2 1 eMIOS timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, TA = TL to TH, and CL = 50 pF with SRC = 0b00. 2 See Notes on tcyc on Table 28. 3 This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR). MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 47 Electrical Characteristics eMIOS Input 1 2 eMIOS Output Figure 23. eMIOS Timing 4.12.9 DSPI Timing Table 38. DSPI Timing1,2 Spec Characteristic Symbol Peripheral Bus Freq: 92 MHz Min Max Unit 1 DSPI Cycle Time3, 4 Master (MTFE = 0) Slave (MTFE = 0) Master (MTFE = 1) Slave (MTFE = 1) tSCK 23.8 1800 ns 2 PCS to SCK Delay5 tCSC 12 — ns 3 After SCK Delay6 tASC 12 — ns 4 SCK Duty Cycle tSDC 0.4 * tSCK 0.6 * tSCK ns 5 Slave Access Time (SS active to SOUT valid) tA — 25 ns 6 Slave SOUT Disable Time (SS inactive to SOUT High-Z or invalid) tDIS — 25 ns 7 PCSx to PCSS time tPCSC 4 — ns 8 PCSS to PCSx time tPASC 5 — ns MPC5676R Microcontroller Data Sheet, Rev. 4 48 Freescale Semiconductor Electrical Characteristics Table 38. DSPI Timing1,2 (continued) Spec 9 10 11 12 1 2 3 4 5 6 7 Characteristic Symbol Data Setup Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) tSUI Data Hold Time for Inputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0)7 Master (MTFE = 1, CPHA = 1) tHI Data Valid (after SCK edge) Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Master (LVDS) tSUO Data Hold Time for Outputs Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = 1) Master (LVDS) tHO Peripheral Bus Freq: 92 MHz Unit Min Max 27 10 7 27 — — — — ns ns ns ns –3 7 12 –3 — — — — ns ns ns ns — — — — — 10 30 20 10 5 ns ns ns ns ns –6 2.5 3 –7 –5 — — — — — ns ns ns ns ns DSPI timing specified at VDD = 1.08 V to 1.32 V, VDDEH = 3.0 V to 5.5 V, VDD33 and VDDSYN = 3.0 V to 3.6 V, and TA = TL to TH Speed is the nominal maximum frequency of platform clock (fplatf). Max speed is the maximum speed allowed including frequency modulation (FM). The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two devices communicating over a DSPI link. The actual minimum SCK cycle time is limited by pad performance. The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK]. The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC]. This number is calculated assuming the SMPL_PT bit-field in DSPI_MCR is set to 0b10. The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol. DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high speed operation. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 49 Electrical Characteristics 2 3 PCSx 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 10 9 SIN First Data Last Data Data 12 SOUT First Data 11 Data Last Data Figure 24. DSPI Classic SPI Timing — Master, CPHA = 0 2 3 PCSx 4 1 SCK Output (CPOL=0) 4 10 SCK Output (CPOL=1) 9 SIN Data First Data 12 SOUT First Data Last Data 11 Data Last Data Figure 25. DSPI Classic SPI Timing — Master, CPHA = 1 MPC5676R Microcontroller Data Sheet, Rev. 4 50 Freescale Semiconductor Electrical Characteristics 3 2 SS 1 4 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 First Data SOUT 9 6 Data Last Data Data Last Data 10 First Data SIN 11 12 Figure 26. DSPI Classic SPI Timing — Slave, CPHA = 0 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) 11 5 12 SOUT First Data 9 SIN Data Last Data Data Last Data 6 10 First Data Figure 27. DSPI Classic SPI Timing — Slave, CPHA = 1 MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 51 Electrical Characteristics 3 PCSx 4 1 2 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN 10 First Data Last Data Data 12 SOUT 11 First Data Last Data Data Figure 28. DSPI Modified Transfer Format Timing — Master, CPHA = 0 3 PCSx 2 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Figure 29. DSPI Modified Transfer Format Timing — Master, CPHA = 1 MPC5676R Microcontroller Data Sheet, Rev. 4 52 Freescale Semiconductor Electrical Characteristics 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) First Data SOUT 12 11 5 Data Last Data 10 9 Data First Data SIN 6 Last Data Figure 30. DSPI Modified Transfer Format Timing — Slave, CPHA = 0 3 2 SS 1 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 4 11 5 12 First Data SOUT 9 SIN Data Last Data Data Last Data 6 10 First Data Figure 31. DSPI Modified Transfer Format Timing — Slave, CPHA = 1 MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 53 Electrical Characteristics 7 8 PCSS PCSx Figure 32. DSPI PCS Strobe (PCSS) Timing MPC5676R Microcontroller Data Sheet, Rev. 4 54 Freescale Semiconductor Package Information 5 Package Information 5.1 416-Pin Package The package drawings of the 416-pin TEPBGA package are shown in Figure 33 and Figure 34. Figure 33. 416 TEPBGA Package (1 of 2) MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 55 Package Information Figure 34. 416 TEPBGA Package (2 of 2) MPC5676R Microcontroller Data Sheet, Rev. 4 56 Freescale Semiconductor Package Information 5.2 516-Pin Package The package drawings of the 516-pin TEPBGA package are shown in Figure 35 and Figure 36. Figure 35. 516 TEPBGA Package (1 of 2) MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 57 Package Information Figure 36. 516 TEPBGA Package (2 of 2) MPC5676R Microcontroller Data Sheet, Rev. 4 58 Freescale Semiconductor Product Documentation 6 Product Documentation This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.nxp.com. The following documents are required for a complete description of the device and are necessary to design properly with the parts: • MPC5676R RM Microprocessor Reference Manual (document number MPC5676RRM) MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 59 Freescale Semiconductor Appendix A Signal Properties and Muxing The following table shows the signals properties for each pin on the MPC5676R. For each port pin that has an associated SIU_PCRn register to control its pin properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See Figure 37. U Table 2. Signal Properties and Muxing Summar GPIO/ PCR1 Primary Functions are listed First 113 Signal Name2 P/ F/ G TCRCLKA_IRQ7_GPIO113 P Function3 Function Summary I/O Pad Type 5V M eTPU A TCR clock I I Secondary Functions are alternate functions A1 IRQ7 External interrupt request A2 — — — GPIO Functions are listed Last G GPIO113 GPIO I/O Function not implemented on this device Figure 37. Supported Functions Example Voltage6 State during RESET7 416 516 Function Summary Package Location Pad Type5 Function4 Direction Signal Name2 P/A/G3 Table 39. Signal Properties and Muxing Summary GPIO/PCR1 MPC5676R Microcontroller Data Sheet, Rev. 4 TCRCLKA I MH VDDEH1 —/Up —/Up L1 K4 MH VDDEH1 —/WKPCFG —/WKPCFG L2 L6 State after RESET8 eTPU_A 113 114 TCRCLKA_IRQ7_ GPIO113 ETPUA0_ETPUA12_ GPIO114 P TCRCLKA eTPU A TCR clock A1 IRQ7 External interrupt request I A2 — — — G GPIO113 GPIO I/O P ETPUA0 eTPU A channel I/O A1 ETPUA12 eTPU A channel (output only) O A2 — — — G GPIO114 GPIO I/O 60 Freescale Semiconductor 120 ETPUA5_ETPUA17_ GPIO119 ETPUA6_ETPUA18_ GPIO120 516 119 ETPUA4_ETPUA16_ GPIO118 State during RESET7 416 118 ETPUA3_ETPUA15_ GPIO117 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 117 ETPUA2_ETPUA14_ GPIO116 Function Package Location Pad Type5 116 ETPUA1_ETPUA13_ GPIO115 4 Direction 115 Signal Name 2 P/A/G3 GPIO/PCR1 61 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH1 —/WKPCFG —/WKPCFG L3 J1 MH VDDEH1 —/WKPCFG —/WKPCFG L4 J2 MH VDDEH1 —/WKPCFG —/WKPCFG K1 H4 MH VDDEH1 —/WKPCFG —/WKPCFG K2 J4 MH VDDEH1 —/WKPCFG —/WKPCFG K3 H1 MH VDDEH1 —/WKPCFG —/WKPCFG K4 K5 P ETPUA1 eTPU A channel A1 ETPUA13 eTPU A channel (output only) O A2 — — — G GPIO115 GPIO I/O P ETPUA2 eTPU A channel I/O A1 ETPUA14 eTPU A channel (output only) O A2 — — — G GPIO116 GPIO I/O P ETPUA3 eTPU A channel I/O A1 ETPUA15 eTPU A channel (output only) O A2 — — — G GPIO117 GPIO I/O P ETPUA4 eTPU A channel I/O A1 ETPUA16 eTPU A channel (output only) O A2 — — — G GPIO118 GPIO I/O P ETPUA5 eTPU A channel I/O A1 ETPUA17 eTPU A channel (output only) O A2 — — — G GPIO119 GPIO I/O P ETPUA6 eTPU A channel I/O A1 ETPUA18 eTPU A channel (output only) O A2 — — — G GPIO120 GPIO I/O State after RESET8 126 ETPUA11_ETPUA23_ GPIO125 ETPUA12_PCSB1_ GPIO126 516 125 ETPUA10_ETPUA22_ GPIO124 State during RESET7 416 124 ETPUA9_ETPUA21_ GPIO123 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 123 ETPUA8_ETPUA20_ GPIO122 Function Package Location Pad Type5 122 ETPUA7_ETPUA19_ GPIO121 4 Direction 121 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH1 —/WKPCFG —/WKPCFG J1 H2 MH VDDEH1 —/WKPCFG —/WKPCFG J2 H3 MH VDDEH1 —/WKPCFG —/WKPCFG J3 J3 MH VDDEH1 —/WKPCFG —/WKPCFG J4 K6 MH VDDEH1 —/WKPCFG —/WKPCFG H1 G1 MH VDDEH1 —/WKPCFG —/WKPCFG H2 J5 P ETPUA7 eTPU A channel A1 ETPUA19 eTPU A channel (output only) O A2 — — — G GPIO121 GPIO I/O P ETPUA8 eTPU A channel I/O A1 ETPUA20 eTPU A channel (output only) O A2 — — — G GPIO122 GPIO I/O P ETPUA9 eTPU A channel I/O A1 ETPUA21 eTPU A channel (output only) O A2 — — — G GPIO123 GPIO I/O P ETPUA10 eTPU A channel I/O A1 ETPUA22 eTPU A channel (output only) O A2 — — — G GPIO124 GPIO I/O P ETPUA11 eTPU A channel I/O A1 ETPUA23 eTPU A channel (output only) O A2 — — — G GPIO125 GPIO I/O P ETPUA12 eTPU A channel I/O A1 PCSB1 DSPI B peripheral chip select O A2 — — — G GPIO126 GPIO I/O State after RESET8 62 132 ETPUA17_PCSD2_ GPIO131 ETPUA18_PCSD3_ GPIO132 516 131 ETPUA16_PCSD1_ GPIO130 State during RESET7 416 130 ETPUA15_PCSB5_ GPIO129 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 129 ETPUA14_PCSB4_ GPIO128 Function Package Location Pad Type5 128 ETPUA13_PCSB3_ GPIO127 4 Direction 127 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH1 —/WKPCFG —/WKPCFG H4 G2 MH VDDEH1 —/WKPCFG —/WKPCFG H3 H5 MH VDDEH1 —/WKPCFG —/WKPCFG G1 G3 MH VDDEH1 —/WKPCFG —/WKPCFG G2 H6 MH VDDEH1 —/WKPCFG —/WKPCFG G3 G4 MH VDDEH1 —/WKPCFG —/WKPCFG G4 G5 P ETPUA13 eTPU A channel A1 PCSB3 DSPI B peripheral chip select O A2 — — — G GPIO127 GPIO I/O P ETPUA14 eTPU A channel I/O A1 PCSB4 DSPI B peripheral chip select O A2 — — — G GPIO128 GPIO I/O P ETPUA15 eTPU A channel I/O A1 PCSB5 DSPI B peripheral chip select O A2 — — — G GPIO129 GPIO I/O P ETPUA16 eTPU A channel I/O A1 PCSD1 DSPI D peripheral chip select O A2 — — — G GPIO130 GPIO I/O P ETPUA17 eTPU A channel I/O A1 PCSD2 DSPI D peripheral chip select O A2 — — — G GPIO131 GPIO I/O P ETPUA18 eTPU A channel I/O A1 PCSD3 DSPI D peripheral chip select O A2 — — — G GPIO132 GPIO I/O State after RESET8 63 Freescale Semiconductor 138 ETPUA23_IRQ11_ GPIO137 ETPUA24_IRQ12_ GPIO138 516 137 ETPUA22_IRQ10_ GPIO136 State during RESET7 416 136 ETPUA21_IRQ9_ GPIO135 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 135 ETPUA20_IRQ8_ GPIO134 Function Package Location Pad Type5 134 ETPUA19_PCSD4_ GPIO133 4 Direction 133 Signal Name 2 P/A/G3 GPIO/PCR1 64 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH1 —/WKPCFG —/WKPCFG F1 F1 MH VDDEH1 —/WKPCFG —/WKPCFG F2 F2 MH VDDEH1 —/WKPCFG —/WKPCFG F3 F3 MH VDDEH1 —/WKPCFG —/WKPCFG F4 F4 MH VDDEH1 —/WKPCFG —/WKPCFG E1 E1 MH VDDEH1 —/WKPCFG —/WKPCFG E2 E2 P ETPUA19 eTPU A channel A1 PCSD4 DSPI D peripheral chip select O A2 — — — G GPIO133 GPIO I/O P ETPUA20 eTPU A channel I/O A1 IRQ8 External interrupt request A2 — — — G GPIO134 GPIO I/O P ETPUA21 eTPU A channel I/O A1 IRQ9 External interrupt request A2 — — — G GPIO135 GPIO I/O P ETPUA22 eTPU A channel I/O A1 IRQ10 External interrupt request A2 — — — G GPIO136 GPIO I/O P ETPUA23 eTPU A channel I/O A1 IRQ11 External interrupt request A2 — — — G GPIO137 GPIO I/O P ETPUA24 eTPU A channel I/O A1 IRQ12 External interrupt request A2 — — — G GPIO138 GPIO I/O State after RESET8 I I I I I 144 ETPUA29_PCSC2_ GPIO143 ETPUA30_PCSC3_ GPIO144 516 143 ETPUA28_PCSC1_ GPIO142 State during RESET7 416 142 ETPUA27_IRQ15_ GPIO141 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 141 ETPUA26_IRQ14_ GPIO140 Function Package Location Pad Type5 140 ETPUA25_IRQ13_ GPIO139 4 Direction 139 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH1 —/WKPCFG —/WKPCFG E3 E3 MH VDDEH1 —/WKPCFG —/WKPCFG E4 E4 MH VDDEH1 —/WKPCFG —/WKPCFG D1 D1 MH VDDEH1 —/WKPCFG —/WKPCFG D2 D2 MH VDDEH1 —/WKPCFG —/WKPCFG D3 D3 MH VDDEH1 —/WKPCFG —/WKPCFG C1 C1 P ETPUA25 eTPU A channel A1 IRQ13 External interrupt request A2 — — — G GPIO139 GPIO I/O P ETPUA26 eTPU A channel I/O A1 IRQ14 External interrupt request A2 — — — G GPIO140 GPIO I/O P ETPUA27 eTPU A channel I/O A1 IRQ15 External interrupt request A2 — — — G GPIO141 GPIO I/O P ETPUA28 eTPU A channel I/O A1 PCSC1 DSPI C peripheral chip select O A2 — — — G GPIO142 GPIO I/O P ETPUA29 eTPU A channel I/O A1 PCSC2 DSPI C peripheral chip select O A2 — — — G GPIO143 GPIO I/O P ETPUA30 eTPU A channel I/O A1 PCSC3 DSPI C peripheral chip select O A2 — — — G GPIO144 GPIO I/O State after RESET8 I I I 65 State during RESET7 416 516 Function Summary Voltage6 Function Package Location Pad Type5 ETPUA31_PCSC4_ GPIO145 4 Direction 145 Signal Name 2 P/A/G3 GPIO/PCR1 66 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH1 —/WKPCFG —/WKPCFG C2 C2 MH VDDEH6 —/Up —/Up T23 V25 MH VDDEH6 —/WKPCFG —/WKPCFG T24 V26 MH VDDEH6 —/WKPCFG —/WKPCFG T25 U22 MH VDDEH6 —/WKPCFG —/WKPCFG T26 U23 MH VDDEH6 —/WKPCFG —/WKPCFG R23 T22 P ETPUA31 eTPU A channel A1 PCSC4 DSPI C peripheral chip select O A2 — — — G GPIO145 GPIO I/O State after RESET8 eTPU_B MPC5676R Microcontroller Data Sheet, Rev. 4 146 147 148 149 Freescale Semiconductor 150 TCRCLKB_IRQ6_ GPIO146 ETPUB0_ETPUB16_ GPIO147 ETPUB1_ETPUB17_ GPIO148 ETPUB2_ETPUB18_ GPIO149 ETPUB3_ETPUB19_ GPIO150 P TCRCLKB eTPU B TCR clock I A1 IRQ6 External interrupt request I A2 — — — G GPIO146 GPIO I/O P ETPUB0 eTPU B channel I/O A1 ETPUB16 eTPU B channel (output only) O A2 — — — G GPIO147 GPIO I/O P ETPUB1 eTPU B channel I/O A1 ETPUB17 eTPU B channel (output only) O A2 — — — G GPIO148 GPIO I/O P ETPUB2 eTPU B channel I/O A1 ETPUB18 eTPU B channel (output only) O A2 — — — G GPIO149 GPIO I/O P ETPUB3 eTPU B channel I/O A1 ETPUB19 eTPU B channel (output only) O A2 — — — G GPIO150 GPIO I/O 156 ETPUB8_ETPUB24_ GPIO155 ETPUB9_ETPUB25_ GPIO156 516 155 ETPUB7_ETPUB23_ GPIO154 State during RESET7 416 154 ETPUB6_ETPUB22_ GPIO153 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 153 ETPUB5_ETPUB21_ GPIO152 Function Package Location Pad Type5 152 ETPUB4_ETPUB20_ GPIO151 4 Direction 151 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH6 —/WKPCFG —/WKPCFG R24 U24 MH VDDEH6 —/WKPCFG —/WKPCFG R25 U25 MH VDDEH6 —/WKPCFG —/WKPCFG R26 U26 MH VDDEH6 —/WKPCFG —/WKPCFG P23 T23 MH VDDEH6 —/WKPCFG —/WKPCFG P24 T24 MH VDDEH6 —/WKPCFG —/WKPCFG P25 R22 P ETPUB4 eTPU B channel A1 ETPUB20 eTPU B channel (output only) O A2 — — — G GPIO151 GPIO I/O P ETPUB5 eTPU B channel I/O A1 ETPUB21 eTPU B channel (output only) O A2 — — — G GPIO152 GPIO I/O P ETPUB6 eTPU B channel I/O A1 ETPUB22 eTPU B channel (output only) O A2 — — — G GPIO153 GPIO I/O P ETPUB7 eTPU B channel I/O A1 ETPUB23 eTPU B channel (output only) O A2 — — — G GPIO154 GPIO I/O P ETPUB8 eTPU B channel I/O A1 ETPUB24 eTPU B channel (output only) O A2 — — — G GPIO155 GPIO I/O P ETPUB9 eTPU B channel I/O A1 ETPUB25 eTPU B channel (output only) O A2 — — — G GPIO156 GPIO I/O State after RESET8 67 Freescale Semiconductor 162 ETPUB14_ETPUB30_ GPIO161 ETPUB15_ETPUB31_ GPIO162 516 161 ETPUB13_ETPUB29_ GPIO160 State during RESET7 416 160 ETPUB12_ETPUB28_ GPIO159 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 159 ETPUB11_ETPUB27_ GPIO158 Function Package Location Pad Type5 158 ETPUB10_ETPUB26_ GPIO157 4 Direction 157 Signal Name 2 P/A/G3 GPIO/PCR1 68 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH6 —/WKPCFG —/WKPCFG P26 T25 MH VDDEH6 —/WKPCFG —/WKPCFG N24 T26 MH VDDEH6 —/WKPCFG —/WKPCFG N25 R23 MH VDDEH6 —/WKPCFG —/WKPCFG N26 P22 MH VDDEH6 —/WKPCFG —/WKPCFG M25 R24 MH VDDEH6 —/WKPCFG —/WKPCFG M24 R25 P ETPUB10 eTPU B channel A1 ETPUB26 eTPU B channel (output only) O A2 — — — G GPIO157 GPIO I/O P ETPUB11 eTPU B channel I/O A1 ETPUB27 eTPU B channel (output only) O A2 — — — G GPIO158 GPIO I/O P ETPUB12 eTPU B channel I/O A1 ETPUB28 eTPU B channel (output only) O A2 — — — G GPIO159 GPIO I/O P ETPUB13 eTPU B channel I/O A1 ETPUB29 eTPU B channel (output only) O A2 — — — G GPIO160 GPIO I/O P ETPUB14 eTPU B channel I/O A1 ETPUB30 eTPU B channel (output only) O A2 — — — G GPIO161 GPIO I/O P ETPUB15 eTPU B channel I/O A1 ETPUB31 eTPU B channel (output only) O A2 — — — G GPIO162 GPIO I/O State after RESET8 168 ETPUB20_ GPIO167 ETPUB21_ GPIO168 516 167 ETPUB19_PCSA4_ GPIO166 State during RESET7 416 166 ETPUB18_PCSA3_ GPIO165 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 165 ETPUB17_PCSA2_ GPIO164 Function Package Location Pad Type5 164 ETPUB16_PCSA1_ GPIO163 4 Direction 163 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH6 —/WKPCFG —/WKPCFG U26 V24 MH VDDEH6 —/WKPCFG —/WKPCFG U25 T21 MH VDDEH6 —/WKPCFG —/WKPCFG U24 W26 MH VDDEH6 —/WKPCFG —/WKPCFG U23 W25 MH VDDEH6 —/WKPCFG —/WKPCFG V26 W24 MH VDDEH6 —/WKPCFG —/WKPCFG V25 V22 P ETPUB16 eTPU B channel A1 PCSA1 DSPI A peripheral chip select O A2 — — — G GPIO163 GPIO I/O P ETPUB17 eTPU B channel I/O A1 PCSA2 DSPI A peripheral chip select O A2 — — — G GPIO164 GPIO I/O P ETPUB18 eTPU B channel I/O A1 PCSA3 DSPI A peripheral chip select O A2 — — — G GPIO165 GPIO I/O P ETPUB19 eTPU B channel I/O A1 PCSA4 DSPI A peripheral chip select O A2 — — — G GPIO166 GPIO I/O P ETPUB20 eTPU B channel I/O A1 — — — A2 — — — G GPIO167 GPIO I/O P ETPUB21 eTPU B channel I/O A1 — — — A2 — — — G GPIO168 GPIO I/O State after RESET8 69 Freescale Semiconductor 174 ETPUB26_ GPIO173 ETPUB27_ GPIO174 516 173 ETPUB25_ GPIO172 State during RESET7 416 172 ETPUB24_ GPIO171 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 171 ETPUB23_ GPIO170 Function Package Location Pad Type5 170 ETPUB22_ GPIO169 4 Direction 169 Signal Name 2 P/A/G3 GPIO/PCR1 70 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH6 —/WKPCFG —/WKPCFG V24 V23 MH VDDEH6 —/WKPCFG —/WKPCFG W26 U21 MH VDDEH6 —/WKPCFG —/WKPCFG W25 Y25 MH VDDEH6 —/WKPCFG —/WKPCFG W24 W21 MH VDDEH6 —/WKPCFG —/WKPCFG V23 Y23 MH VDDEH6 —/WKPCFG —/WKPCFG Y25 Y24 P ETPUB22 eTPU B channel A1 — — — A2 — — — G GPIO169 GPIO I/O P ETPUB23 eTPU B channel I/O A1 — — — A2 — — — G GPIO170 GPIO I/O P ETPUB24 eTPU B channel I/O A1 — — — A2 — — — G GPIO171 GPIO I/O P ETPUB25 eTPU B channel I/O A1 — — — A2 — — — G GPIO172 GPIO I/O P ETPUB26 eTPU B channel I/O A1 — — — A2 — — — G GPIO173 GPIO I/O P ETPUB27 eTPU B channel I/O A1 — — — A2 — — — G GPIO174 GPIO I/O State after RESET8 516 ETPUB31_ GPIO178 State during RESET7 416 178 ETPUB30_ GPIO177 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 177 ETPUB29_ GPIO176 Function Package Location Pad Type5 176 ETPUB28_ GPIO175 4 Direction 175 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH6 —/WKPCFG —/WKPCFG Y24 AA24 MH VDDEH6 —/WKPCFG —/WKPCFG Y23 W22 MH VDDEH6 —/WKPCFG —/WKPCFG AA24 AB24 MH VDDEH6 —/WKPCFG —/WKPCFG AB24 Y22 MH VDDEH7 —/Up —/Up B26 F22 MH VDDEH7 —/WKPCFG —/WKPCFG C25 C25 P ETPUB28 eTPU B channel A1 — — — A2 — — — G GPIO175 GPIO I/O P ETPUB29 eTPU B channel I/O A1 — — — A2 — — — G GPIO176 GPIO I/O P ETPUB30 eTPU B channel I/O A1 — — — A2 — — — G GPIO177 GPIO I/O P ETPUB31 eTPU B channel I/O A1 — — — A2 — — — G GPIO178 GPIO I/O State after RESET8 eTPU_C 440 441 TCRCLKC_ GPIO440 ETPUC0_ GPIO441 P TCRCLKC eTPU C TCR clock A1 I — — — A2 — — — G GPIO440 GPIO I/O P ETPUC0 eTPU C channel I/O A1 — — — A2 — — — G GPIO441 GPIO I/O 71 Freescale Semiconductor 447 ETPUC5_ PCSE2_GPIO446 ETPUC6_ PCSE3_GPIO447 516 446 ETPUC4_ PCSE1_GPIO445 State during RESET7 416 445 ETPUC3_ GPIO444 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 444 ETPUC2_ GPIO443 Function Package Location Pad Type5 443 ETPUC1_ GPIO442 4 Direction 442 Signal Name 2 P/A/G3 GPIO/PCR1 72 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH7 —/WKPCFG —/WKPCFG C26 C26 MH VDDEH7 —/WKPCFG —/WKPCFG D25 D25 MH VDDEH7 —/WKPCFG —/WKPCFG D26 D26 MH VDDEH7 —/WKPCFG —/WKPCFG E24 E24 MH VDDEH7 —/WKPCFG —/WKPCFG E25 E25 MH VDDEH7 —/WKPCFG —/WKPCFG E26 E26 P ETPUC1 eTPU C channel A1 — — — A2 — — — G GPIO442 GPIO I/O P ETPUC2 eTPU C channel I/O A1 — — — A2 — — — G GPIO443 GPIO I/O P ETPUC3 eTPU C channel I/O A1 — — — A2 — — — G GPIO444 GPIO I/O P ETPUC4 eTPU C channel I/O State after RESET8 DSPI E peripheral chip select A1 A2 — — — G GPIO445 GPIO I/O P ETPUC5 eTPU C channel I/O DSPI E peripheral chip select A1 A2 — — — G GPIO446 GPIO I/O P ETPUC6 eTPU C channel I/O DSPI E peripheral chip select A1 A2 — — — G GPIO447 GPIO I/O 453 ETPUC11_IRQ2_ GPIO452 ETPUC12_IRQ3_ GPIO453 516 452 ETPUC10__IRQ1_ GPIO451 eTPU C channel State during RESET7 416 451 ETPUC9_IRQ0_ GPIO450 ETPUC7 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 450 ETPUC8_ PCSE5_GPIO449 P Function Package Location Pad Type5 449 ETPUC7_ PCSE4_GPIO448 4 Direction 448 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH7 —/WKPCFG —/WKPCFG F23 F23 MH VDDEH7 —/WKPCFG —/WKPCFG F24 F24 MH VDDEH7 —/WKPCFG —/WKPCFG F25 F25 MH VDDEH7 —/WKPCFG —/WKPCFG F26 F26 MH VDDEH7 —/WKPCFG —/WKPCFG G23 G22 MH VDDEH7 —/WKPCFG —/WKPCFG G24 G23 State after RESET8 DSPI E peripheral chip select A1 A2 — — — G GPIO448 GPIO I/O P ETPUC8 eTPU C channel I/O DSPI E peripheral chip select A1 A2 — — — G GPIO449 GPIO I/O P ETPUC9 eTPU C channel I/O A1 IRQ0 External interrupt request A2 — — — G GPIO450 GPIO I/O P ETPUC10 eTPU C channel I/O A1 IRQ1 External interrupt request A2 — — — G GPIO451 GPIO I/O P ETPUC11 eTPU C channel I/O A1 IRQ2 External interrupt request A2 — — — G GPIO452 GPIO I/O P ETPUC12 eTPU C channel I/O A1 IRQ3 External interrupt request A2 — — — G GPIO453 GPIO I/O I I I I 73 Freescale Semiconductor 459 ETPUC17_FR_A_RX_ GPIO458 ETPUC18_FR_A_TX_EN_ GPIO459 516 458 ETPUC16_FR_A_TX_ GPIO457 State during RESET7 416 457 ETPUC15__ GPIO456 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 456 ETPUC14_4_IRQ5_ GPIO455 Function Package Location Pad Type5 455 ETPUC13_3_IRQ4_ GPIO454 4 Direction 454 Signal Name 2 P/A/G3 GPIO/PCR1 74 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH7 —/WKPCFG —/WKPCFG G25 G24 MH VDDEH7 —/WKPCFG —/WKPCFG G26 G25 MH VDDEH7 —/WKPCFG —/WKPCFG H23 G26 MH VDDEH7 —/WKPCFG —/WKPCFG H24 H22 MH VDDEH7 —/WKPCFG —/WKPCFG H25 H23 MH VDDEH7 —/WKPCFG —/WKPCFG H26 H24 P ETPUC13 eTPU C channel A1 IRQ4 External interrupt request A2 — — — G GPIO454 GPIO I/O P ETPUC14 eTPU C channel I/O A1 IRQ5 External interrupt request A2 — — — G GPIO455 GPIO I/O P ETPUC15 eTPU C channel I/O A1 — — — A2 — — — G GPIO456 GPIO I/O P ETPUC16 eTPU C channel I/O A1 FR_A_TX FlexRay A transfer O A2 — — — G GPIO457 GPIO I/O P ETPUC17 eTPU C channel I/O A1 FR_A_RX FlexRay A receive A2 — — — G GPIO458 GPIO I/O P ETPUC18 eTPU C channel I/O A1 FR_A_TX_EN FlexRay A transfer enable O A2 — — — G GPIO459 GPIO I/O State after RESET8 I I I 465 ETPUC23_PCSD5_ GPIO464 ETPUC24_PCSD4_ GPIO465 516 464 ETPUC22_RXDB_ GPIO463 State during RESET7 416 463 ETPUC21_TXDB_ GPIO462 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 462 ETPUC20_RXDA _ GPIO461 Function Package Location Pad Type5 461 ETPUC19_TXDA_ GPIO460 4 Direction 460 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH7 —/WKPCFG —/WKPCFG J23 H21 MH VDDEH7 —/WKPCFG —/WKPCFG J24 H25 MH VDDEH7 —/WKPCFG —/WKPCFG J25 H26 MH VDDEH7 —/WKPCFG —/WKPCFG J26 J22 MH VDDEH7 —/WKPCFG —/WKPCFG K23 J23 MH VDDEH7 —/WKPCFG —/WKPCFG K24 J24 P ETPUC19 eTPU C channel A1 TXDA eSCI A transmit O A2 — — — G GPIO460 GPIO I/O P ETPUC20 eTPU C channel I/O A1 RXDA eSCI A receive A2 — — — G GPIO461 GPIO I/O P ETPUC21 eTPU C channel I/O A1 TXDB eSCI B transmit O A2 — — — G GPIO462 GPIO I/O P ETPUC22 eTPU C channel I/O A1 RXDB eSCI B receive A2 — — — G GPIO463 GPIO I/O P ETPUC23 eTPU C channel I/O A1 PCSD5 DSPI D peripheral chip select O A2 MAA0 ADC A Mux Address 0 O A3 MAB0 ADC B Mux Address 0 O G GPIO464 GPIO I/O P ETPUC24 eTPU C channel I/O A1 PCSD4 DSPI D peripheral chip select O A2 MAA1 ADC A Mux Address 1 O A4 MAB1 ADC B Mux Address 1 O G GPIO465 GPIO I/O State after RESET8 I I 75 Freescale Semiconductor 471 ETPUC29_SCKD_ GPIO470 ETPUC30_SOUTD_ GPIO471 516 470 ETPUC28_PCSD0_ GPIO469 State during RESET7 416 469 ETPUC27_PCSD1_ GPIO468 Function Summary Voltage6 468 ETPUC26_PCSD2_ GPIO467 Function Package Location Pad Type5 MPC5676R Microcontroller Data Sheet, Rev. 4 467 ETPUC25_PCSD3_ GPIO466 4 Direction 466 Signal Name 2 P/A/G3 GPIO/PCR1 76 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH7 —/WKPCFG —/WKPCFG K25 K21 MH VDDEH7 —/WKPCFG —/WKPCFG K26 J25 MH VDDEH7 —/WKPCFG —/WKPCFG L23 J26 MH VDDEH7 —/WKPCFG —/WKPCFG L24 K22 MH VDDEH7 —/WKPCFG —/WKPCFG L25 K23 MH VDDEH7 —/WKPCFG —/WKPCFG L26 K24 P ETPUC25 eTPU C channel A1 PCSD3 DSPI D peripheral chip select O A2 MAA2 ADC A Mux Address 2 O A3 MAB2 ADC B Mux Address 2 O G GPIO466 GPIO I/O P ETPUC26 eTPU C channel I/O A1 PCSD2 DSPI D peripheral chip select O A2 — — — G GPIO467 GPIO I/O P ETPUC27 eTPU C channel I/O A1 PCSD1 DSPI D peripheral chip select O A2 — — — G GPIO468 GPIO I/O P ETPUC28 eTPU C channel I/O A1 PCSD0 DSPI D peripheral chip select O A2 — — — G GPIO469 GPIO I/O P ETPUC29 eTPU C channel I/O A1 SCKD DSPI D clock I/O A2 — — — G GPIO470 GPIO I/O P ETPUC30 eTPU C channel I/O A1 SOUTD DSPI D data output O A2 — — — G GPIO471 GPIO I/O State after RESET8 State during RESET7 416 516 Function Summary Voltage6 Function Package Location Pad Type5 ETPUC31_SIND_ GPIO472 4 Direction 472 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH7 —/WKPCFG —/WKPCFG M23 K25 MH VDDEH4 —/WKPCFG —/WKPCFG AE10 AC13 MH VDDEH4 —/WKPCFG —/WKPCFG AF10 AB13 MH VDDEH4 —/WKPCFG —/WKPCFG AD11 AD13 MH VDDEH4 —/WKPCFG —/WKPCFG AE11 AE13 MH VDDEH4 —/WKPCFG —/WKPCFG AF11 AF13 P ETPUC31 eTPU C channel A1 SIND DSPI D data input A2 — — — G GPIO472 GPIO I/O State after RESET8 I eMIOS MPC5676R Microcontroller Data Sheet, Rev. 4 179 180 181 182 183 EMIOS0_ETPUA0_ GPIO179 EMIOS1_ETPUA1_ GPIO180 EMIOS2_ETPUA2_ GPIO181 EMIOS3_ETPUA3_ GPIO182 EMIOS4_ETPUA4_ GPIO183 P EMIOS0 eMIOS channel I/O A1 ETPUA0 eTPU A channel O A2 — — — G GPIO179 GPIO I/O P EMIOS1 eMIOS channel I/O A1 ETPUA1 eTPU A channel O A2 — — — G GPIO180 GPIO I/O P EMIOS2 eMIOS channel I/O A1 ETPUA2 eTPU A channel O A2 — — — G GPIO181 GPIO I/O P EMIOS3 eMIOS channel I/O A1 ETPUA3 eTPU A channel O A2 — — — G GPIO182 GPIO I/O P EMIOS4 eMIOS channel I/O A1 ETPUA4 eTPU A channel O A2 — — — G GPIO183 GPIO I/O 77 Freescale Semiconductor 189 EMIOS9_ETPUA9_ GPIO188 EMIOS10_SCKD_ GPIO189 516 188 EMIOS8_ETPUA8_ GPIO187 State during RESET7 416 187 EMIOS7_ETPUA7_ GPIO186 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 186 EMIOS6_ETPUA6_ GPIO185 Function Package Location Pad Type5 185 EMIOS5_ETPUA5_ GPIO184 4 Direction 184 Signal Name 2 P/A/G3 GPIO/PCR1 78 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD12 AF14 MH VDDEH4 —/WKPCFG —/WKPCFG AE12 AE14 MH VDDEH4 —/WKPCFG —/WKPCFG AF12 AD14 MH VDDEH4 —/WKPCFG —/WKPCFG AC13 AC14 MH VDDEH4 —/WKPCFG —/WKPCFG AD13 AF15 MH VDDEH4 —/WKPCFG —/WKPCFG AE13 AE15 P EMIOS5 eMIOS channel A1 ETPUA5 eTPU A channel O A2 — — — G GPIO184 GPIO I/O P EMIOS6 eMIOS channel I/O A1 ETPUA6 eTPU A channel O A2 — — — G GPIO185 GPIO I/O P EMIOS7 eMIOS channel I/O A1 ETPUA7 eTPU A channel O A2 — — — G GPIO186 GPIO I/O P EMIOS8 eMIOS channel I/O A1 ETPUA8 eTPU A channel O A2 — — — G GPIO187 GPIO I/O P EMIOS9 eMIOS channel I/O A1 ETPUA9 eTPU A channel O A2 — — — G GPIO188 GPIO I/O P EMIOS10 eMIOS channel I/O A1 SCKD DSPI D clock O A2 — — — G GPIO189 GPIO I/O State after RESET8 195 EMIOS15_IRQ1_ GPIO194 EMIOS16_ETPUB0_ GPIO195 516 194 EMIOS14_IRQ0_ GPIO193 State during RESET7 416 193 EMIOS13_SOUTD_ GPIO192 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 192 EMIOS12_SOUTC_ GPIO191 Function Package Location Pad Type5 191 EMIOS11_SIND_ GPIO190 4 Direction 190 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH4 —/WKPCFG —/WKPCFG AF13 AB14 MH VDDEH4 —/WKPCFG —/WKPCFG AF14 AD15 MH VDDEH4 —/WKPCFG —/WKPCFG AE14 AC15 MH VDDEH4 —/WKPCFG —/WKPCFG AC14 AF17 MH VDDEH4 —/WKPCFG —/WKPCFG AD14 AE16 MH VDDEH4 —/WKPCFG —/WKPCFG AF15 AD16 P EMIOS11 eMIOS channel A1 SIND DSPI D data input A2 — — — G GPIO190 GPIO I/O P EMIOS12 eMIOS channel O A1 SOUTC DSPI C data output O A2 — — — G GPIO191 GPIO I/O P EMIOS13 eMIOS channel O A1 SOUTD DSPI D data output O A2 — — — G GPIO192 GPIO I/O P EMIOS14 eMIOS channel O A1 IRQ0 External interrupt request I A2 CNTXD FlexCAN D transmit O G GPIO193 GPIO I/O P EMIOS15 eMIOS channel O A1 IRQ1 External interrupt request I A2 CNRXD FlexCAN D receive I G GPIO194 GPIO I/O P EMIOS16 eMIOS channel I/O A1 ETPUB0 eTPU B channel O A2 FR_DBG[3] FlexRay debug O G GPIO195 GPIO I/O State after RESET8 I 79 Freescale Semiconductor 201 EMIOS21_ETPUB5_ GPIO200 EMIOS22_ETPUB6_ GPIO201 516 200 EMIOS20_ETPUB4_ GPIO199 State during RESET7 416 199 EMIOS19_ETPUB3_ GPIO198 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 198 EMIOS18_ETPUB2_ GPIO197 Function Package Location Pad Type5 197 EMIOS17_ETPUB1_ GPIO196 4 Direction 196 Signal Name 2 P/A/G3 GPIO/PCR1 80 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE15 AB15 MH VDDEH4 —/WKPCFG —/WKPCFG AC15 AD17 MH VDDEH4 —/WKPCFG —/WKPCFG AD15 AB16 MH VDDEH4 —/WKPCFG —/WKPCFG AF16 AF16 MH VDDEH4 —/WKPCFG —/WKPCFG AE16 AE17 MH VDDEH4 —/WKPCFG —/WKPCFG AC16 AC16 P EMIOS17 eMIOS channel A1 ETPUB1 eTPU B channel O A2 FR_DBG[2] FlexRay debug O G GPIO196 GPIO I/O P EMIOS18 eMIOS channel I/O A1 ETPUB2 eTPU B channel O A2 FR_DBG[1] FlexRay debug O G GPIO197 GPIO I/O P EMIOS19 eMIOS channel I/O A1 ETPUB3 eTPU B channel O A2 FR_DBG[0] FlexRay debug O G GPIO198 GPIO I/O P EMIOS20 eMIOS channel I/O A1 ETPUB4 eTPU B channel O A2 — — — G GPIO199 GPIO I/O P EMIOS21 eMIOS channel I/O A1 ETPUB5 eTPU B channel O A2 — — — G GPIO200 GPIO I/O P EMIOS22 eMIOS channel I/O A1 ETPUB6 eTPU B channel O A2 — — — G GPIO201 GPIO I/O State after RESET8 434 EMIOS27_PCSB3_ GPIO433 EMIOS28_PCSC0_ GPIO434 516 433 EMIOS26_PCSB2_ GPIO432 State during RESET7 416 432 EMIOS25_PCSB1_ GPIO204 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 204 EMIOS24_PCSB0_ GPIO203 Function Package Location Pad Type5 203 EMIOS23_ETPUB7_ GPIO202 4 Direction 202 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH4 —/WKPCFG —/WKPCFG AD16 AA16 MH VDDEH4 —/WKPCFG —/WKPCFG AF17 AC17 MH VDDEH4 —/WKPCFG —/WKPCFG AE17 AF18 MH VDDEH4 —/WKPCFG —/WKPCFG AD17 AE18 MH VDDEH4 —/WKPCFG —/WKPCFG AC17 AD18 MH VDDEH4 —/WKPCFG —/WKPCFG AF18 AC18 P EMIOS23 eMIOS channel A1 ETPUB7 eTPU B channel O A2 — — — G GPIO202 GPIO I/O P EMIOS24 eMIOS channel I/O A1 PCSB0 DSPI B peripheral chip select I/O A2 — — — G GPIO203 GPIO I/O P EMIOS25 eMIOS channel I/O A1 PCSB1 DSPI B peripheral chip select O A2 — — — G GPIO204 GPIO I/O P EMIOS26 eMIOS channel I/O A1 PCSB2 DSPI B peripheral chip select O A2 — — — G GPIO432 GPIO I/O P EMIOS27 eMIOS channel I/O A1 PCSB3 DSPI B peripheral chip select O A2 — — — G GPIO433 GPIO I/O P EMIOS28 eMIOS channel I/O A1 PCSC0 DSPI C peripheral chip select I/O A2 — — — G GPIO434 GPIO I/O State after RESET8 81 State during RESET7 416 516 EMIOS31_PCSC5_ GPIO437 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 437 EMIOS30_PCSC2_ GPIO436 Function Package Location Pad Type5 436 EMIOS29_PCSC1_ GPIO435 4 Direction 435 Signal Name 2 P/A/G3 GPIO/PCR1 82 Table 39. Signal Properties and Muxing Summary (continued) I/O MH VDDEH4 —/WKPCFG —/WKPCFG AE18 AB17 MH VDDEH4 —/WKPCFG —/WKPCFG AD18 AF19 MH VDDEH4 —/WKPCFG —/WKPCFG AC18 AA17 P EMIOS29 eMIOS channel A1 PCSC1 DSPI C peripheral chip select O A2 — — — G GPIO435 GPIO I/O P EMIOS30 eMIOS channel I/O A1 PCSC2 DSPI C peripheral chip select O A2 — — — G GPIO436 GPIO I/O P EMIOS31 eMIOS channel I/O A1 PCSC5 DSPI C peripheral chip select O A2 — — — G GPIO437 GPIO I/O State after RESET8 eQADC Freescale Semiconductor — ANA0 P ANA09 eQADC A shared analog input I AE/updown VDDA_A1 ANA0 ANA0 A4 A4 — ANA1 P ANA19 eQADC A shared analog input I AE/updown VDDA_A1 ANA1 ANA1 B5 B5 — ANA2 P ANA29 eQADC A shared analog input I AE/updown VDDA_A1 ANA2 ANA2 C5 C5 — ANA3 P ANA39 eQADC A shared analog input I AE/updown VDDA_A1 ANA3 ANA3 D6 D6 — ANA4 P ANA49 eQADC A shared analog input I AE/updown VDDA_A1 ANA4 ANA4 A5 A5 — ANA5 P ANA59 eQADC A shared analog input I AE/updown VDDA_A1 ANA5 ANA5 B6 B6 — ANA6 P ANA69 eQADC A shared analog input I AE/updown VDDA_A1 ANA6 ANA6 C6 C6 — ANA7 P ANA79 eQADC A shared analog input I AE/updown VDDA_A1 ANA7 ANA7 D7 C7 State during RESET7 416 516 — ANA8 P ANA8 eQADC A analog input I AE VDDA_A1 ANA8 ANA8 A6 D7 — ANA9 P ANA9 eQADC A analog input I AE VDDA_A1 ANA9 ANA9 C7 A6 — ANA10 P ANA10 eQADC A analog input I AE VDDA_A1 ANA10 ANA10 B7 B7 — ANA11 P ANA11 eQADC A analog input I AE VDDA_A1 ANA11 ANA11 A7 A7 — ANA12 P ANA12 eQADC A analog input I AE VDDA_A1 ANA12 ANA12 D8 D8 — ANA13 P ANA13 eQADC A analog input I AE VDDA_A1 ANA13 ANA13 C8 C8 — ANA14 P ANA14 eQADC A analog input I AE VDDA_A1 ANA14 ANA14 B8 B8 — ANA15 P ANA15 eQADC A analog input I AE VDDA_A1 ANA15 ANA15 A8 A8 — ANA16 P ANA16 eQADC A analog input I AE VDDA_A1 ANA16 ANA16 D9 D9 — ANA17 P ANA17 eQADC A analog input I AE VDDA_A1 ANA17 ANA17 C9 C9 — ANA18 P ANA18 eQADC A analog input I AE VDDA_A1 ANA18 ANA18 D10 D10 — ANA19 P ANA19 eQADC A analog input I AE VDDA_A1 ANA19 ANA19 C10 C10 — ANA20 P ANA20 eQADC A analog input I AE VDDA_A1 ANA20 ANA20 D11 D11 — ANA21 P ANA21 eQADC A analog input I AE VDDA_A1 ANA21 ANA21 C11 C11 — ANA22 P ANA22 eQADC A analog input I AE VDDA_A1 ANA22 ANA22 D12 C12 — ANA23 P ANA23 eQADC A analog input I AE VDDA_A1 ANA23 ANA23 C12 D12 — AN24 P AN24 eQADC analog input I AE VDDA_A0 AN24 AN24 B12 B12 — AN25 P AN25 eQADC analog input I AE VDDA_A0 AN25 AN25 D13 C13 — AN26 P AN26 eQADC analog input I AE VDDA_A0 AN26 AN26 C13 D13 — AN27 P AN27 eQADC analog input I AE VDDA_A0 AN27 AN27 B13 B13 — AN28 P AN28 eQADC analog input I AE VDDA_A0 AN28 AN28 A13 A13 — AN29 P AN29 eQADC analog input I AE VDDA_A0 AN29 AN29 B14 A14 — AN30 P AN30 eQADC analog input I AE VDDA_B1 AN30 AN30 C14 B14 — AN31 P AN31 eQADC analog input I AE VDDA_B1 AN31 AN31 D14 C14 — AN32 P AN32 eQADC analog input I AE VDDA_B1 AN32 AN32 A14 B15 — AN33 P AN33 eQADC analog input I AE VDDA_B0 AN33 AN33 B15 D14 — AN34 P AN34 eQADC analog input I AE VDDA_B0 AN34 AN34 C15 C15 Signal Name 2 P/A/G3 Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 83 Pad Type5 Package Location Direction GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) 4 Function Function Summary State after RESET8 State during RESET7 416 516 — AN35 P AN35 eQADC analog input I AE VDDA_B0 AN35 AN35 D15 D15 — AN36 P AN36 eQADC analog input I AE VDDA_B1 AN36 AN36 A15 A15 — AN37 P AN37 eQADC analog input I AE VDDA_B0 AN37 AN37 C16 C17 — AN38 P AN38 eQADC analog input I AE VDDA_B0 AN38 AN38 C17 D16 — AN39 P AN39 eQADC analog input I AE VDDA_B0 AN39 AN39 D16 C16 — ANB0 P ANB0 eQADC B shared analog input I AE/updown VDDA_B0 ANB0 ANB0 C18 C18 — ANB1 P ANB1 eQADC B shared analog input I AE/updown VDDA_B0 ANB1 ANB1 D17 D17 — ANB2 P ANB2 eQADC B shared analog input I AE/updown VDDA_B0 ANB2 ANB2 D18 D18 — ANB3 P ANB3 eQADC B shared analog input I AE/updown VDDA_B0 ANB3 ANB3 D19 D19 — ANB4 P ANB4 eQADC B shared analog input I AE/updown VDDA_B0 ANB4 ANB4 C19 B19 — ANB5 P ANB5 eQADC B shared analog input I AE/updown VDDA_B0 ANB5 ANB5 C20 A20 — ANB6 P ANB6 eQADC B shared analog input I AE/updown VDDA_B0 ANB6 ANB6 B19 C20 — ANB7 P ANB7 eQADC B shared analog input I AE/updown VDDA_B0 ANB7 ANB7 A20 C19 — ANB8 P ANB8 eQADC B analog input I AE VDDA_B0 ANB8 ANB8 B20 B20 — ANB9 P ANB9 eQADC B analog input I AE VDDA_B0 ANB9 ANB9 D20 A21 — ANB10 P ANB10 eQADC B analog input I AE VDDA_B0 ANB10 ANB10 B21 B21 — ANB11 P ANB11 eQADC B analog input I AE VDDA_B0 ANB11 ANB11 A21 C21 — ANB12 P ANB12 eQADC B analog input I AE VDDA_B0 ANB12 ANB12 C21 A22 — ANB13 P ANB13 eQADC B analog input I AE VDDA_B0 ANB13 ANB13 D21 B22 — ANB14 P ANB14 eQADC B analog input I AE VDDA_B0 ANB14 ANB14 A22 D20 — ANB15 P ANB15 eQADC B analog input I AE VDDA_B0 ANB15 ANB15 B22 C22 — ANB16 P ANB16 eQADC B analog input I AE VDDA_B0 ANB16 ANB16 C22 D21 Signal Name 2 P/A/G3 Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor Pad Type5 Package Location Direction GPIO/PCR1 84 Table 39. Signal Properties and Muxing Summary (continued) 4 Function Function Summary State after RESET8 State during RESET7 416 516 — ANB17 P ANB17 eQADC B analog input I AE VDDA_B0 ANB17 ANB17 A23 D22 — ANB18 P ANB18 eQADC B analog input I AE VDDA_B0 ANB18 ANB18 B23 A23 — ANB19 P ANB19 eQADC B analog input I AE VDDA_B0 ANB19 ANB19 C23 B23 — ANB20 P ANB20 eQADC B analog input I AE VDDA_B0 ANB20 ANB20 D22 C23 — ANB21 P ANB21 eQADC B analog input I AE VDDA_B0 ANB21 ANB21 A24 A24 — ANB22 P ANB22 eQADC B analog input I AE VDDA_B0 ANB22 ANB22 B24 B24 — ANB23 P ANB23 eQADC B analog input I AE VDDA_B0 ANB23 ANB23 A25 E20 — VRH_A P VRH_A ADC A Voltage reference high I VDDINT VRH_A VRH_A VRH_A A12 A12 — VRL_A P VRL_A ADC A Voltage reference low I VSSINT VRL_A VRL_A VRL_A A11 A11 — VRH_B P VRH_B ADC B Voltage reference high I VDDINT VRH_B VRH_B VRH_B A19 A19 — VRL_B P VRL_B ADC B Voltage reference low I VSSINT VRL_B VRL_B VRL_B A18 A18 — REFBYPCB P REFBYPCB ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB REFBYPCB B18 B18 — REFBYPCA P REFBYPCA ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA REFBYPCA B11 B11 — VDDA_A0 P VDDA_A Internal logic supply input I VDDE VDDA_A0 VDDA_A0 VDDA_A0 A9 A9 — VDDA_A1 P VDDA_A Internal logic supply input I VDDE VDDA_A1 VDDA_A1 VDDA_A1 B9 B9 — REFBYPCA1 P REFBYPCA1 ADC A Reference bypass capacitor I AE VDDA_A1 REFBYPCA1 REFBYPCA1 A10 A10 — VSSA_A1 P VSSA_A Ground I VSSE VSSA_A1 VSSA_A1 VSSA_A1 B10 B10 — VDDA_B0 P VDDA_B Internal logic supply input I VDDE VDDA_B0 VDDA_B0 VDDA_B0 A16 A16 — VDDA_B1 P VDDA_B Internal logic supply input I VDDE VDDA_B1 VDDA_B1 VDDA_B1 B16 B16 — VSSA_B0 P VSSA_B Ground I VSSE VSSA_B0 VSSA_B0 VSSA_B0 B17 B17 — REFBYPCB1 P REFBYPCB1 ADC B Reference bypass capacitor I AE VDDA_B0 REFBYPCB1 REFBYPCB1 A17 A17 FS VDDE2 —/Up (–/– for Rev.1 of the device) —/Up (–/– for Rev.1 of the device) AD4 AD4 Signal Name 2 P/A/G3 Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 Pad Type5 Package Location Direction GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) 4 Function Function Summary State after RESET8 FlexRay 248 FR_A_TX_ GPIO248 P FR_A_TX FlexRay A transfer O A1 — — — A2 — — — G GPIO248 GPIO I/O 85 FR_B_TX_EN_ GPIO253 Freescale Semiconductor 516 253 FR_B_RX_ GPIO252 416 252 FR_B_TX_ GPIO251 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 251 FR_A_TX_EN_ GPIO250 Function Package Location Pad Type5 250 FR_A_RX_ GPIO249 4 Direction 249 Signal Name 2 P/A/G3 GPIO/PCR1 86 Table 39. Signal Properties and Muxing Summary (continued) I FS VDDE2 —/Up (–/– for Rev.1 of the device) —/Up (–/– for Rev.1 of the device) AE3 AE3 FS VDDE2 —/Up (–/– for Rev.1 of the device) —/Up (–/– for Rev.1 of the device) AF3 AF3 FS VDDE2 —/Up (–/– for Rev.1 of the device) —/Up (–/– for Rev.1 of the device) AD5 AD5 FS VDDE2 —/Up (–/– for Rev.1 of the device) —/Up (–/– for Rev.1 of the device) AE4 AE4 FS VDDE2 —/Up (–/– for Rev.1 of the device) —/Up (–/– for Rev.1 of the device) AF4 AF4 MH VDDEH4 —/Up —/Up AF19 AE19 P FR_A_RX FlexRay A receive A1 — — — A2 — — — G GPIO249 GPIO I/O P FR_A_TX_EN FlexRay A transfer enable O A1 — — — A2 — — — G GPIO250 GPIO I/O P FR_B_TX FlexRay B transfer O A1 — — — A2 — — — G GPIO251 GPIO I/O P FR_B_RX FlexRay B receive A1 — — — A2 — — — G GPIO252 GPIO I/O P FR_B_TX_EN FlexRay B transfer enable O A1 — — — A2 — — — G GPIO253 GPIO I/O I State during RESET7 State after RESET8 FlexCAN 83 CNTXA_TXDA_ GPIO83 P CNTXA FlexCAN A transmit O A1 TXDA eSCI A transmit O A2 — — — G GPIO83 GPIO I/O 246 CNRXC_PCSD4_ GPIO88 CNTXD_ GPIO246 516 88 CNTXC_PCSD3_ GPIO87 State during RESET7 416 87 CNRXB_PCSC4_ GPIO86 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 86 CNTXB_PCSC3_ GPIO85 Function Package Location Pad Type5 85 CNRXA_RXDA_ GPIO84 4 Direction 84 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I MH VDDEH4 —/Up —/Up AE19 AD19 MH VDDEH4 —/Up —/Up AD19 AC19 MH VDDEH4 —/Up —/Up AC19 AA19 MH VDDEH4 —/Up —/Up AF20 AF20 MH VDDEH4 —/Up —/Up AE20 AE20 MH VDDEH4 —/Up —/Up AD20 AD20 P CNRXA FlexCAN A receive A1 RXDA eSCI A receive I A2 — — — G GPIO84 GPIO I/O P CNTXB FlexCAN B transmit O A1 PCSC3 DSPI C peripheral chip select O A2 — — — G GPIO85 GPIO I/O P CNRXB FlexCAN B receive I A1 PCSC4 DSPI C peripheral chip select O A2 — — — G GPIO86 GPIO I/O P CNTXC FlexCAN C transmit O A1 PCSD3 DSPI D peripheral chip select O A2 — — — G GPIO87 GPIO I/O P CNRXC FlexCAN C receive I A1 PCSD4 DSPI D peripheral chip select O A2 — — — G GPIO88 GPIO I/O P CNTXD FlexCAN D transmit O A1 — — — A2 — — — G GPIO246 GPIO I/O State after RESET8 87 State during RESET7 416 516 Function Summary Voltage6 Function Package Location Pad Type5 CNRXD_ GPIO247 4 Direction 247 Signal Name 2 P/A/G3 GPIO/PCR1 88 Table 39. Signal Properties and Muxing Summary (continued) I MH VDDEH4 —/Up —/Up AC20 AC20 MH VDDEH1 —/Up —/Up M2 K2 MH VDDEH1 —/Up —/Up M3 K3 MH VDDEH1 —/Up —/Up P1 K1 MH VDDEH1 —/Up —/Up N1 L5 MH VDDEH4 —/Up —/Up AF23 AF23 P CNRXD FlexCAN D receive A1 — — — A2 — — — G GPIO247 GPIO I/O State after RESET8 eSCI MPC5676R Microcontroller Data Sheet, Rev. 4 89 90 91 92 Freescale Semiconductor 244 TXDA_ GPIO89 RXDA _ GPIO90 TXDB_PCSD1_ GPIO91 RXDB_PCSD5_ GPIO92 TXDC_ETRIG0_ GPIO244 P TXDA eSCI A transmit O A1 — — — A2 — — — G GPIO89 GPIO I/O P RXDA eSCI A receive A1 — — — A2 — — — G GPIO90 GPIO I P TXDB eSCI B transmit O A1 PCSD1 DSPI D peripheral chip select O A2 — — — G GPIO91 GPIO I/O P RXDB eSCI B receive I A1 PCSD5 DSPI D peripheral chip select O A2 — — — G GPIO92 GPIO I/O P TXDC eSCI C transmit O A1 ETRIG0 eQADC trigger input I A2 — — — G GPIO244 GPIO I/O I State during RESET7 416 516 Function Summary Voltage6 Function Package Location Pad Type5 RXDC_ GPIO245 4 Direction 245 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I MH VDDEH5 —/Up —/Up AD22 AD22 MH VDDEH3 —/Up —/Up AD8 AB8 MH VDDEH3 —/Up —/Up AF7 AE7 MH VDDEH3 —/Up —/Up AD7 AC7 MH VDDEH3 —/Up —/Up AE6 AD6 MH VDDEH3 —/Up —/Up AC6 AC6 P RXDC eSCI C receive A1 — — — A2 — — — G GPIO245 GPIO I/O State after RESET8 DSPI MPC5676R Microcontroller Data Sheet, Rev. 4 93 94 95 96 97 SCKA_PCSC1_ GPIO93 SINA_PCSC2_ GPIO94 SOUTA_PCSC5_ GPIO95 PCSA0_PCSD2_ GPIO96 PCSA1_ PCSE0_GPIO97 P SCKA DSPI A clock I/O A1 PCSC1 DSPI C peripheral chip select O A2 — — — G GPIO93 GPIO I/O P SINA DSPI A data input I A1 PCSC2 DSPI C peripheral chip select O A2 — — — G GPIO94 GPIO I/O P SOUTA DSPI A data output O A1 PCSC5 DSPI C peripheral chip select O A2 — — — G GPIO95 GPIO I/O P PCSA0 DSPI A peripheral chip select I/O A1 PCSD2 DSPI D peripheral chip select O A2 — — — G GPIO96 GPIO I/O P PCSA1 DSPI A peripheral chip select O DSPI E peripheral chip select A1 A2 — — — G GPIO97 GPIO I/O 89 Freescale Semiconductor 103 SCKB_ GPIO102 SINB_ GPIO103 516 102 PCSA5_ETRIG1_ GPIO101 DSPI A peripheral chip select State during RESET7 416 101 PCSA4_ SCKE_GPIO100 PCSA2 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 100 PCSA3_ SINE_GPIO99 P Function Package Location Pad Type5 99 PCSA2_ SOUTE_GPIO98 4 Direction 98 Signal Name 2 P/A/G3 GPIO/PCR1 90 Table 39. Signal Properties and Muxing Summary (continued) O MH VDDEH3 —/Up —/Up AC7 AF6 MH VDDEH3 —/Up —/Up AE7 AD7 MH VDDEH3 —/Up —/Up AE5 AE5 MH VDDEH3 —/Up —/Up AD6 AA8 MH VDDEH3 —/Up —/Up AE8 AC8 MH VDDEH3 —/Up —/Up AE9 AB9 State after RESET8 DSPI E data output A1 A2 — — — G GPIO98 GPIO I/O P PCSA3 DSPI A peripheral chip select O DSPI E data input A1 A2 — — — G GPIO99 GPIO I/O P PCSA4 DSPI A peripheral chip select O DSPI E clock A1 A2 — — — G GPIO100 GPIO I/O P PCSA5 DSPI A peripheral chip select O A1 ETRIG1 eQADC trigger input I A2 — — — G GPIO101 GPIO I/O P SCKB DSPI B clock I/O A1 — — — A2 — — — G GPIO102 GPIO I/O P SINB DSPI B data input A1 — — — A2 — — — G GPIO103 GPIO I/O I 109 PCSB3_SINC_ GPIO108 PCSB4_SCKC_ GPIO109 516 108 PCSB2_SOUTC_ GPIO107 State during RESET7 416 107 PCSB1_PCSD0_ GPIO106 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 106 PCSB0_PCSD2_ GPIO105 Function Package Location Pad Type5 105 SOUTB_ GPIO104 4 Direction 104 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) O MH VDDEH3 —/Up —/Up AF9 AA10 MH VDDEH3 —/Up —/Up AD9 AF8 MH VDDEH3 —/Up —/Up AC9 AE8 MH VDDEH3 —/Up —/Up AF8 AD8 MH VDDEH3 —/Up —/Up AD10 AC9 MH VDDEH3 —/Up —/Up AC8 AF7 P SOUTB DSPI B data output A1 — — — A2 — — — G GPIO104 GPIO I/O P PCSB0 DSPI B peripheral chip select I/O A1 PCSD2 DSPI D peripheral chip select O A2 — — — G GPIO105 GPIO I/O P PCSB1 DSPI B peripheral chip select O A1 PCSD0 DSPI D peripheral chip select I/O A2 — — — G GPIO106 GPIO I/O P PCSB2 DSPI B peripheral chip select O A1 SOUTC DSPI C data output O A2 — — — G GPIO107 GPIO I/O P PCSB3 DSPI B peripheral chip select O A1 SINC DSPI C data input I A2 — — — G GPIO108 GPIO I/O P PCSB4 DSPI B peripheral chip select O A1 SCKC DSPI C clock I/O A2 — — — G GPIO109 GPIO I/O State after RESET8 91 Freescale Semiconductor 239 PCSC0_SOUT_C_LVDSM_ GPIO238 PCSC1_ GPIO239 516 238 SOUTC_SOUT_C_LVDSP_ GPIO237 State during RESET7 416 237 SINC_SCK_C_LVDSM_ GPIO236 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 236 SCKC_SCK_C_LVDSP_ GPIO235 Function Package Location Pad Type5 235 PCSB5_PCSC0_ GPIO110 4 Direction 110 Signal Name 2 P/A/G3 GPIO/PCR1 92 Table 39. Signal Properties and Muxing Summary (continued) O MH VDDEH3 —/Up —/Up AF6 AE6 MH+ LVDS VDDEH4 —/Up —/Up AD21 AD21 MH+ LVDS VDDEH4 —/Up —/Up AE22 AE22 MH+ LVDS VDDEH4 —/Up —/Up AF21 AF21 MH+ LVDS VDDEH4 —/Up —/Up AE21 AE21 MH VDDEH4 —/Up —/Up AC22 AC22 P PCSB5 DSPI B peripheral chip select A1 PCSC0 DSPI C peripheral chip select I/O A2 — — — G GPIO110 GPIO I/O P SCKC DSPI C clock I/O A1 SCK_C_LVDSP LVDS+ downstream signal positive output clock O A2 — — — G GPIO235 GPIO I/O P SINC DSPI C data input I A1 SCK_C_LVDSM LVDS– downstream signal negative output clock O A2 — — — G GPIO236 GPIO I/O P SOUTC DSPI C data output O A1 SOUT_C_LVDSP LVDS+ downstream signal positive output data O A2 — — — G GPIO237 GPIO I/O P PCSC0 DSPI C peripheral chip select I/O A1 SOUT_C_LVDSM LVDS– downstream signal negative output data O A2 — — — G GPIO238 GPIO I/O P PCSC1 DSPI C peripheral chip select O A1 — — — A2 — — — G GPIO239 GPIO I/O State after RESET8 516 PCSC5_GPIO243 State during RESET7 416 243 PCSC4_GPIO242 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 242 PCSC3_GPIO241 Function Package Location Pad Type5 241 PCSC2_GPIO240 4 Direction 240 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) O MH VDDEH5 —/Up —/Up AE23 AE23 MH VDDEH5 —/Up —/Up AD23 AD23 MH VDDEH5 —/Up —/Up AF24 AF24 MH VDDEH5 —/Up —/Up AE24 AE24 F VDDE9 —/Up —/Up — AD9 F VDDE8 —/Up —/Up — U1 P PCSC2 DSPI C peripheral chip select A1 — — — A2 — — — G GPIO240 GPIO I/O P PCSC3 DSPI C peripheral chip select O A1 — — — A2 — — — G GPIO241 GPIO I/O P PCSC4 DSPI C peripheral chip select O A1 — — — A2 — — — G GPIO242 GPIO I/O P PCSC5 DSPI C peripheral chip select O A1 — — — A2 — — — G GPIO243 GPIO I/O State after RESET8 EBI 256 257 D_CS0_ GPIO256 D_CS2_D_ADD_DAT31_ GPIO257 P D_CS0 EBI chip select 0 O A1 — — — A2 — — — G GPIO256 GPIO I/O P D_CS2 EBI chip select 2 O A1 D_ADD_DAT31 Address and data in mux mode. I/O A2 — — — G GPIO257 GPIO I/O 93 Freescale Semiconductor 263 D_ADD15_ GPIO262 D_ADD16_D_ADD_DAT16_ GPIO263 516 262 D_ADD14_ GPIO261 State during RESET7 416 261 D_ADD13_ GPIO260 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 260 D_ADD12_ GPIO259 Function Package Location Pad Type5 259 D_CS3_D_TEA_ GPIO258 4 Direction 258 Signal Name 2 P/A/G3 GPIO/PCR1 94 Table 39. Signal Properties and Muxing Summary (continued) O F VDDE8 —/Up —/Up — T6 F VDDE8 —/Up —/Up — R1 F VDDE8 —/Up —/Up — R2 F VDDE8 —/Up —/Up — R3 F VDDE8 —/Up —/Up — R4 F VDDE8 —/Up —/Up — R5 P D_CS3 EBI chip select 3 A1 D_TEA EBI transfer error acknowledge I/O A2 — — — G GPIO258 GPIO I/O P D_ADD12 EBI address bus O A1 — — — A2 — — — G GPIO259 GPIO I/O P D_ADD13 EBI address bus O A1 — — — A2 — — — G GPIO260 GPIO I/O P D_ADD14 EBI address bus O A1 — — — A2 — — — G GPIO261 GPIO I/O P D_ADD15 EBI address bus O A1 — — — A2 — — — G GPIO262 GPIO I/O P D_ADD16 EBI address bus O A1 D_ADD_DAT16 Address and data in mux mode. I/O A2 — — — G GPIO263 GPIO I/O State after RESET8 269 D_ADD21_D_ADD_DAT21_ GPIO268 D_ADD22_D_ADD_DAT22_ GPIO269 516 268 D_ADD20_D_ADD_DAT20_ GPIO267 State during RESET7 416 267 D_ADD19_D_ADD_DAT19_ GPIO266 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 266 D_ADD18_D_ADD_DAT18_ GPIO265 Function Package Location Pad Type5 265 D_ADD17_D_ADD_DAT17_ GPIO264 4 Direction 264 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) O F VDDE8 —/Up —/Up — T5 F VDDE8 —/Up —/Up — T2 F VDDE8 —/Up —/Up — T3 F VDDE8 —/Up —/Up — T4 F VDDE9 —/Up —/Up — AB11 F VDDE9 —/Up —/Up — AD10 P D_ADD17 EBI address bus A1 D_ADD_DAT17 Address and data in mux mode. I/O A2 — — — G GPIO264 GPIO I/O P D_ADD18 EBI address bus O A1 D_ADD_DAT18 Address and data in mux mode. I/O A2 — — — G GPIO265 GPIO I/O P D_ADD19 EBI address bus O A1 D_ADD_DAT19 Address and data in mux mode. I/O A2 — — — G GPIO266 GPIO I/O P D_ADD20 EBI address bus O A1 D_ADD_DAT20 Address and data in mux mode. I/O A2 — — — G GPIO267 GPIO I/O P D_ADD21 EBI address bus O A1 D_ADD_DAT21 Address and data in mux mode. I/O A2 — — — G GPIO268 GPIO I/O P D_ADD22 EBI address bus O A1 D_ADD_DAT22 Address and data in mux mode. I/O A2 — — — G GPIO269 GPIO I/O State after RESET8 95 Freescale Semiconductor 275 D_ADD27_D_ADD_DAT27_ GPIO274 D_ADD28_D_ADD_DAT28_ GPIO275 516 274 D_ADD26_D_ADD_DAT26_ GPIO273 State during RESET7 416 273 D_ADD25_D_ADD_DAT25_ GPIO272 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 272 D_ADD24_D_ADD_DAT24_ GPIO271 Function Package Location Pad Type5 271 D_ADD23_D_ADD_DAT23_ GPIO270 4 Direction 270 Signal Name 2 P/A/G3 GPIO/PCR1 96 Table 39. Signal Properties and Muxing Summary (continued) O F VDDE9 —/Up —/Up — AE10 F VDDE9 —/Up —/Up — AF10 F VDDE9 —/Up —/Up — AD11 F VDDE9 —/Up —/Up — AE11 F VDDE9 —/Up —/Up — AF11 F VDDE9 —/Up —/Up — AD12 P D_ADD23 EBI address bus A1 D_ADD_DAT23 Address and data in mux mode. I/O A2 — — — G GPIO270 GPIO I/O P D_ADD24 EBI address bus O A1 D_ADD_DAT24 Address and data in mux mode. I/O A2 — — — G GPIO271 GPIO I/O P D_ADD25 EBI address bus O A1 D_ADD_DAT25 Address and data in mux mode. I/O A2 — — — G GPIO272 GPIO I/O P D_ADD26 EBI address bus O A1 D_ADD_DAT26 Address and data in mux mode. I/O A2 — — — G GPIO273 GPIO I/O P D_ADD27 EBI address bus O A1 D_ADD_DAT27 Address and data in mux mode. I/O A2 — — — G GPIO274 GPIO I/O P D_ADD28 EBI address bus O A1 D_ADD_DAT28 Address and data in mux mode. I/O A2 — — — G GPIO275 GPIO I/O State after RESET8 281 D_ADD_DAT2_ GPIO280 D_ADD_DAT3_ GPIO281 516 280 D_ADD_DAT1_ GPIO279 State during RESET7 416 279 D_ADD_DAT0_ GPIO278 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 278 D_ADD30_D_ADD_DAT30_ GPIO277 Function Package Location Pad Type5 277 D_ADD29_D_ADD_DAT29_ GPIO276 4 Direction 276 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) O F VDDE9 —/Up —/Up — AB12 F VDDE9 —/Up —/Up — AE12 F VDDE10 —/Up —/Up — P25 F VDDE10 —/Up —/Up — P26 F VDDE10 —/Up —/Up — N24 F VDDE10 —/Up —/Up — N25 P D_ADD29 EBI address bus A1 D_ADD_DAT29 Address and data in mux mode. I/O A2 — — — G GPIO276 GPIO I/O P D_ADD30 EBI address bus O A1 D_ADD_DAT30 Address and data in mux mode. I/O A2 — — — G GPIO277 GPIO I/O P D_ADD_DAT0 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO278 GPIO I/O P D_ADD_DAT1 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO279 GPIO I/O P D_ADD_DAT2 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO280 GPIO I/O P D_ADD_DAT3 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO281 GPIO I/O State after RESET8 97 D_ADD_DAT8_ GPIO286 516 286 D_ADD_DAT7_ GPIO285 State during RESET7 416 285 D_ADD_DAT6_ GPIO284 Function Summary Voltage6 284 D_ADD_DAT5_ GPIO283 Function Package Location Pad Type5 MPC5676R Microcontroller Data Sheet, Rev. 4 283 D_ADD_DAT4_ GPIO282 4 Direction 282 Signal Name 2 P/A/G3 GPIO/PCR1 98 Table 39. Signal Properties and Muxing Summary (continued) I/O F VDDE10 —/Up —/Up — N26 F VDDE10 —/Up —/Up — M25 F VDDE10 —/Up —/Up — N22 F VDDE10 —/Up —/Up — M24 F VDDE10 —/Up —/Up — M23 Freescale Semiconductor P D_ADD_DAT4 EBI data only in non-mux mode. Address and data in mux mode. A1 — — — A2 — — — G GPIO282 GPIO I/O P D_ADD_DAT5 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO283 GPIO I/O P D_ADD_DAT6 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO284 GPIO I/O P D_ADD_DAT7 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO285 GPIO I/O P D_ADD_DAT8 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO286 GPIO I/O State after RESET8 D_ADD_DAT13 _GPIO291 516 291 D_ADD_DAT12_ GPIO290 State during RESET7 416 290 D_ADD_DAT11_ GPIO289 Function Summary Voltage6 289 D_ADD_DAT10_ GPIO288 Function Package Location Pad Type5 MPC5676R Microcontroller Data Sheet, Rev. 4 288 D_ADD_DAT9_ GPIO287 4 Direction 287 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I/O F VDDE10 —/Up —/Up — M22 F VDDE10 —/Up —/Up — L26 F VDDE10 —/Up —/Up — L25 F VDDE10 —/Up —/Up — L24 F VDDE10 —/Up —/Up — L23 P D_ADD_DAT9 EBI data only in non-mux mode. Address and data in mux mode. A1 — — — A2 — — — G GPIO287 GPIO I/O P D_ADD_DAT10 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO288 GPIO I/O P D_ADD_DAT11 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO289 GPIO I/O P D_ADD_DAT12 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO290 GPIO I/O P D_ADD_DAT13 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO291 GPIO I/O State after RESET8 99 295 296 Freescale Semiconductor 297 D_RD_WR_GPIO294 D_WE0_GPIO295 D_WE1_GPIO296 D_OE_GPIO297 516 294 D_ADD_DAT15_GPIO293 State during RESET7 416 MPC5676R Microcontroller Data Sheet, Rev. 4 293 Function Summary Voltage6 D_ADD_DAT14_GPIO292 Function Package Location Pad Type5 292 4 Direction Signal Name 2 P/A/G3 GPIO/PCR1 100 Table 39. Signal Properties and Muxing Summary (continued) I/O F VDDE10 —/Up —/Up — L22 F VDDE10 —/Up —/Up — K26 F VDDE10 —/Up —/Up — R26 F VDDE8 —/Up —/Up — N1 F VDDE8 —/Up —/Up — P5 F VDDE10 —/Up —/Up — P23 P D_ADD_DAT14 EBI data only in non-mux mode. Address and data in mux mode. A1 — — — A2 — — — G GPIO292 GPIO I/O P D_ADD_DAT15 EBI data only in non-mux mode. Address and data in mux mode. I/O A1 — — — A2 — — — G GPIO293 GPIO I/O P D_RD_WR EBI read/write O A1 — — — A2 — — — G GPIO294 GPIO I/O P D_WE0 EBI write enable O A1 — — — A2 — — — G GPIO295 GPIO I/O P D_WE1 EBI write enable O A1 — — — A2 — — — G GPIO296 GPIO I/O P D_OE EBI output enable O A1 — — — A2 — — — G GPIO297 GPIO I/O State after RESET8 303 D_BDIP_GPIO302 D_WE2_GPIO303 516 302 D_CS1_GPIO301 State during RESET7 416 301 D_TA_GPIO300 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 300 D_ALE_GPIO299 Function Package Location Pad Type5 299 D_TS_GPIO298 4 Direction 298 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) O F VDDE9 —/Up —/Up — AE9 F VDDE10 —/Up —/Up — P24 F VDDE9 —/Up —/Up — AF9 F VDDE9 —/Up —/Up — AB10 F VDDE8 —/Up —/Up — M2 F VDDE8 —/Up —/Up — N2 P D_TS EBI transfer start A1 — — — A2 — — — G GPIO298 GPIO I/O P D_ALE EBI Address Latch Enable O A1 — — — A2 — — — G GPIO299 GPIO I/O P D_TA EBI transfer acknowledge I/O A1 — — — A2 — — — G GPIO300 GPIO I/O P D_CS1 EBI chip select O A1 — — — A2 — — — G GPIO301 GPIO I/O P D_BDIP EBI burst data in progress O A1 — — — A2 — — — G GPIO302 GPIO I/O P D_WE2 EBI write enable O A1 — — — A2 — — — G GPIO303 GPIO I/O State after RESET8 101 516 D_ADD11_GPIO307 State during RESET7 416 307 D_ADD10_GPIO306 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 306 D_ADD9_GPIO305 Function Package Location Pad Type5 305 D_WE3_GPIO304 4 Direction 304 Signal Name 2 P/A/G3 GPIO/PCR1 102 Table 39. Signal Properties and Muxing Summary (continued) O F VDDE8 —/Up —/Up — N3 F VDDE8 —/Up —/Up — P1 F VDDE8 —/Up —/Up — P2 F VDDE8 —/Up —/Up — P3 P D_WE3 EBI write enable A1 — — — A2 — — — G GPIO304 GPIO I/O P D_ADD9 EBI address bus O A1 — — — A2 — — — G GPIO305 GPIO I/O P D_ADD10 EBI address bus O A1 — — — A2 — — — G GPIO306 GPIO I/O P D_ADD11 EBI address bus O A1 — — — A2 — — — G GPIO307 GPIO I/O State after RESET8 Reset and Clocks — Freescale Semiconductor RESET P RESET External reset input I MH VDDEH1 RESET/Up RESET/Up R2 N5 230 RSTOUT P RSTOUT External reset output O MH VDDEH1 RSTOUT/Low RSTOUT/ High A3 A3 211 BOOTCFG0_IRQ2_ GPIO211 P BOOTCFG0 Boot configuration I MH VDDEH1 —/Down — L4 A1 IRQ2 BOOTCFG/ Down A2 — — — G GPIO211 GPIO I/O I 516 PLLCFG1_IRQ5_GPIO209 416 209 PLLCFG0_IRQ4_ GPIO208 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 208 WKPCFG_NMI_ GPIO21310 Function Package Location Pad Type5 213 BOOTCFG1_IRQ3_ GPIO212 4 Direction 212 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) I MH VDDEH1 BOOTCFG/ Down —/Down N2 L3 MH VDDEH1 WKPCFG/Up —/Up N3 M5 MH VDDEH1 PLLCFG/Up —/Up R3 M3 MH VDDEH1 PLLCFG/Up —/Up P2 L1 P BOOTCFG1 Boot configuration A1 IRQ3 External interrupt request I A2 — — — G GPIO212 GPIO I/O P WKPCFG Weak pull configuration input A2 — — G GPIO213 GPIO I P PLLCFG0 FMPLL mode configuration input I A1 IRQ4 External interrupt request I A2 — — — G GPIO208 GPIO I/O P PLLCFG1 FMPLL mode configuration input I A1 IRQ5 External interrupt request I A2 SOUTD DSPI D data output O G GPIO209 GPIO I/O I State during RESET7 State after RESET8 A1 — — PLLCFG2 P PLLCFG2 FMPLL mode configuration input I MH VDDEH1 PLLCFG/ Down —/ Down P3 L2 — XTAL P XTAL Crystal oscillator output O AE VDD33 XTAL XTAL AC26 AC26 — EXTAL P EXTAL Crystal oscillator input I AE VDD33 EXTAL EXTAL AB26 AB26 229 D_CLKOUT P D_CLKOUT EBI system clock output O F VDDE9 CLKOUT/ Enabled CLKOUT/ Enabled — AF12 214 ENGCLK P ENGCLK EBI engineering clock output Note: EXTCLK (External clock input) selected through SIU register) O F VDDE2 ENGCLK/ Enabled ENGCLK/ Enabled AD1 AD1 F VDDE2 —/Up EVTI/Up T4 V1 JTAG and Nexus (see footnote11 about resets) 103 — EVTI –12 EVTI Nexus event in I Voltage6 State during RESET7 416 516 227 EVTO (the BAM uses this pin to select if auto baud rate is on or off) –12 EVTO Nexus event out O F VDDE2 ABS/Up EVTO/HI U1 V2 219 MCKO –12 MCKO Nexus message clock out O F VDDE2 O/Low Disabled13 T2 U4 MDO0_GPIO220 –12 MDO014 Nexus message data out O Note15 U3 V3 A1 — — — A2 — — — G GPIO220 GPIO I/O – MDO114 Nexus message data out O A1 — — — A2 — — — G GPIO221 GPIO I/O – MDO214 Nexus message data out O A1 — — — A2 — — — G GPIO222 GPIO I/O 220 MPC5676R Microcontroller Data Sheet, Rev. 4 221 222 223 75 Signal Name MDO1_GPIO221 MDO2_GPIO222 MDO3_GPIO223 MDO4_GPIO75 2 P/A/G3 Pad Type5 Package Location Direction GPIO/PCR1 104 Table 39. Signal Properties and Muxing Summary (continued) 12 12 4 Function 14 Function Summary Freescale Semiconductor –12 MDO3 Nexus message data out O A1 — — — A2 — — — G GPIO223 GPIO I/O –12 MDO414 Nexus message data out O A1 — — — A2 — — — G GPIO75 GPIO I/O See Note15 State after RESET8 F VDDE2 See F VDDE2 O/Low —/Down U4 W6 F VDDE2 O/Low —/Down V1 V4 F VDDE2 O/Low —/Down V2 V5 F VDDE2 O/Low —/Down V3 W1 81 MDO9_GPIO80 MDO10_GPIO81 516 80 MDO8_GPIO79 State during RESET7 416 79 MDO7_GPIO78 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 78 MDO6_GPIO77 Function O F VDDE2 O/Low —/Down V4 W2 F VDDE2 O/Low —/Down W1 W3 F VDDE2 O/Low —/Down W2 Y1 F VDDE2 O/Low —/Down W3 W5 F VDDE2 O/Low —/Down Y1 Y2 F VDDE2 O/Low —/Down Y2 Y3 –12 MDO514 Nexus message data out A1 — — — A2 — — — G GPIO76 GPIO I/O – MDO614 Nexus message data out O A1 — — — A2 — — — G GPIO77 GPIO I/O – MDO714 Nexus message data out O A1 — — — A2 — — — G GPIO78 GPIO I/O –12 MDO814 Nexus message data out O A1 — — — A2 — — — G GPIO79 GPIO I/O – MDO914 Nexus message data out O A1 — — — A2 — — — G GPIO80 GPIO I/O – MDO1014 Nexus message data out O A1 — — — A2 — — — G GPIO81 GPIO I/O 12 12 12 12 Package Location Pad Type5 77 MDO5_GPIO76 4 Direction 76 Signal Name 2 P/A/G3 GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) State after RESET8 105 Freescale Semiconductor 224 225 226 — — 228 — MDO15_GPIO234 MSEO0 516 234 MDO14_GPIO233 State during RESET7 416 233 MDO13_GPIO232 Function Summary Voltage6 MPC5676R Microcontroller Data Sheet, Rev. 4 232 MDO12_GPIO231 Function O F VDDE2 O/Low —/Down Y3 Y4 F VDDE2 O/Low —/Down AA1 Y5 F VDDE2 O/Low —/Down AA2 AA1 F VDDE2 O/Low —/Down AA3 AA2 F VDDE2 O/Low —/Down Y4 AA3 –12 MDO1114 Nexus message data out A1 — — — A2 — — — G GPIO82 GPIO I/O – MDO1214 Nexus message data out O A1 — — — A2 — — — G GPIO231 GPIO I/O – MDO1314 Nexus message data out O A1 — — — A2 — — — G GPIO232 GPIO I/O –12 MDO1414 Nexus message data out O A1 — — — A2 — — — G GPIO233 GPIO I/O – MDO1514 Nexus message data out O A1 — — — A2 — — — G 12 12 12 Package Location Pad Type5 231 MDO11_GPIO82 4 Direction 82 Signal Name 2 P/A/G3 GPIO/PCR1 106 Table 39. Signal Properties and Muxing Summary (continued) State after RESET8 GPIO234 GPIO I/O 12 MSEO014 Nexus message start/end out O F VDDE2 O/Low MSEO/HI U2 U6 12 – MSEO1 – MSEO114 Nexus message start/end out O F VDDE2 O/Low MSEO/HI T3 U5 RDY –12 RDY Nexus ready output O F VDDE2 O/Low RDY/HI R4 U3 TCK 12 TCK JTAG test clock input I F VDDE2 TCK/Down TCK/Down AB2 AB2 12 – TDI – TDI JTAG test data input I F VDDE2 TDI/Up TDI/Up AC2 AC2 TDO –12 TDO JTAG test data output O F VDDE2 TDO/Up TDO/Up AB1 AB1 TMS 12 TMS JTAG test mode select input I F VDDE2 TMS/Up TMS/Up AB3 AB3 – 2 3 4 5 6 7 8 Voltage6 State during RESET7 416 516 — JCOMP –12 JCOMP JTAG TAP controller enable I F VDDE2 JCOMP/Down JCOMP/Down R1 U2 — TEST — TEST Test mode select (not for customer use) I F VDDEH1 TEST/Down TEST/Down B4 B4 — VDDSYN — VDDSYN Clock synthesizer power input I/O VDDE VDDSYN VDDSYN VDDSYN AD26 AD26 — VSSSYN — VSSSYN Clock synthesizer ground input I VSSE VDDSYN VSSSYN VSSSYN AA26 AA26 — VSTBY — VSTBY SRAM standby power input I VHV VDDEH1 VSTBY VSTBY M4 M4 — REGSEL — REGSEL Selects regulator mode (Linear/Switch mode) I AE VDDREG REGSEL REGSEL W23 W23 — REGCTL — REGCTL Regulator controller output to base/gate of power transistor O AE VDDREG REGCTL REGCTL Y26 Y26 — VSSFL — VSSFL Tie to VSS I VSS VDDREG VSSFL VSSFL AB25 AB25 — VDDREG — VDDREG Source voltage for on-chip regulators and Low voltage detect circuits I VDDINT VDDREG VDDREG VDDREG AA25 AA25 Signal Name 2 P/A/G3 Pad Type5 MPC5676R Microcontroller Data Sheet, Rev. 4 1 Package Location Direction GPIO/PCR1 Freescale Semiconductor Table 39. Signal Properties and Muxing Summary (continued) 4 Function Function Summary State after RESET8 107 The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not have GPIO functionality, this number is the PCR number. The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type. P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO. Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are designated in the PA field of the SIU_PCRn registers except where explicitly noted. MH = High voltage, medium speed F = Fast speed FS = Fast speed with slew AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad) VHV = Very high voltage VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5%/–10%) power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply. All pins are sampled after the internal POR is negated. The terminology used in this column is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select (during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled. The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin. 9 Freescale Semiconductor During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device. 10 NMI function is selected using the SIU_IREER/SIU_IFEER registers and has priority over any other function on this pin. 11 Nexus reset is different than system reset; MDO0-11 are enabled in RPM or FPM trace modes, while MDO12-15 are enabled in FPM trace mode only. MSEO and MCKO are also dependent on trace (RPM or FPM) being enabled. 12 The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values have no effect on the function of these pins once enabled. 13 MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register). 14 Do not connect pin directly to a power supply or ground. 15 While JCOMP is negated, the MDO0 pad is pulled up because of the default values in its SIU PCR. When JCOMP is asserted, the MDO0 pad is enabled as an output and goes low when the system clock is present. MPC5676R Microcontroller Data Sheet, Rev. 4 108 Revision History Appendix B Revision History Table 40 describes the changes made to this document between revisions. Table 40. Revision History Revision Date Description Rev 1 5 Aug 2011 Initial customer release Rev 2 21 Dec 2011 Added information about specs 1a through 1d in the PMC Electrical Specifications table. Updated the footnote reference (changed from 13 to 14) of spec 18 of the PMC Electrical Specifications table. Updated the Operating Current 5.0 V Supplies @ fsys = 180MHz VDDA Max value (changed from 30 to 50). Updated footnote 1 of the VDD33 Pad Average DC Current table (changed IDDE to IDD33). Updated the pF value of 11 SRC/DSC Fast with Slew Rate (changed from 2.6 to 200) in the Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V) table. Added a footnote for ANA0-ANA7 (9) functions in the “Signal Properties and Muxing Summary” table. Added a footnote for MDO0-MDO15 (14) and MSEO0 functions in the “Signal Properties and Muxing Summary” table. Updated figure numbers 25, 27, 29, and 31: Added specs 1-4. Changed the title of the “PFCPR1 Settings” table to “BIUCR1/BIUCR3”. Added a new row “Load” under “Termination” in the “DSPI LVDS Pad Specification” table. Updated the “Max” and “Typical” values of “Delay, Z to Normal”, “Rise/Fall Time”, and “Data Frequency” in the “DSPI LVDS Pad Specification” table. Changed “VDDE” to “VDDEH” in footnote 10 of the “DC Electrical Specifications” table. Made the following changes in the “DSPI Timing” table: • Update the minimum peripheral bus frequencies for “Data Setup Time for Inputs” and “Data Hold Time for Outputs”. • Updated the maximum peripheral bus frequencies for “Data Valid (after SCK edge)”. • Added “Master (LVDS)” information for “Data Valid (after SCK edge)” and “Data Hold Time for Outputs”. Changed the minimum voltage value of the “I/O Supply Voltage (fast I/O pads)” from “1.62 V” to “3.0 V” in the “DC Electrical Specifications” table. Changed “VDDE” values from “1.62 V to 1.98 V” to “3.0 V to 3.6 V” in footnote 1 of the “Pad AC Specifications (VDDEH = 5.0 V, VDDE = 3.3 V)” table. Removed voltage ranges “1.62 V–1.98 V” and “2.25 V–2.75 V” from “Fast I/O Weak Pull Up/Down Current” in the “DC Electrical Specifications” table. MPC5676R Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 109 Revision History Table 40. Revision History (continued) Revision Date Description Rev 3 10 August 2012 Added minimum and maximum “Nominal bandgap reference voltage” values in the “PMC Electrical Specifications” table. Updated the maximum “Medium I/O Output Low Voltage” value (changed from 0.2 x VDDEH to 0.2 x VDDEH and 0.15 x VDDEH ) in the “DC Electrical Specifications” table, moved reference to the footnote 10 (IOH_S = {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with VDDEH = 4.5 V; IOH_S = {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with VDDEH = 3.0 V) to “0.2 x VDDEH”, and added a new footnote 11(IOL_S=2 mA) to “0.15 x VDDEH”. Updated footnote9 (IOH_F = {12,20,30,40} mA and IOL_F = {24,40,50,65} mA for {00,01,10,11} drive mode with VDDE = 3.0 V): Removed “IOH_F = {7,13,18,25} mA and IOL_F = {18,30,35,50} mA for {00,01,10,11} drive mode with VDDE = 2.25 V; IOH_F = {3,7,10,16}mA and IOL_F = {12,20,27,35} mA for {00,01,10,11} drive mode with VDDE = 1.62 V”. Added minimum and maximum values to all rows of the “Power Management Control (PMC) Specification” table. Updated the “Accuracy” temperature values in the “Temperature Sensor Electrical Specifications” table: Changed “–40 C to 100 C to 40 C to 150 C, removed the correspnding “Typ” value, removed “100 C to 150 C, and added minimum (10) and maximum (+10) values. Added a new section “ADC Internal Resource Measurements” and moved “Power Management Control (PMC) Specification”, “Standby RAM Regulator Electrical Specifications”, “ADC Band Gap Reference / LVI Electrical Specifications”, and “Temperature Sensor Electrical Specifications” tables to the section. Changed “Minimum Data Retention at 25 °C ambient temperature” to “Minimum Data Retention at 85 °C ambient temperature” in the “Flash EEPROM Module Life” table. Added the following note after “Flash Program and Erase Specifications (Pending Si characterization)” table in the “C90 Flash Memory Electrical Characteristics” section: “The low, mid, and high address blocks of the flash arrays are erased (all bits set to 1) before leaving the factory. Updated the “DSPI LVDS Pad Specification” table: Changed maximum “Load” value from “25” to “32”; minimum values for “Differential Output Voltage SRC=0b00 or 0b11, SRC=0b01, SRC=0b10” from “150, 90, 160” to “215, 170, 260”; “Transmission lines (Differential) to “Termination Resistance”; “Zc” to “RLoad”; and added the following footnote: “The termination resistance spec is not meant to specify the receiver termination requirements. They are there to establish the measurement criteria for the specs in this table. As per the TIA/EIA-644A standard, the LVDS receiver termination resistance can vary from 90 to 132  . Rev 4 21 January 2016 Added a table “Flash Memory AC Timing Specifications”. Updated the min and max values from -10 and +10 to -20 and +20 for “Accuracy” in the “Temperature Sensor Electrical Specifications” table. MPC5676R Microcontroller Data Sheet, Rev. 4 110 Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. 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U.S. Pat. & Tm. Off. the power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2016. All rights reserved. Document Number: MPC5676R Rev. 4 16 Feb 2016