NXP Semiconductors
Data Sheet: Technical Data
Document Number MPC5748G
Rev. 6, 11/2018
MPC5748G
MPC5748G Microcontroller
Data Sheet
Features
• 2 x 160 MHz Power Architecture® e200Z4 Dual issue,
32-bit CPU
– Single precision floating point operations
– 8 KB instruction cache and 4 KB data cache
– Variable length encoding (VLE) for significant code
density improvements
• 1 x 80 MHz Power Architecture® e200Z2 Single issue,
32-bit CPU
– Using variable length encoding (VLE) for
significant code size footprint reduction
• End to end ECC
– All bus masters, for example, cores generate single
error correction, double error detection (SECDED)
code for every bus transaction
– SECDED covers 64-bit data and 29-bit address
• Memory interfaces
– 6 MB on-chip flash supported with the flash
controller
– 3 x flash page buffers (3 port flash controller)
– 768 KB on-chip SRAM across three RAM ports
• Clock interfaces
– 8-40 MHz external crystal (FXOSC)
– 16 MHz IRC (FIRC)
– 128 KHz IRC (SIRC)
– 32 KHz external crystal (SXOSC)
– Clock Monitor Unit (CMU)
– Frequency modulated phase-locked loop (FMPLL)
– Real Time Counter (RTC)
• 2x System Memory Protection Unit (SMPU) each with
16 region descriptors and 16-byte region granularity
• 16 Semaphores to manage access to shared resource
• Interrupt controller (INTC) capable of routing
interrupts to any CPU
• Multiple crossbar switch architecture for concurrent
access to peripherals, flash, and RAM from multiple
bus masters
• Boot Assist Flash (BAF) supports internal flash
programming via a serial link (LIN / SCI)
• Analog
– Two analog-to-digital converters (ADC), one 10-bit
and one 12-bit
– Three analogue comparators
– Cross Trigger Unit to enable synchronization of
ADC conversions with a timer event from the
eMIOS or from the PIT
• Communication
– Four Deserial Peripheral Interface (DSPI)
– Six Serial Peripheral interface (SPI)
– 18 serial communication interface (LIN) modules
– Eight enhanced FlexCAN3 with FD support
– Four inter-IC communication interface (IIC)
– One USB OTG Controller (USB_0) and One USB
SPH Controller (USB_1) with ULPI Interface.
– ENET complex (10/100 Ethernet) that supports
Multi queue with AVB support, 1588, and MII/
RMII
– 2 x ENET with L2 switch
– Secure Digital Hardware Controller (uSDHC)
– Dual-channel FlexRay Controller
• Audio
– 3 x Synchronous Audio Interface (SAI)
– Fractional clock dividers (FCD) operating in
conjunction with the SAIs
• Configurable I/O domains supporting FLEXCAN,
LINFlex, Ethernet, USB, MLB, uSDHC and general
I/O
• Supports wake-up from low power modes via the
WKPU controller
• On-chip voltage regulator (VREG)
• Debug functionality
– e200Z2 core:NDI per IEEE-ISTO 5001-2008
Class3+
– e200Z4 core(s): NDI per IEEE-ISTO 5001-2008
Class 3+
• 32-channels eDMA controller with multiple transfer
request sources using DMAMUX
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Timer
– 16 Periodic Interrupt Timers (PITs)
– Three System Timer Module (STM)
– Four Software WatchDog Timers (SWT)
– 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and
1149.7 (cJTAG)
• Security
– Hardware Security Module (HSMv2)
– Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management
– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts
• Functional Safety
– ISO26262 ASIL compliance
• Multiple operating modes
– Includes enhanced low power operation
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
2
NXP Semiconductors
Table of Contents
1
Block diagram.................................................................................... 4
6.3.5
Flash memory AC timing specifications................... 40
2
Family comparison.............................................................................4
6.3.6
Flash read wait state and address pipeline control
3
Ordering parts.....................................................................................9
4
5
6
3.1
Determining valid orderable parts ..........................................9
3.2
Ordering Information ............................................................. 9
settings ...................................................................... 41
6.4
General............................................................................................... 10
Communication interfaces.......................................................41
6.4.1
DSPI timing............................................................... 41
6.4.2
FlexRay electrical specifications............................... 47
4.1
Absolute maximum ratings..................................................... 10
6.4.2.1
FlexRay timing...................................... 47
4.2
Recommended operating conditions....................................... 11
6.4.2.2
TxEN......................................................48
4.3
Voltage regulator electrical characteristics............................. 13
6.4.2.3
TxD........................................................ 49
4.4
Voltage monitor electrical characteristics............................... 16
6.4.2.4
RxD........................................................50
4.5
Supply current characteristics................................................. 18
6.4.3
uSDHC specifications............................................... 51
4.6
Electrostatic discharge (ESD) characteristics......................... 21
6.4.4
Ethernet switching specifications.............................. 52
4.7
Electromagnetic Compatibility (EMC) specifications............ 22
6.4.5
MediaLB (MLB) electrical specifications.................54
I/O parameters....................................................................................22
6.4.5.1
MLB 3-pin interface DC characteristics54
5.1
AC specifications @ 3.3 V Range...........................................22
6.4.5.2
MLB 3-pin interface electrical
5.2
DC electrical specifications @ 3.3V Range............................23
5.3
AC specifications @ 5 V Range..............................................24
5.4
DC electrical specifications @ 5 V Range..............................25
6.4.6.1
USB electrical specifications................. 56
5.5
Reset pad electrical characteristics..........................................26
6.4.6.2
ULPI timing specifications.................... 56
5.6
PORST electrical specifications..............................................28
specifications......................................... 54
6.4.6
6.4.7
Peripheral operating requirements and behaviours............................ 28
6.1
6.2
SAI electrical specifications ..................................... 58
Debug specifications............................................................... 60
Analog..................................................................................... 28
6.5.1
JTAG interface timing .............................................. 60
6.1.1
ADC electrical specifications.................................... 28
6.5.2
Nexus timing............................................................. 62
6.1.2
Analog Comparator (CMP) electrical specifications 32
6.5.3
WKPU/NMI timing................................................... 64
Clocks and PLL interfaces modules........................................33
6.5.4
External interrupt timing (IRQ pin)...........................65
6.2.1
Main oscillator electrical characteristics................... 33
6.2.2
32 kHz Oscillator electrical specifications ............... 35
6.2.3
16 MHz RC Oscillator electrical specifications........ 35
6.2.4
128 KHz Internal RC oscillator Electrical
specifications ............................................................ 36
6.2.5
6.3
6.5
USB electrical specifications.....................................56
PLL electrical specifications .................................... 36
Memory interfaces...................................................................37
7
Thermal attributes.............................................................................. 65
7.1
8
Dimensions.........................................................................................67
8.1
9
Thermal attributes................................................................... 65
Obtaining package dimensions ...............................................67
Pinouts................................................................................................68
9.1
Package pinouts and signal descriptions................................. 68
10 Reset sequence................................................................................... 68
6.3.1
Flash memory program and erase specifications.......37
10.1 Reset sequence duration.......................................................... 68
6.3.2
Flash memory Array Integrity and Margin Read
10.2 BAF execution duration.......................................................... 68
specifications............................................................. 38
10.3 Reset sequence description......................................................69
6.3.3
Flash memory module life specifications..................39
11 Revision History.................................................................................71
6.3.4
Data retention vs program/erase cycles..................... 39
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
3
Block diagram
1 Block diagram
System bus masters
80 MHz e200z2
uSDHC
MLB150
160 MHz e200z4
64-bit AHB
HSM
8 KB i-cache 4 KB d-cache
E2 E-ECC
Ethernet(ENET)
Ethernet Switch
eDMA
Flexray
WKPU
3 x STM
HS_USBSPH
HS_USBOTG
BAF
PMC
FMPLL
16 MHz FIRC
RTC/API
DEBUG/
JTAG
160 MHz e200z4
SPFP-APU
Nexus 3+
E2 E-ECC
64-bit AHB
Nexus 3+
64-bit data
System
E2 E-ECC
SMPU
4 x SWTs
FCCU
3 x DSMC
2 x DSMC
16 x SEMA4
PASS
16 x PIT-RTI
SSCM
32 KHz
SXOSC
MC_CGM,
MC_PCU,
MC_ME,
MC_RGM
128 KHz
SIRC
SIUL
8–40 MHz
FXOSC
STCU
(MBIST/
LBIST)
2 x MEMU
CMU
Padkeeper
support
TDM
Flash
3xRAM
E2 E-ECC
E2 E-ECC
3 x SA-PF buffers
64-bit wide RAM
Triple ported
256 KB array
6 MB array (inc EEE)
256 KB array
Peripheral
bridge
E2 E-ECC
Low power
unit interface
256 KB array
Peripheral clusters
80 ch 10-bit ADC0 64 ch 12-bit ADC1 1 x FlexCAN(PN)
(mix int and ext)
(mix int and ext)
7 x FlexCAN
1x 18 LinFlex
4 x I2C
3 x analog
comparator (CMP)
4 x DSPI
6 x SPI
3 x SAI
3 x FCD
3 x eMIOS + BCTU
3-core INTC
DMA and
2 x chmux
1 x CRC
Register
protection
LPU_CTL
*All FlexCANs optionally
support CAN FD
Figure 1. MPC5748G block diagram
2 Family comparison
The following table provides a summary of the different members of the MPC5748G
family and their proposed features. This information is intended to provide an
understanding of the range of functionality offered by this family. For full details of all of
the family derivatives please contact your marketing representative.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
4
NXP Semiconductors
Family comparison
NOTE
All optional features (Flash memory, RAM, Peripherals) start
with lowest peripheral number (for example: STM_0) or
memory address and end at the highest available peripheral
number or memory address (for example: MPC574xC have 2
STM, ending with STM_1).
Table 1. MPC5748G Family Comparison1
Feature
MPC5747C
MPC5748C
MPC5746G
MPC5747G
MPC5748G
CPUs
e200z4
e200z4
e200z4
e200z4
e200z4
e200z2
e200z2
e200z4
e200z4
e200z4
e200z2
e200z2
e200z2
e200z4
e200z4
e200z4
e200z4
e200z4
e200z4
FPU
e200z4
Maximum
Operating
Frequency2
Flash memory
EEPROM support
RAM
e200z4
160MHz (z4)
160MHz (z4)
160MHz (z4)
160MHz (z4)
160MHz (z4)
80MHz (z2)
80MHz (z2)
160MHz (z4)
160MHz (z4)
160MHz (z4)
80MHz (z2)
80MHz (z2)
80MHz (z2)
4 MB
6 MB
4 MB
6 MB
3 MB
32 KB to 128 KB emulated
32 KB to 192 KB emulated
512 KB
768 KB
ECC
End to End
SMPU
SMPU_0: 12 entry, SMPU_1: 12 entry
SMPU_0: 16 entry, SMPU_1: 16 entry
DMA
32 channels
10-bit ADC
48 Standard channels
32 External channels
12-bit ADC
16 Precision channels
16 Standard channels
32 External channels
AnalogComparator
3
BCTU
1
SWT
2
STM
2
43
3
PIT-RTI
16 channels PIT
1 channels RTI
RTC/API
Total Timer
Yes
I/O4
96 channels
16-bits
LINFlexD
1 M/S, 15 M
1 M/S, 17 M
FlexCAN
8 with optional CAN FD support
DSPI/SPI
4 x DSPI
6 x SPI
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
5
Family comparison
Table 1. MPC5748G Family Comparison1 (continued)
Feature
MPC5747C
MPC5748C
MPC5746G
I2C
4
SAI/I2S
3
FXOSC
8 - 40 MHz
SXOSC
32 KHz
FIRC
16 MHz
SIRC
128 KHz
FMPLL
Yes
LPU
Yes
FlexRay 2.1 (dual
channel)
Yes, 128 MB
MPC5747G
MLB150
0
1
USB 2.0 SPH
0
1
USB 2.0 OTG
0
1
SDHC
1
Ethernet (RMII, MII
+ 1588, Muti queue
AVB support)
Up to 2
3 Port L2 Ethernet
Switch
Optional
CRC
1
MEMU
2
STCU
1
HSM-v2 (security)
Optional
Censorship
Yes
FCCU
1
Safety level
Specific functions ASIL-B certifiable
User MBIST
Yes
User LBIST
Yes
I/O Retention in
Standby
Yes
GPI
17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA)
GPIO
129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA)
Debug
JTAGC,
MPC5748G
cJTAG
Nexus
Z4 N3+
Z2 N3+
Packages
176 LQFP-EP
256 BGA, 324 BGA
1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package
dependent.
2. Based on 125°C ambient operating temperature and subject to full device characterisation.
3. Additional SWT included when HSM option selected
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
6
NXP Semiconductors
Family comparison
4. Refer device datasheet and reference manual for information on to timer channel configuration and functions.
Table 2. MPC5748G Family Comparison - NVM Memory Map 1
Start Address
End Address
Flash block
RWW
MPC5746
MPC5747
MPC5748
0x01000000
0x0103FFFF
256 KB code
Flash block 0
6
available
available
available
0x01040000
0x0107FFFF
256 KB code
Flash block 1
6
available
available
available
0x01080000
0x010BFFFF
256 KB code
Flash block 2
6
available
available
available
0x010C0000
0x010FFFFF
256 KB code
Flash block3
6
available
available
available
0x01100000
0x0113FFFF
256 KB code
Flash block 4
6
available
available
available
0x01140000
0x0117FFFF
256 KB code
Flash block 5
6
available
available
available
0x01180000
0x011BFFFF
256 KB code
Flash block 6
6
available
available
available
0x011C0000
0x011FFFFF
256 KB code
Flash block 7
6
available
available
available
0x01200000
0x0123FFFF
256 KB code
Flash block 8
7
available
available
available
0x01240000
0x0127FFFF
256 KB code
Flash block 9
7
available
available
available
0x01280000
0x012BFFFF
256 KB code
Flash block 10
7
not available
available
available
0x012C0000
0x012FFFFF
256 KB code
flash block 11
7
not available
available
available
0x01300000
0x0133FFFF
256 KB code
flash block 12
7
not available
available
available
0x01340000
0x0137FFFF
256 KB code
flash block 13
7
not available
available
available
0x01380000
0x013BFFFF
256 KB code
flash block 14
7
not available
not available
available
0x013C0000
0x013FFFFF
256 KB code
flash block 15
7
not available
not available
available
0x01400000
0x0143FFFF
256 KB code
flash block 16
8
not available
not available
available
0x01440000
0x0147FFFF
256 KB code
flash block 17
8
not available
not available
available
0x01480000
0x014BFFFF
256 KB code
flash block 18
8
not available
not available
available
0x14C0000
0x014FFFFF
256 KB code
flash block 19
9
not available
not available
available
0x01500000
0x0153FFFF
256 KB code
flash block 20
9
not available
not available
available
0x01540000
0x0157FFFF
256 KB code
flash block 21
9
not available
not available
available
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
7
Family comparison
Table 3. MPC5748G Family Comparison - NVM Memory Map 2
Start Address
End Address
Flash block
RWW
MPC5747C
MPC5746G
MPC5748C
MPC5747G
MPC5748G
0x00F90000
0x00F93FFF
16 KB data Flash
2
available
available
0x00F94000
0x00F97FFF
16 KB data Flash
2
available
available
0x00F98000
0x00F9BFFF
16 KB data Flash
2
available
available
0x00F9C000
0x00F9FFFF
16 KB data Flash
2
available
available
0x00FA0000
0x00FA3FFF
16 KB data Flash
3
available
available
0x00FA4000
0x00FA7FFF
16 KB data Flash
3
available
available
0x00FA8000
0x00FABFFF
16 KB data Flash
3
available
available
0x00FAC000
0x00FAFFFF
16 KB data Flash
3
available
available
0x00FB0000
0x00FB7FFF
32 KB data Flash
2
not available
available
0x00FB8000
0x00FBFFFF
32 KB data flash
3
not available
available
0x00FC0000
0x00FC7FFF
32 KB data flash
0
available
available
0x00FC8000
0x00FCFFFF
32 KB data flash
0
available
available
0x00FD0000
0x00FD7FFF
32 KB data flash
1
available
available
0x00FD8000
0x00FDFFFF
32 KB data flash
1
available
available
0x00FE0000
0x00FEFFFF
64 KB data flash
0
available
available
0x00FF0000
0x00FFFFFF
64 KB data flash
1
available
available
Table 4. MPC5748G Family Comparison - RAM Memory Map
Start Address
End Address
Allocated size [KB]
MPC5747C
MPC5748C
MPC5746G
MPC5747G
MPC5748G
0x40000000
0x40001FFF
8
available
available
0x40002000
0x4000FFFF
56
available
available
0x40010000
0x4001FFFF
64
available
available
0x40020000
0x4003FFFF
128
available
available
0x40040000
0x4007FFFF
256
available
available
0x40080000
0x400BFFFF
256
not available
available
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
8
NXP Semiconductors
Ordering parts
3 Ordering parts
3.1 Determining valid orderable parts
To determine the orderable part numbers for this device, go to www.nxp.com and
perform a part number search for the following device number: MPC5748G .
3.2 Ordering Information
P
Example Code
PC
57
4
8
G
S K0
M
MJ
6
R
Qualification Status
Power Architecture
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional fields
Fab and mask indicator
Temperature spec.
Package Code
CPU Frequency
R = Tape & Reel (blank if Tray)
Qualification Status
P = Engineering samples
S = Automotive qualified
Product Version
C = Body Control Feature Set
G = Gateway Feature Set
PC = Power Architecture
Optional fields
Blank = Feature not available
S = HSM (Security Module)
F = CAN FD
B = Both HSM and CAN FD
Automotive Platform
57 = Power Architecture in 55nm
Core Version
4 = e200z4 Core Version (highest
core version in the case of multiple
cores)
Flash Memory Size
6 = 3 MB
7 = 4 MB
8 = 6 MB
T = HSM and 2nd Ethernet
G = CAN FD and 2nd Ethernet
H = HSM, CAN FD, and 2nd Eternet
Fab and mask version indicator
K=TSMC Fab
#=Version of maskset
0=0N65H
1=1N81M
0A=0N78S
Package Code
KU = 176 LQFP EP
MJ = 256 MAPBGA
MN = 324 MAPBGA
CPU Frequency
2 = Each z4 operates up to 120
MHz
6 = Each z4 operates up to 160
MHz
Shipping Method
R = Tape and reel
Blank = Tray
Temperature spec.
C = -40.C to +85.C Ta
V = -40.C to +105.C Ta
M = -40.C to +125.C Ta
,
Note: Not all part number combinations are available as production
product
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
9
General
4 General
4.1 Absolute maximum ratings
NOTE
Functional operating conditions appear in the DC electrical
characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed. See footnotes in Table 5 for specific conditions
Stress beyond the listed maximum values may affect device
reliability or cause permanent damage to the device.
Table 5. Absolute maximum ratings
Conditions1
Min
Max
Unit
3.3 V - 5. 5V input/output supply voltage
—
–0.3
6.0
V
3.3 V flash supply voltage (when supplying
from an external source in bypass mode)
—
–0.3
3.63
V
Decoupling pin for low power regulators6
—
–0.3
1.32
V
3.3 V / 5.0 V ADC1 high reference voltage
—
–0.3
6
V
3.3 V to 5.5V ADC supply voltage
—
–0.3
6.0
V
3.3V to 5.5V ADC supply ground
—
–0.1
0.1
V
Core logic supply voltage
—
–0.3
1.32
V
VINA
Voltage on analog pin with respect to
ground (VSS_HV)
—
–0.3
Min (VDD_HV_x,
VDD_HV_ADCx,
VDD_ADCx_REF)
+0.3
V
VIN
Voltage on any digital pin with respect to
ground (VSS_HV)
Relative to
VDD_HV_A,
VDD_HV_B,
VDD_HV_C
–0.3
VDD_HV_x + 0.3
V
Always
–5
5
mA
Symbol
Parameter
VDD_HV_A, VDD_HV_B,
VDD_HV_C2
VDD_HV_FLA3, 4
VDD_LP_DEC5
7
VDD_HV_ADC1_REF
VDD_HV_ADC0
VDD_HV_ADC1
VSS_HV_ADC0
VSS_HV_ADC1
VDD_LV8, 9, 10, 11
IINJPAD
Injected input current on any pin during
overload condition
IINJSUM
Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
Tramp
Supply ramp rate
—
0.5 V / min
100V/ms
—
TA12
Ambient temperature
—
-40
125
°C
TSTG
Storage temperature
—
–55
165
°C
1. All voltages are referred to VSS_HV unless otherwise specified
2. VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
10
NXP Semiconductors
General
3.
4.
5.
6.
7.
8.
VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V
VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V
This pin should be decoupled with low ESR 1 µF capacitor.
Not available for input voltage, only for decoupling internal regulators
10-bit ADC does not have dedicated reference and its reference is double bonded to 10-bit ADC supply(VDD_HV_ADC0).
Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C, remaining time as defined in footnotes 10
and 11.
9. Allowed 1.38 – 1.45 V– for 10 hours cumulative time at maximum TJ = 150 °C, remaining time as defined in footnote 11.
10. 1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at
maximum TJ = 150 °C.
11. If HVD on core supply (VHVD_LV_x) is enabled, it will generate a reset when supply goes above threshold.
12. TJ=150°C. Assumes TA=125°C
• Assumes maximum θJA. SeeThermal attributes
4.2 Recommended operating conditions
The following table describes the operating conditions for the device, and for which all
specifications in the data sheet are valid, except where explicitly noted. The device
operating conditions must not be exceeded in order to guarantee proper operation and
reliability. The ranges in this table are design targets and actual data may vary in the
given range.
NOTE
• For normal device operations, all supplies must be within
operating range corresponding to the range mentioned in
following tables. This is required even if some of the
features are not used.
• If VDD_HV_A is in 5.0V range, VDD_HV_FLA should be
externally supplied using a 3.3V source. If VDD_HV_A is
in 3.3V range, VDD_HV_FLA should be shorted to
VDD_HV_A.
• VDD_HV_A, VDD_HV_B and VDD_HV_C are all
independent supplies and can each be set to 3.3V or 5V.
The following tables: 'Recommended operating conditions
(VDD_HV_x = 3.3 V)' and table 'Recommended operating
conditions (VDD_HV_x = 5 V)' specify their ranges when
configured in 3.3V or 5V respectively.
Table 6. Recommended operating conditions (VDD_HV_x = 3.3 V)
Symbol
VDD_HV_A
Conditions1
Min2
Max
Unit
HV IO supply voltage
—
3.15
3.6
V
HV flash supply voltage
—
3.15
3.6
V
Parameter
VDD_HV_B
VDD_HV_C
VDD_HV_FLA3
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
11
General
Table 6. Recommended operating conditions (VDD_HV_x = 3.3 V) (continued)
Symbol
Conditions1
Min2
Max
Unit
HV ADC1 high reference voltage
—
3.0
5.5
V
HV ADC supply voltage
—
max(VDD_H
V_A,VDD_H
V_B,VDD_H
V_C) - 0.05
3.6
V
HV ADC supply ground
—
-0.1
0.1
V
Core supply voltage
—
1.2
1.32
V
Analog Comparator DAC reference voltage
—
3.15
3.6
V
Injected input current on any pin during
overload condition
—
-3.0
3.0
mA
Parameter
VDD_HV_ADC1_REF
VDD_HV_ADC0
VDD_HV_ADC1
VSS_HV_ADC0
VSS_HV_ADC1
VDD_LV4
VIN1_CMP_REF5, 6
IINJPAD
TA
Ambient temperature under bias
fCPU ≤ 160
MHz
–40
125
°C
TJ
Junction temperature under bias
—
–40
150
°C
1. All voltages are referred to VSS_HV unless otherwise specified
2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the
point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.
3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V
4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be
left floating.
5. VIN1_CMP_REF ≤ VDD_HV_A
6. This supply is shorted VDD_HV_A on lower packages.
NOTE
If VDD_HV_A is in 5V range, it is necessary to use internal
Flash supply 3.3V regulator. VDD_HV_FLA should not be
supplied externally and should only have decoupling capacitor.
Table 7. Recommended operating conditions (VDD_HV_x = 5 V)
Symbol
VDD_HV_A
Conditions 1
Min2
Max
Unit
HV IO supply voltage
—
4.5
5.5
V
HV flash supply voltage
—
3.15
3.6
V
HV ADC1 high reference voltage
—
3.15
5.5
V
HV ADC supply voltage
—
max(VDD_H
V_A,VDD_H
V_B,VDD_H
V_C) - 0.05
5.5
V
HV ADC supply ground
—
-0.1
0.1
V
Core supply voltage
—
1.2
1.32
V
Parameter
VDD_HV_B
VDD_HV_C
VDD_HV_FLA3
VDD_HV_ADC1_REF
VDD_HV_ADC0
VDD_HV_ADC1
VSS_HV_ADC0
VSS_HV_ADC1
VDD_LV4
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
12
NXP Semiconductors
General
Table 7. Recommended operating conditions (VDD_HV_x = 5 V) (continued)
Symbol
VIN1_CMP_REF5
IINJPAD
Conditions 1
Min2
Max
Unit
Analog Comparator DAC reference voltage
—
3.15
5.5
V
Injected input current on any pin during
overload condition
—
-3.0
3.0
mA
Parameter
TA
Ambient temperature under bias
fCPU ≤ 160
MHz
–40
125
°C
TJ
Junction temperature under bias
—
–40
150
°C
1. All voltages are referred to VSS_HV unless otherwise specified
2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the
point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.
3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with Cflash_reg.
4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be
left floating
5. This supply is shorted VDD_HV_A on lower packages.
4.3 Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
• Choice of generating supply voltage for the core area.
• Control of external NPN ballast transistor
• Connecting an external 1.25 V (nominal) supply directly without the NPN ballast
• Internal generation of the 3.3 V flash supply when device connected in 5V
applications
• External bypass of the 3.3 V flash regulator when device connected in 3.3V
applications
• Low voltage detector - low threshold (LVD_IO_A_LO) for VDD_HV_IO_A supply
• Low voltage detector - high threshold (LVD_IO_A_Hi) for VDD_HV_IO_A supply
• Various low voltage detectors (LVD_LV_x)
• High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV)
• Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV)
• Power on Reset (POR_HV) for 3.3 V to 5 V supply (VDD_HV_A)
The following bipolar transistors1 are supported, depending on the device performance
requirements. As a minimum the following must be considered when determining the
most appropriate solution to maintain the device under its maximum power dissipation
capability: current, ambient temperature, mounting pad area, duty cycle and frequency for
Idd, collector voltage, etc
1.
BCP56, MCP68 and MJD31are guaranteed ballasts.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
13
General
LPPREG
VDD_LP_DEC
VDD_HV_BALLAST
ULPPREG
CLP/ULPREG
VRC_CTRL
V SS_HV
FPREG
CBE_FPREG
Flash
voltage
regulator
V DD_LV
VDD_HV_FLA
CFLASH_REG
CFP_REG
VSS_HV
VSS_HV
DEVICE
Figure 2. Voltage regulator capacitance connection
Table 8. Voltage regulator electrical specifications
Symbol
Cfp_reg
1
Clp/ulp_reg
Cbe_fpreg3
Cflash_reg4
Parameter
Conditions
Min
Typ
Max
Unit
1.32
2.22
3
µF
—
0.03
Ohm
1
1.4
µF
—
0.1
Ohm
External decoupling / stability
capacitor
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
Combined ESR of external
capacitor
—
External decoupling / stability
capacitor for internal low power
regulators
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
Combined ESR of external
capacitor
—
Capacitor in parallel to baseemitter
BCP68 and BCP56
3.3
MJD31
4.7
External decoupling / stability
capacitor for internal Flash
regulators
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
Combined ESR of external
capacitor
—
0.001
0.8
0.001
1.32
0.001
nF
2.2
3
µF
—
0.03
Ohm
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
14
NXP Semiconductors
General
Table 8. Voltage regulator electrical specifications (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CHV_VDD_A
VDD_HV_A supply capacitor
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1
—
—
µF
CHV_VDD_B
VDD_HV_B supply capacitor5
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1
—
—
µF
CHV_VDD_C
VDD_HV_C supply capacitor5
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1
—
—
µF
CHV_ADC0
HV ADC supply decoupling
capacitances
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
1
—
—
µF
HV ADC SAR reference supply
decoupling capacitances
Min, max values shall be granted
with respect to tolerance, voltage,
temperature, and aging
variations.
0.47
—
—
µF
VDD_HV_BALL FPREG Ballast collector supply
7
voltage
AST
When collector of NPN ballast is
directly supplied by an on board
supply source (not shared with
VDD_HV_A supply pin) without
any series resistance, that is,
RC_BALLAST less than 0.01 Ohm.
2.25
—
5.5
V
RC_BALLAST Series resistor on collector of
FPREG ballast
When VDD_HV_BALLAST is
shorted to VDD_HV_A on the
board
—
—
0.1
Ohm
Start-up time after main supply
stabilization
Cfp_reg = 3 μF
—
74
—
μs
Load current transient
Iload from 15% to 55%
CHV_ADC1
CHV_ADR6
tSU
tramp
1.0
µs
Cfp_reg = 3 µF
1. Split capacitance on each pair VDD_LV pin should sum up to a total value of Cfp_reg
2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and
maximum values.
3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is
recommended. The tolerance +/-20% is acceptable.
4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing
inductance should be less than 1nH.
5.
1. For VDD_HV_A, VDD_HV_B, and VDD_HV_C, 1µf on each side of the chip
a. 0.1 µf close to each VDD/VSS pin pair.
b. 10 µf near for each power supply source
c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation
mode, this amount of capacitance will need to be subtracted from the total capacitance required by the
regulator for e.g., as specified by CFP_REG parameter.
2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this
amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as
specified by CFP_REG parameter
6. Only applicable to ADC1
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
15
General
7. In external ballast configuration the following must be ensured during power-up and power-down (Note: If VDD_HV_BALLAST
is supplied from the same source as VDD_HV_A this condition is implicitly met):
• During power-up, VDD_HV_BALLAST must have met the min spec of 2.25V before VDD_HV_A reaches the
POR_HV_RISE min of 2.75V.
• During power-down, VDD_HV_BALLAST must not drop below the min spec of 2.25V until VDD_HV_A is below
POR_HV_FALL min of 2.7V.
NOTE
For a typical configuration using an external ballast transistor
with separate supply for VDD_HV_A and the ballast collector,
a bulk storage capacitor (as defined in Table 8) is required on
VDD_HV_A close to the device pins to ensure a stable supply
voltage.
Extra care must be taken if the VDD_HV_A supply is also
being used to power the external ballast transistor or the device
is running in internal regulation mode. In these modes, the
inrush current on device Power Up or on exit from Low Power
Modes is significant and may cause the VDD_HV_A voltage to
drop resulting in an LVD reset event. To avoid this, the board
layout should be optimized to reduce common trace resistance
or additional capacitance at the ballast transistor collector (or
VDD_HV_A pins in the case of internal regulation mode) is
required. NXP recommends that customers simulate the
external voltage supply circuitry.
In all circumstances, the voltage on VDD_HV_A must be
maintained within the specified operating range (see
Recommended operating conditions) to prevent LVD events.
4.4 Voltage monitor electrical characteristics
Table 9. Voltage monitor electrical characteristics
Symbol
Parameter
State
Conditions
Configuration
Powe Mas
r Up 1
k
Opt
VPOR_LV
LV supply
Fall
power on
reset detector
Rise
Untrimmed
Yes
No
Threshold
Reset Type
POR
Min
Typ
Unit
Max
V
0.930
0.979
1.028
V
Trimmed
0.959
0.979
0.999
V
Untrimmed
0.980
1.029
1.078
V
Trimmed
1.009
1.029
1.049
V
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
16
NXP Semiconductors
General
Table 9. Voltage monitor electrical characteristics (continued)
Symbol
Parameter
State
Conditions
Configuration
Powe Mas
r Up 1
k
Opt
VHVD_LV_cold
VLVD_LV_PD2_hot
VLVD_LV_PD1_hot
VLVD_LV_PD0_hot
VPOR_HV
VLVD_IO_A_LO, 2
VLVD_IO_A_HI2
VLVD_LV_PD2_cold
LV supply high Fall
voltage
monitoring,
Rise
detecting at
the device pin
Untrimmed
Yes
Reset Type
Functional
Min
V
Disabled at Start
Untrimmed
Disabled at Start
Trimmed
1.345
1.365
1.395
V
LV supply low Fall
voltage
monitoring,
Rise
detecting in
the PD1 core
(hot) area
Untrimmed
LV supply low Fall
voltage
monitoring,
Rise
detecting in
the PD0 core
(hot) area
Untrimmed
HV supply
Fall
power on
Rise
reset detector
Untrimmed
HV IO_A
supply low
voltage
monitoring low range
Fall
Untrimmed
HV IO_A
supply low
voltage
monitoring high range
Fall
Yes
V
1.120
1.160
V
1.125
1.143
1.160
V
Untrimmed
1.100
1.140
1.180
V
Trimmed
1.145
1.163
1.180
V
1.080
1.120
1.160
V
Trimmed
1.114
1.137
1.160
V
Untrimmed
1.100
1.140
1.180
V
Trimmed
1.134
1.157
1.180
V
1.080
1.120
1.160
V
Trimmed
1.114
1.137
1.160
V
Untrimmed
1.100
1.140
1.180
V
Trimmed
1.134
1.157
1.180
V
2.700
2.850
3.000
V
2.750
2.900
3.050
V
2.750
2.923
3.095
V
Trimmed
2.978
3.039
3.100
V
Untrimmed
2.780
2.953
3.125
V
Trimmed
3.008
3.069
3.130
V
Yes
Yes
No
No
No
POR
1.375
1.080
Yes
No
1.345
Trimmed
POR
POR
POR
Untrimmed
Trimmed
Yes
No
No
Yes
POR
Functional
Disabled at Start
4.060
LV supply low Fall
voltage
monitoring,
Rise
detecting at
the device pin
Max
1.325
Untrimmed
Rise
Typ
Unit
Trimmed
LV supply low Fall
voltage
monitoring,
Rise
detecting in
the PD2 core
(hot) area
Rise
No
Threshold
Trimmed
4.240
V
Disabled at Start
4.115
Untrimmed
4.151
No
Yes
Functional
4.201
4.3
V
Disabled at Start
Trimmed
1.14
1.158
Untrimmed
Disabled at Start
Trimmed
1.16
1.178
1.175
1.195
V
V
1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until the
minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active
will always generate a POR reset.
2. There is no voltage monitoring on the VDD_HV_ADC0, VDD_HV_ADC1, VDD_HV_B and VDD_HV_C I/O segments. For applications
requiring monitoring of these segments, either connect these to VDD_HV_A at the PCB level or monitor externally.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
17
General
4.5 Supply current characteristics
Current consumption data is given in the following table. These specifications are design
targets and are subject to change per device characterization.
NOTE
The ballast must be chosen in accordance with the ballast
transistor supplier operating conditions and recommendations.
Table 10. Current consumption characteristics
Symbol
IDD_FULL
2, 3
Conditions1
Parameter
RUN Full Mode
LV supply + HV supply + HV Flash supply +
Operating current
2 x HV ADC supplies
Min
Typ
Max
Unit
—
219
292
mA
Ta = 85°C
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 160MHz
IDD_GWY
5, 6
RUN Gateway
Mode Operating
current
Ta = 105°C
—
230
328
mA
Ta = 125 °C
—
249
400
mA
260
mA
LV supply + HV supply + HV Flash supply + 2 x HV
ADC supplies
—
183
Ta = 85°C
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 160MHz
Ta = 105°C
Ta =
IDD_BODY_1
7, 8
RUN Body Mode
Profile Operating
current
125°C4
LV supply + HV supply + HV Flash supply + 2 x HV
ADC supplies
—
196
294
mA
—
215
348
mA
223
mA
—
149
Ta = 85 °C
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 120MHz
IDD_BODY_29, 10 RUN Body Mode
Profile Operating
current
Ta = 105 °C
—
158
270
mA
Ta = 125°C 4
—
175
310
mA
174
mA
LV supply + HV supply + HV Flash supply + 2 x HV
ADC supplies
—
105
Ta = 85 °C
VDD_LV = 1.25 V
VDD_HV_A = 5.5V
SYS_CLK = 80MHz
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
18
NXP Semiconductors
General
Table 10. Current consumption characteristics (continued)
Symbol
Conditions1
Parameter
IDD_STOP
Min
Typ
Max
Unit
Ta = 105 °C
—
114
206
mA
Ta = 125 °C 4
—
131
277
mA
—
mA
STOP mode
Ta = 25 °C
Operating current
VDD_LV = 1.25 V
Ta = 85 °C
—
—
11
19.8
105
29
145
45
160
VDD_LV = 1.25 V
Ta = 105 °C
VDD_LV = 1.25 V
Ta = 125 °C 4
—
VDD_LV = 1.25 V
IDD_HV_ADC_REF
11, 12
ADC REF
Ta = 25 °C
Operating current
2 ADCs operating at 80 MHz
—
200
400
µA
VDD_HV_ADC_REF = 3.6 V
Ta = 125 °C 4
—
200
400
2 ADCs operating at 80 MHz
VDD_HV_ADC_REF = 5.5 V
IDD_HV_ADCx12
ADC HV
Ta = 25 °C
Operating current
ADC operating at 80 MHz
—
1
2
1.2
2
mA
VDD_HV_ADC = 3.6 V
Ta = 125 °C 4
—
ADC operating at 80 MHz
VDD_HV_ADC = 5.5 V
IDD_HV_FLASH
Flash Operating
current during
read access
Ta = 125 °C 4
—
40
45
mA
3.3 V supplies
x MHz frequency
1. The content of the Conditions column identifies the components that draw the specific current.
2. ALL Modules enabled at maximum frequency: 2 x e200Z4 @160 MHz, e200Z2 at 80 MHz, Platform @160MHz, DMA
(SRAM to SRAM), all SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM
reading from flash at regular intervals (500 pll clock cycles), ENET0 transmitting, MLB transmitting, FlexRay transmitting,
USB-SPH transmitting (USB-OTG only clocked), 2 x I2C transmitting (rest clocked), 1 x SAI transmitting (rest clocked),
ADC0 converting using BCTU triggers triggered through PIT (other ADC clocked), RTC running, 3 x STM running, 2 x
DSPI transmitting (rest clocked), 2 x SPI transmitting (rest clocked), 4 x CAN state machines working(rest clocked), 9 x
LINFlexD transmitting (rest clocked), 1 x eMIOS clocked (used OPWFMB mode) (Others clock gated), SDHC,3 x CMP
only clocked, FIRC, SIRC, FXOSC, SXOSC, PLL running. All others modules clock gated if not specifically mentioned. I/O
supply current excluded.
3. Recommended Transistors:MJD31 @ 85°C, 105°C and 125°C.
4. Tj=150°C. Assumes Ta=125°C
• Assumes maximum θJA. SeeThermal attributes
5. Enabled Modules in Gateway mode: 2 x e200Z4 @160 MHz (Instruction and Data cache enabled), Platform @160MHz,
e200Z2 at 80 MHz(Instruction cache enabled), all SRAMs accessed in parallel, Flash access(prefetch is disabled while
buffers are enabled), HSM reading from flash at regular intervals(500 pll clock cycles), ENET0 transmitting, MLB
transmitting, FlexRay transmitting, USB-SPH Transmitting, USB-OTG clocked, 2 x I2C transmitting, (2 x I2C clock gated),
1 x SAI transmitting (2 x SAI clock gated), ADC0 converting in continuous mode (ADC1 clock gated), PIT clocked, RTC
clocked, 3 x STM clocked, 2 x DSPI transmitting(Other DSPS clock gated), 2 x SPI transmitting(Other SPIs clock gated), 4
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
19
General
x FlexCAN state machines clocked(other FLEXCAN clock gated), 4 x LINFlexD transmitting (Other clock gated), 1x eMIOS
clocked(used OPWFMB mode) (Others clock gated), FIRC, SIRC, FXOSC, SXOSC, PLL running, BCTU, DMAMUX,
ACMP clock gated. All others modules clock gated if not specifically mentioned. I/O supply current excluded
6. Recommended Transistors:MJD31@85°C, 105°C and 125°C.
7. Enabled Modules in Body mode enabled at maximum frequency: 2 x e200Z4 @120Mhz(Instruction and Data cache
enabled),Platform@120MHz, SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled),
HSM reading from flash at regular intervals(500 pll clock cycles), DMA (SRAM to SRAM), ADC0 converting using BCTU
triggers which are triggered through PIT(ADC1 clocked), RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(others
DSPIs clocked), 2 x SPI transmitting(others clocked), 4 x FlexCAN state machines working(others clocked), 9xLINFlexD
transmitting (others clocked), 1xeMIOS operational (used OPWFMB mode) (others clocked), FIRC, SIRC, FXOSC,
SXOSC, PLL running, MEMU, FCCU, SIUL, SDHC,CMP clocked, e200Z2, ENET, MLB, SAI, I2C, FlexRay, USB clock
gated. All others modules clock gated if not specifically mentioned I/O supply current excluded
8. Recommended Transistors:BCP56, BCP68 or MJD31@85°C, BCP56, BCP68 or MJD31@105°C and MJD31@125°C.
9. Enabled Modules in Body mode enabled at maximum frequency:2 x e200Z4 @80Mhz(Instruction and Data cache
enabled),Platform@80MHz, SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled),
HSM reading from flash at regular intervals(500 pll clock cycles), DMA (SRAM to SRAM), ADC0 converting using BCTU
triggers which are triggered through PIT(ADC1 clocked), RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(others
DSPIs clocked), 2 x SPI transmitting(others clocked), 4 x FlexCAN state machines working(others clocked), 9xLINFlexD
transmitting (others clocked), 1xeMIOS operational (used OPWFMB mode) (others clocked), FIRC, SIRC, FXOSC,
SXOSC, PLL running, MEMU, FCCU, SIUL, SDHC,CMP clocked, e200Z2, ENET, MLB, SAI, I2C, FlexRay, USB clock
gated. All others modules clock gated if not specifically mentioned I/O supply current excluded
10. Recommended Transistors:BCP56, BCP68 or MJD31@85°C, 105°C and 125°C
11. Internal structures hold the input voltage less than VDD_HV_ADC_REF + 1.0 V on all pads powered by VDDA supplies, if the
maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
12. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max.
Table 11. Low Power Unit (LPU) Current consumption characteristics
Symbol
LPU_RUN
Conditions1
Parameter
with 256K RAM,
Ta = 25 °C
but only one RAM
SYS_CLK = 16MHz
being accessed
ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF
Min
Typ
—
8.9
Ta = 25 °C
Max
Unit
mA
10.2
SYS_CLK = 16MHz
ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON
Ta = 85 °C
Ta = 105 °C
Ta = 125 °C
,2
—
12.5
22
—
14.5
24
—
16
26
SYS_CLK = 16MHz
ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON
LPU_STOP
with 256K RAM
Ta = 25 °C
—
0.535
mA
Ta = 85 °C
—
0.72
6
Ta = 105 °C
—
1
8
Ta = 125 °C 2
—
1.6
10.6
1. The content of the Conditions column identifies the components that draw the specific current.
2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal
attributes
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
20
NXP Semiconductors
General
Table 12. STANDBY Current consumption characteristics
Symbol
Parameter
Conditions1
Min
Typ
Max
Unit
STANDBY0
STANDBY with
8K RAM
Ta = 25 °C
—
71
—
µA
Ta = 85 °C
—
175
800
Ta = 105 °C
—
338
1725
Ta = 125 °C
—
750
2775
Ta = 25 °C
—
72
—
Ta = 85 °C
—
176
815
Ta = 105 °C
—
350
1775
Ta = 125 °C
—
825
3000
Ta = 25 °C
—
75
—
Ta = 85 °C
—
182
830
Ta = 105 °C
—
366
1825
Ta = 125 °C
—
900
3250
Ta = 25 °C
—
80
—
Ta = 85 °C
—
197
860
Ta = 105 °C
—
400
1875
Ta = 125 °C
—
975
3500
Ta = 25 °C
—
500
—
STANDBY1
STANDBY with
64K RAM
STANDBY2
STANDBY with
128K RAM
STANDBY3
STANDBY with
256K RAM
STANDBY3
FIRC ON
µA
µA
µA
µA
1. The content of the Conditions column identifies the components that draw the specific current.
NOTE
For the Precision channel Analog inputs, SIUL2_MSCRn[PUS]
must be configured to 0 before entering STANDBY. An
increase in current would be observed when
SIUL2_MSCRn[PUS] is configured to be 1, irrespective of the
state of IBE or PUE. The current numbers would increase
irrespective of whether the pad is pulled low/high externally.
4.6 Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This
test conforms to the AEC-Q100-002/-003/-011 standard.
NOTE
A device will be defined as a failure if after exposure to ESD
pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing
shall be performed per applicable device specification at room
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
21
I/O parameters
temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 13. ESD ratings
Symbol
VESD(HBM)
VESD(CDM)
Conditions1
Parameter
Electrostatic discharge
TA = 25 °C
(Human Body Model)
conforming to AECQ100-002
Electrostatic discharge
TA = 25 °C
(Charged Device Model)
conforming to AECQ100-011
Class
Max value2
Unit
H1C
2000
V
C3A
500
V
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Data based on characterization results, not tested in production.
4.7 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
5 I/O parameters
5.1 AC specifications @ 3.3 V Range
Table 14. Functional Pad AC Specifications @ 3.3 V Range
Symbol
Prop. Delay (ns)1
Rise/Fall Edge (ns)
L>H/H>L
Min
Max
pad_sr_hv
(output)
pad_i_hv/
pad_sr_hv
Min
6/6
Drive Load
(pF)
Max
MSB,LSB
1.9/1.5
25
2.5/2.5
8.25/7.5
0.8/0.6
3.25/3
50
6.4/5
19.5/19.5
3.5/2.5
12/12
200
2.2/2.5
8/8
0.55/0.5
3.9/3.5
25
0.090
1.1
0.035
1.1
asymmetry2
2.9/3.5
12.5/11
1/1
7/6
50
11/8
35/31
7.7/5
25/21
200
8.3/9.6
45/45
4/3.5
25/25
50
13.5/15
65/65
6.3/6.2
30/30
200
13/13
75/75
6.8/6
40/40
50
21/22
100/100
11/11
51/51
200
0.5/0.5
0.5
2/2
SIUL2_MSCRn[SRC 1:0]
11
10
01
003
NA
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
22
NXP Semiconductors
I/O parameters
Table 14. Functional Pad AC Specifications @ 3.3 V Range
Prop. Delay (ns)1
Symbol
Rise/Fall Edge (ns)
L>H/H>L
Min
Max
Min
Drive Load
(pF)
SIUL2_MSCRn[SRC 1:0]
Max
MSB,LSB
(input)4
1. As measured from 50% of core side input to Voh/Vol of the output
2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF
load. Required for the Flexray spec.
3. Slew rate control modes
4. Input slope = 2ns
NOTE
The specification given above is based on simulation data into
an ideal lumped capacitor. Customer should use IBIS models
for their specific board/loading conditions to simulate the
expected signal integrity and edge rates of their system.
NOTE
The specification given above is measured between 20% / 80%.
5.2 DC electrical specifications @ 3.3V Range
Table 15. DC electrical specifications @ 3.3V Range
Symbol
VDD
VDD_HV_x
Parameter
Value
Unit
Min
Max
LV (core) Supply Voltage
1.08
1.32
V
I/O Supply Voltage
3.15
3.63
V
Vih (pad_i_hv)
pad_i_hv Input Buffer High Voltage
0.72*VDD_HV_
x
VDD_HV_x +
0.3
V
Vil (pad_i_hv)
pad_i_hv Input Buffer Low Voltage
VSS_LV - 0.3
0.45*VDD_HV_
x
V
Vhys (pad_i_hv)
pad_i_hv Input Buffer Hysteresis
0.11*VDD_HV_
x
Vih_hys
CMOS Input Buffer High Voltage (with hysteresis
enabled)
0.67*VDD_HV_
x
VDD_HV_x +
0.3
V
Vil_hys
CMOS Input Buffer Low Voltage (with hysteresis
enabled)
VSS_LV - 0.3
0.35*VDD_HV_
x
V
Vih
CMOS Input Buffer High Voltage (with hysteresis
disabled)
0.57 *
VDD_HV_x
VDD_HV_x +
0.3
V
Vil
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
VSS_LV - 0.3
0.4 *
VDD_HV_x
V
Vhys
CMOS Input Buffer Hysteresis
0.09 *
VDD_HV_x
V
V
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
23
I/O parameters
Table 15. DC electrical specifications @ 3.3V Range (continued)
Symbol
Parameter
Value
Min
Pull_IIH (pad_i_hv) Weak Pullup Current Low
Unit
Max
15
µA
Pull_IIH (pad_i_hv) Weak Pullup Current High
55
Pull_IIL (pad_i_hv) Weak Pulldown Current2 Low
Pull_IIL (pad_i_hv) Weak Pulldown
Pull_Ioh
28
Current4
Weak Pulldown
Iinact_d
Digital Pad Input Leakage Current (weak pull inactive)
Vol
µA
High
Current3
Pull_Iol
Voh
85
µA
15
50
µA
15
50
µA
-2.5
2.5
µA
Output High
Voltage5
0.8 *VDD_HV_x
—
V
Output Low
Voltage6
—
0.2 *VDD_HV_x
V
Output Low
Voltage7
Ioh8
0.1 *VDD_HV_x
Ioh_f
Full drive
18
70
mA
Iol_f
Full drive Iol8 (SIUL2_MSCRn[SRC 1:0]= 11)
21
120
mA
Ioh_h
Half drive Ioh8 (SIUL2_MSCRn[SRC 1:0]= 10)
9
35
mA
10.5
60
mA
Iol_h
1.
2.
3.
4.
5.
6.
7.
8.
Weak Pullup
Current1
µA
Half drive
Iol8
(SIUL2_MSCRn[SRC 1:0]= 11)
(SIUL2_MSCRn[SRC 1:0]= 10)
Measured when pad=0.69*VDD_HV_x
Measured when pad=0.49*VDD_HV_x
Measured when pad = 0 V
Measured when pad = VDD_HV_x
Measured when pad is sourcing 2 mA
Measured when pad is sinking 2 mA
Measured when pad is sinking 1.5 mA
Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.
5.3 AC specifications @ 5 V Range
Table 16. Functional Pad AC Specifications @ 5 V Range
Symbol
Prop. Delay (ns)1
Rise/Fall Edge (ns)
Drive Load (pF)
SIUL2_MSCRn[SRC 1:0]
L>H/H>L
Min
pad_sr_hv
(output)
Max
Min
Max
MSB,LSB
4.5/4.5
1.3/1.2
25
6/6
2.5/2
50
13/13
9/9
200
5.25/5.25
3/2
25
9/8
5/4
50
22/22
18/16
200
27/27
13/13
50
40/40
24/24
200
40/40
24/24
50
11
10
012
002
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
24
NXP Semiconductors
I/O parameters
Table 16. Functional Pad AC Specifications @ 5 V Range (continued)
Prop. Delay (ns)1
Symbol
Rise/Fall Edge (ns)
Drive Load (pF)
SIUL2_MSCRn[SRC 1:0]
L>H/H>L
Min
pad_i_hv/
pad_sr_hv
Max
Min
Max
MSB,LSB
65/65
40/40
200
1.5/1.5
0.5/0.5
0.5
NA
(input)
1. As measured from 50% of core side input to Voh/Vol of the output
2. Slew rate control modes
NOTE
The above specification is based on simulation data into an
ideal lumped capacitor. Customer should use IBIS models for
their specific board/loading conditions to simulate the expected
signal integrity and edge rates of their system.
NOTE
The above specification is measured between 20% / 80%.
5.4 DC electrical specifications @ 5 V Range
Table 17. DC electrical specifications @ 5 V Range
Symbol
VDD_LV
VDD_HV_x
Parameter
Value
Unit
Min
Max
LV (core) Supply Voltage
1.08
1.32
V
I/O Supply Voltage
4.5
5.5
V
Vih (pad_i_hv)
pad_i_hv Input Buffer High Voltage
0.7*VDD_HV_x
VDD_HV_x +
0.3
V
Vil (pad_i_hv)
pad_i_hv Input Buffer Low Voltage
VSS_LV- 0.3
0.45*VDD_HV_
x
V
Vhys (pad_i_hv)
pad_i_hv Input Buffer Hysteresis
0.09*VDD_HV_
x
V
Vih
CMOS Input Buffer High Voltage (with hysteresis
disabled)
0.55 *
VDD_HV_x
VDD_HV_x +
0.3
V
Vil
CMOS Input Buffer Low Voltage (with hysteresis
disabled)
VSS_LV - 0.3
0.4 *
VDD_HV_x
V
Vhys
Vih_hys
CMOS Input Buffer Hysteresis
0.09 *
VDD_HV_x
CMOS Input Buffer High Voltage (with hysteresis
enabled)
0.65*
VDD_HV_x
V
VDD_HV_x +
0.3
V
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
25
I/O parameters
Table 17. DC electrical specifications @ 5 V Range (continued)
Symbol
Vil_hys
Parameter
Value
CMOS Input Buffer Low Voltage (with hysteresis
enabled)
Min
Max
VSS_LV - 0.3
0.35*VDD_HV_
x
Pull_IIH (pad_i_hv) Weak Pullup Current Low
23
Pull_IIH (pad_i_hv) Weak Pullup Current High
Pull_IIL (pad_i_hv) Weak Pulldown
Current2
Low
Pull_IIL (pad_i_hv) Weak Pulldown
Current1
High
Pull_Ioh
Weak Pullup
Unit
µA
82
40
Current3
30
Current4
Pull_Iol
Weak Pulldown
Iinact_d
Digital Pad Input Leakage Current (weak pull inactive)
V
µA
µA
130
µA
80
µA
30
80
µA
-2.5
2.5
µA
Voh
Output High Voltage5
0.8 *
VDD_HV_x
—
V
Vol
Output Low Voltage6
—
0.2 *
VDD_HV_x
V
Output Low
Voltage7
0.1*VDD_HV_x
Ioh_f
Iol_f
1.
2.
3.
4.
5.
6.
7.
8.
Full drive
Ioh8 (SIUL2_MSCRn[SRC
Full drive
Iol8
1:0]= 11)
38
132
mA
(SIUL2_MSCRn[SRC 1:0]= 11)
48
220
mA
Ioh_h
Half drive Ioh8 (SIUL2_MSCRn[SRC 1:0]= 10)
19
66
mA
Iol_h
Half drive Iol8 (SIUL2_MSCRn[SRC 1:0]= 10)
24
110
mA
Measured when pad=0.69*VDD_HV_x
Measured when pad=0.49*VDD_HV_x
Measured when pad = 0 V
Measured when pad = VDD_HV_x
Measured when pad is sourcing 2 mA
Measured when pad is sinking 2 mA
Measured when pad is sinking 1.5 mA
Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.
5.5 Reset pad electrical characteristics
The device implements a dedicated bidirectional RESET pin.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
26
NXP Semiconductors
I/O parameters
AA
A
VDD_HV_IOx
A
VDDMIN
PORST
VIH
VIL
device reset forced by PORST
device start-up phase
Figure 3. Start-up reset requirements
VPORST
hw_rst
VDD_HV_IO
A
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WFRST
WNFRST
Figure 4. Noise filtering on reset signal
Table 18. Functional reset pad electrical specifications
Symbol
Parameter
Conditions
Value
Min
Typ
Max
Unit
VIH
Input high level TTL (Schmitt Trigger)
—
2.0
—
VDD_HV_A
+0.4
V
VIL
Input low level TTL (Schmitt Trigger)
—
–0.4
—
0.8
V
VHYS
Input hysteresis TTL (Schmitt Trigger)
—
300
—
—
mV
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
27
Peripheral operating requirements and behaviours
Table 18. Functional reset pad electrical specifications (continued)
Symbol
Parameter
Conditions
Value
Min
Unit
Typ
Max
VDD_POR
Minimum supply for strong pull-down
activation
—
—
—
1.2
V
IOL_R
Strong pull-down current 1
Device under power-on reset
0.2
—
—
mA
11
—
—
mA
VDD_HV_IO= V DD_POR
VOL = 0.35*VDD_HV_IO
Device under power-on reset
3.0 V < VDD_HV_IO < 5.5 V
VOL = 0.35*VDD_HV_IO
WFRST
RESET input filtered pulse
—
—
—
500
ns
WNFRST
RESET input not filtered pulse
—
2000
—
—
ns
|IWPU|
Weak pull-up current absolute value
RESET pin VIN = VDD
23
—
82
µA
1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET.
5.6 PORST electrical specifications
Table 19. PORST electrical specifications
Symbol
Parameter
Value
Min
WFPORST
PORST input filtered pulse
WNFPORST
PORST input not filtered pulse
VIH
Input high level
VIL
Input low level
—
Unit
Typ
Max
—
200
ns
1000
—
—
ns
—
0.65 x VDD_HV_A
—
V
—
0.35 x VDD_HV_A
—
V
6 Peripheral operating requirements and behaviours
6.1 Analog
6.1.1 ADC electrical specifications
The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter.
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
28
NXP Semiconductors
Analog
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
( 2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out
7
( 1)
6
5
(5)
4
(4)
3
(3)
2
1
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
1 LSB (ideal)
0
1
2
3
Offset Error OSE
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Figure 5. ADC characteristics and error definitions
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
NXP Semiconductors
29
Analog
6.1.1.1
Input equivalent circuit and ADC conversion characteristics
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD_IO
Source
Filter
RS
Current Limiter
RF
Sampling
RSW1
RAD
RL
CF
VA
Channel
Selection
CP1
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL
Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 6. Input equivalent circuit
NOTE
The ADC performance specifications are not guaranteed if two
ADCs simultaneously sample the same shared channel.
Table 20. ADC conversion characteristics (for 12-bit)
Min
Typ1
Max
Unit
15.2
80
80
MHz
—
—
1.00
MHz
80 MHz@ 100 ohm source
impedance
250
—
—
ns
Conversion time4
80 MHz
700
—
—
ns
Total Conversion time tsample +
tconv (for standard and extended
channels)
80 MHz
1.55
—
—
µs
1
—
—
Symbol
fCK
fs
Parameter
Conditions
ADC Clock frequency (depends on —
ADC configuration) (The duty cycle
depends on AD_CK2 frequency)
Sampling frequency
tsample
tconv
ttotal_conv
Sample
80 MHz
time3
Total Conversion time tsample +
tconv (for precision channels)
CS
ADC input sampling capacitance
—
—
3
5
pF
6
ADC input pin capacitance 1
—
—
—
5
pF
CP2
6
ADC input pin capacitance 2
—
—
—
0.8
pF
RSW16
Internal resistance of analog
source
VREF range = 4.5 to 5.5 V
—
—
0.3
kΩ
VREF range = 3.15 to 3.6 V
—
—
875
Ω
CP1
Table continues on the next page...
MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018
30
NXP Semiconductors
Analog
Table 20. ADC conversion characteristics (for 12-bit) (continued)
Symbol
Parameter
Conditions
Min
Typ1
Max
Unit
RAD6
Internal resistance of analog
source
—
—
—
825
Ω
INL
Integral non-linearity (precise
channel)
—
–2
—
2
LSB
INL
Integral non-linearity (standard
channel)
—
–3
—
3
LSB
DNL
Differential non-linearity
—
–1
—
1
LSB
OFS
Offset error
—
–6
—
6
LSB
GNE
Gain error
—
–4
—
4
LSB
Max leakage (precision channel)
150 °C
—
—
250
nA
Max leakage (standard channel)
150 °C
—
—
2500
nA
Max leakage (standard channel)
105 °C TA
—
5
250
nA
ADC Analog Pad
(pad going to one
ADC)
–5
—
5
mA
TUEprecision channels Total unadjusted error for precision Without current injection
channels
With current injection
Max positive/negative injection
–6
+/-4
6
LSB
TUEstandard/extended Total unadjusted error for standard/ Without current injection
extended channels
channels
With current injection7
–8
trecovery
+/-5
STOP mode to Run mode recovery
time
+/-6
LSB
8
+/-8
LSB
LSB
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