NXP Semiconductors
Data Sheet: Technical Data
Document Number: MPC5777M
Rev. 6, 06/2016
MPC5777M
MPC5777M Microcontroller
Data Sheet
• Three main CPUs, single issue, 32-bit CPU core complexes
(e200z7), one of which is a dedicated lockstep core.
– Power Architecture® embedded specification
compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 16 KB I-Cache and 4 KB D-Cache
• I/O Processor, dual issue, 32-bit CPU core complex
(e200z4), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing
Unit (LSP APU) instruction support for digital signal
processing (DSP)
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 8 KB I-Cache
• 8640 KB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 404 KB on-chip general-purpose SRAM including 64 KB
standby RAM (+ 192 KB data RAM included in the
CPUs). Of this 404 KB, 64 KB can be powered by a
separate supply so the contents of this portion can be
preserved when the main MCU is powered down.
• Multichannel direct memory access controllers (eDMA): 2
x 64 channels per eDMA (128 channels total)
• Triple Interrupt controller (INTC)
•
•
•
•
•
•
•
•
•
•
•
416 TEPBGA
512 TEPBGA
27mm x 27 mm
25 mm x 25 mm
– Dual phase-locked loops with stable clock domain for
peripherals and FM modulation domain for
computational shell
Dual crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters with
end-to-end ECC
Hardware Security Module (HSM) to provide robust
integrity checking of flash memory
System Integration Unit Lite (SIUL)
Boot Assist Module (BAM) supports factory programming
using serial bootload through ‘UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be:
– UART/LIN
– CAN
GTM104 — generic timer module
Enhanced analog-to-digital converter system with
– Twelve separate 12-bit SAR analog converters
– Ten separate 16-bit Sigma-Delta analog converters
Eight deserial serial peripheral interface (DSPI) modules
Two Peripheral Sensor Interface (PSI5) controllers
Three LIN and three UART communication interface
(LINFlexD) modules (6 total)
– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14,
LINFlexD_15, and LINFlexD_16 are Masters
Four modular controller area network (MCAN) modules
and one time-triggered controller area network
(M-TTCAN)
External Bus Interface (EBI)
– Dual routing of accesses to EBI
– Access path determined by access address
– Access path downstream of PFLASH controller
– Allows EBI accesses to share buffer and prefetch
capabilities of internal flash
– Allows internal flash accesses to be remapped to
memories connected to EBI
NXP reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
Table of Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Device feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2.1 Power supply and reference voltage pins/balls .15
2.2.2 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .16
2.2.3 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .17
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21
3.3 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . .23
3.4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .27
3.6 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.6.1 I/O input DC characteristics . . . . . . . . . . . . . . . .31
3.6.2 I/O output DC characteristics. . . . . . . . . . . . . . .35
3.7 I/O pad current specification . . . . . . . . . . . . . . . . . . . . .42
3.8 Reset pad (PORST, ESR0) electrical characteristics . .45
3.9 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.10 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.10.1 ADC input description . . . . . . . . . . . . . . . . . . . .53
3.10.2 SAR ADC electrical specification. . . . . . . . . . . .54
3.10.3 S/D ADC electrical specification . . . . . . . . . . . .58
3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.12 LVDS Fast Asynchronous Serial Transmission
(LFAST) pad electrical characteristics . . . . . . . . . . . . .67
3.12.1 LFAST interface timing diagrams . . . . . . . . . . .68
3.12.2 LFAST and MSC/DSPI LVDS interface
electrical characteristics . . . . . . . . . . . . . . . . . .69
3.12.3 LFAST PLL electrical characteristics . . . . . . . . .72
3.13 Aurora LVDS electrical characteristics . . . . . . . . . . . . .73
3.14 Power management: PMC, POR/LVD, sequencing . . .75
3.14.1 Power management electrical characteristics . .75
4
5
3.14.2 Power management integration . . . . . . . . . . . . 75
3.14.3 3.3 V flash supply . . . . . . . . . . . . . . . . . . . . . . . 76
3.14.4 Device voltage monitoring . . . . . . . . . . . . . . . . 77
3.14.5 Power up/down sequencing . . . . . . . . . . . . . . . 79
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 80
3.15.1 Flash memory program and erase
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.15.2 Flash memory FERS program and
erase specifications . . . . . . . . . . . . . . . . . . . . . 82
3.15.3 Flash memory Array Integrity and Margin
Read specifications . . . . . . . . . . . . . . . . . . . . . 83
3.15.4 Flash memory module life specifications . . . . . 84
3.15.5 Data retention vs program/erase cycles. . . . . . 84
3.15.6 Flash memory AC timing specifications . . . . . . 85
3.15.7 Flash read wait state and address pipeline
control settings . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.16.1 Debug and calibration interface timing . . . . . . . 86
3.16.2 DSPI timing with CMOS and LVDS pads . . . . . 94
3.16.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . 115
3.16.5 PSI5 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.7 External Bus Interface (EBI) Timing . . . . . . . . 119
3.16.8 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.16.9 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . 124
3.16.10Package characteristics. . . . . . . . . . . . . . . . . 124
3.17 416 TEPBGA (production) case drawing . . . . . . . . . 125
3.18 416 TEPBGA (emulation) case drawing. . . . . . . . . . 127
3.19 512 TEPBGA case drawing . . . . . . . . . . . . . . . . . . . 130
3.20 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 132
3.20.1 General notes for specifications at
maximum junction temperature . . . . . . . . . . . 132
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MPC5777M Microcontroller Data Sheet, Rev. 6
2
NXP Semiconductors
•
•
•
•
— Access path via dedicated AXBS slave port
– Avoids contention with other memory accesses
Two Dual-channel FlexRay controllers
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard
Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
Self-test capability
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
3
Introduction
1
Introduction
1.1
Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5777M series of
microcontroller units (MCUs). For functional characteristics, see the MPC5777M Microcontroller Reference Manual.
1.2
Description
This family of MCUs is targeted at automotive powertrain controller and chassis control applications from single cylinder
motorcycles at the very bottom end; through 4 to 8 cylinder gasoline and diesel engines; transmission control; steering and
breaking applications; to high end hybrid and advanced combustion systems at the top end.
Many of the applications are considered to be functionally safe and the family is designed to achieve ISO26262 ASIL-D
compliance.
1.3
Device feature
Table 1. MPC5777M feature
Feature
MPC5777M
Process
Main processor
55 nm
Core
e200z7
Number of main cores
2
Number of checker cores
1
Local RAM (per main core)
Single precision floating point
Yes
LSP
No
VLE
Yes
Cache
I/O processor
16 KB Instruction
64 KB Data
16 KB Instruction
4 KB Data
Core
e200z4
Local RAM
16 KB instruction
64 KB Data
Single precision floating point
Yes
LSP
Yes
VLE
Yes
Cache
8 KB instruction
Main processor frequency
300 MHz1
I/O processor frequency
200 MHz
MMU entries
0
MPU
Yes
Semaphores
Yes
MPC5777M Microcontroller Data Sheet, Rev. 6
4
NXP Semiconductors
Introduction
Table 1. MPC5777M feature (continued)
Feature
MPC5777M
CRC channels
2
Software watchdog timer
(Task SWT/Safety SWT)
4 (3/1)
Core Nexus class
3+
Sequence processing unit (SPU)
Yes
Debug and calibration interface (DCI) / run control
module
Yes
System SRAM
404 KB
Flash memory
8640 KB
Flash memory fetch accelerator
4 256 bit
Data flash memory (EEPROM)
8 64 KB
+ 2 16 KB
Flash memory overlay RAM
16 KB
External bus
32 bit
Calibration interface
64-bit IPS Slave
2 64
DMA channels
DMA Nexus Class
3+
LINFlex (UART/MSC)
6 (3/3)
MCAN/TTCAN
4/1
DSPI
(SPI/MSC/sync SCI)
8 (4/3/1)
Microsecond bus downlink
Yes
SENT bus
15
I
2C
2
PSI5 bus
5
PSI5-S UART-to-PSI5 interface
Yes
FlexRay
2 dual channel
Ethernet
MII / RMII
(SIPI / LFAST2) Interprocessor Communication
Zipwire
Interface
System timers
High speed
8 PIT channels
3 AUTOSAR® (STM)
64-bit PIT
BOSCH GTM Timer3
Yes
GTM RAM
Interrupt controller
58 KB
727 sources
ADC (SAR)
12
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
5
Introduction
Table 1. MPC5777M feature (continued)
Feature
MPC5777M
ADC (SD)
10
Temperature sensor
Yes
Self test controller
Yes
PLL
Dual PLL with FM
Integrated linear voltage regulator
None
External power supplies
5V
3.3 V7
1.2 V
Low-power modes
Packages
1
2
3
4
5
Stop mode
Slow mode
• 416 TEPBGA4
• 512 TEPBGA5
Includes four user-programmable CPU cores and one safety core. The main computational shell consists of
dual e200z7 CPUs operating at 300 MHz with a third identical core running as a safety checker core in delayed
lockstep mode with one of the dual e200z7 cores. The I/O subsystem includes a CPU targeted at managing
the peripherals. This is an e200z4 CPU running at 200 MHz. The fifth CPU is an e200z0 running at 100 MHz
and is embedded in the Hardware Security Module. All CPUs are compatible with the Power Architecture.
LVDS Fast Asynchronous Serial Transmission
BOSCH® is a registered trademark of Robert Bosch GmbH.
416 TEPBGA package supports development and production applications with the same package footprint.
512 TEPBGA package supports development and production applications with the same package footprint.
MPC5777M Microcontroller Data Sheet, Rev. 6
6
NXP Semiconductors
Block diagram
7
1.4
Introduction
The figures below show the top-level block diagrams.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductor s
NXP Semiconductors
MPC5777M Microcontroller Data Sheet, Rev. 6
8
Introduction
Figure 1. Block diagram
Package pinouts and signal descriptions
EBI
TDM
PCM
LVIIO
2 x XBIC
LVIFLASH
2 x AXBS
LVI 1.2V
2 x SMPU
HVI 1.2V
PRAM
PMC
PFLASH
SEMA4
TSENS
INTC_0
4 x SWT
3 x STM
FLEXRAY_1
IIC_1
2 x DMA
9 x SAR ADC
12 x CMU
FEC
PSI5_1
PSI5_S_0
BAF
GTM
SENT_1
CRC_1
SSCM
3 x SAR ADC
3 x DSPI
FCCU
Peripheral Bus (AIPS_1)
PASS
CFLASH_0
PSI5_0
2 x LFAST
FLEXRAY_0
2 x LINFlexD
SENT_0
Peripheral
Cluster B
5 x SD ADC
IIC_0
2 x SIPI
SUIL2
5 x DSPI
ME
4 x LINFlexD
CMU_PLL
4 x MCAN
PLL
TTCAN_0
OSC_DIG
SRAM CAN
RCOSC_DIG_0
5 x SD ADC
CGM
HSM INTERFACE
RGM
DTS
PCU
Peripheral
Cluster A
JDC
WKPU
Peripheral Bus (AIPS_0)
STCU2
JTAGM
MEMU
IMA
CRC_0
10 x DMAMUX
ATX
2 x PIT_RTC
Figure 2. Periphery allocation
2
Package pinouts and signal descriptions
See the MPC5777M Microcontroller Reference Manual for signal information.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
9
NXP Semiconductors
2.1
Package pinouts
The BGA ballmap package pinouts for the 416 and 512 production and emulation devices are shown in the following figures.
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MPC5777M Microcontroller Data Sheet, Rev. 6
13
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See Figure 20 for capacitor integration.
Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over voltage, temperature, and aging.
Each VDD_LV pin requires both a 0.1µF and 0.01µF capacitor for high-frequency bypass and EMC requirements.
The recommended flash regulator composition capacitor is 1.5 µF typical X7R or X5R, with –50% and +35% as min and
max. This puts the min cap at 0.75 µF.
Start-up time of the internal flash regulator from release of the LVD360 is worst case 500 us. This is based on the typical
CHV_FLA bulk capacitance value.
For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between VDD_HV_PMC and
VSS_HV.
In the 512BGA package, VDD_HV_PMC is shorted to VDD_HV_IO_MAIN. Use a local 200 nF capacitor on 512BGA balls A29,
B28, F24, G3, in addition to the normal VDD_HV_IO_MAIN bulk and local external capacitance.
For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and
VSS_HV_ADV.
3.14.3
3.3 V flash supply
Table 36. Flash power supply
Value
Symbol
VDD_HV_FLA1
1
2
Parameter
CC
Flash regulator DC output voltage
Conditions
Unit
Min
Typ
Max
Before trimming
3.12
3.3
3.5
After trimming
–40°C TJ 25°C
3.15
3.3
3.4
After trimming
25°C TJ 150°C
3.10
3.3
3.4
V
Min value accounts for all static and dynamic variations of the regulator (min cap as 0,75uF).
Min value of 3.1 V for VDD_HV_REG at 3.15V assumes that the auxiliary regulator on VDD_LV does not actively provide
any current to the chip. If the auxiliary regulator actively provides current, the min value may go lower than 3.1 V drop to
IR drop caused by auxiliary current demanding on VDD_HV_REG supply.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
75
Electrical characteristics
3.14.4
Device voltage monitoring
The LVD/HVDs and their associated levels for the device are given in the following table. The figure below illustrates the
workings of voltage monitoring threshold.
VDD_xxx
VHVD(rise)
VHVD(fall)
VLVD(rise)
VLVD(fall)
tVDASSERT
tVDRELEASE
HVD TRIGGER
(INTERNAL)
tVDRELEASE
tVDASSERT
LVD TRIGGER
(INTERNAL)
Figure 21. Voltage monitor threshold definition
Table 37. Voltage monitor electrical characteristics1
Value
Symbol
Parameter
VPORUP_LV2 CC LV supply power on reset threshold
Conditions
Unit
Rising voltage (power up)
Falling voltage (power down)
Hysteresis on power-up
3
Min
Typ
Max
1111
—
1235
1015
—
1125
50
—
—
mV
VLVD096
CC LV internal4 supply low voltage
monitoring
See note 5
1015
—
1145
mV
VLVD108
CC Core LV internal4 supply low voltage See note 6
monitoring
1150
—
1220
mV
VLVD112
CC LV external7 supply low voltage
monitoring
1175
—
1235
mV
See note 5
MPC5777M Microcontroller Data Sheet, Rev. 6
76
NXP Semiconductors
Electrical characteristics
Table 37. Voltage monitor electrical characteristics1 (continued)
Value
Symbol
—
1475
mV
VHVD145
CC LV externa10 supply high voltage
reset threshold
—
1430
—
1510
mV
VPORUP_HV2 CC HV supply power on reset threshold9 Rising voltage (power up) on
PMC/IO Main supply
4040
—
Rising voltage (power up) on
IO JTAG and Osc supply
2730
—
3030
Rising voltage (power up) on
ADC supply
2870
—
3182
Falling voltage (power down)11
2850
—
3162
Hysteresis on power up12
878
—
1630
CC HV supply power-on reset voltage
monitoring
Rising voltage
2420
—
2780
Falling voltage
2400
—
2760
CC HV supply low voltage monitoring
Rising voltage
2750
—
3000
Falling voltage
2700
—
2950
Rising voltage
—
—
3120
Falling voltage
2920
—
3100
CC Flash supply high voltage monitoring Rising voltage
3435
—
3650
Falling voltage
3415
—
—
Rising voltage
—
—
4000
Falling voltage
3600
—
3880
Rising voltage
4110
—
4410
Falling voltage
3970
—
4270
Rising voltage
5560
—
5960
Falling voltage
5500
—
5900
VLVD360
VLVD400
VHVD600
CC Flash supply low voltage
monitoring13
CC HV supply low voltage monitoring
CC HV supply low voltage monitoring
CC HV supply high voltage monitoring
448010 mV
mV
mV
mV
mV
mV
mV
mV
CC Voltage detector threshold crossing
assertion
—
0.1
—
2
µs
tVDRELEASE CC Voltage detector threshold crossing
de-assertion
—
5
—
20
µs
tVDASSERT
5
Max
1385
VHVD360
4
Typ
See note 8
VLVD295
3
Unit
Min
CC LV external10 supply high voltage
monitoring
VLVD270
2
Conditions
VHVD140
VPOR240
1
Parameter
For VDD_LV levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR
drop is estimated by multiplying the supply current by 0.5 .
VPORUP_LV and VPORUP_HV threshold are untrimmed values before completion of the power-up sequence. All other
LVD/HVD thresholds are provided after trimming.
Assume all of LVDs on LV supplies disabled.
LV internal supply levels are measured on device internal supply grid after internal voltage drop.
LVD is released after tVDRELEASE temporization when upper threshold is crossed, LVD is asserted tVDASSERT after
detection when lower threshold is crossed.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
77
Electrical characteristics
6
This specification is driven by LVD108_C. There are additional LVDs on PLL and Flash VDD_LV supply nets which will
assert at voltage below LVD108_C.
7
LV external supply levels are measured on the die side of the package bond wire after package voltage drop. This is
monitoring external regulator supply voltage and board voltage drop. This does not guarantee device is working down
to minimum threshold. For minimum supply, refer to operating condition table.
8
HVD is released after tVDRELEASE temporization when lower threshold is crossed, HVD is asserted tVDASSERT after
detection when upper threshold is crossed. HVD140 does not cause reset.
9
This supply also needs to be below 5472 mV (untrimmed HVD600 min)
10
The PMC supply also needs to be below 5472 mV (untrimmed HVD600 mV).
11
Untrimmed LVD300_A will be asserted first on power down.
12
Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage
supply. When these two supplies are shorted together, the hysteresis is as is shown in Table 37. If the supplies are not
shorted (VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.
13
VDD_HV_FLA supply range is guaranteed by internal regulator.
3.14.5
Power up/down sequencing
Table 38 shows the constraints and relationships for the different power supplies
Table 38. Device supply relation during power-up/power-down sequence
Supply 21
VDD_LV VDD_HV_PMC VDD_HV_IO VDD_HV_FLA VDD_HV_ADV VDD_HV_ADR ALTREFn2 VDDSTBY
VDD_LV
VDD_HV_PMU
Supply 11
VDD_HV_IO
VDD_HV_FLA
2 mA3
VDD_HV_ADV
VDD_HV_ADR
ALTREFn
5 mA
10 mA4
10 mA4
VDDSTBY
1
Red cells: supply1 (row) can exceed supply2 (column), granted that external circuitry ensure current flowing from supply1
is less than absolute maximum rating current value provided.
2 ALTREFn are the alternate references for the ADC that can be used in place of the default reference (V
DD_HV_ADR_*). They
are SARB.ALTREF and SAR2.ALTREF.
3 V
DD_HV_FLA is generated internally in normal mode. Above current constraints is guaranteed.
4 ADC performances is not guaranteed with ALTREFn above V
DD_HV_IO / VDD_HV_ADV
During power-up, all functional terminals are maintained into a known state as described within the following table.
MPC5777M Microcontroller Data Sheet, Rev. 6
78
NXP Semiconductors
Electrical characteristics
Table 39. Functional terminals state during power-up and reset
1
2
3
4
5
6
TERMINAL
TYPE1
POWERUP2
pad state
RESET
pad state
DEFAULT
pad state3
PORST
Strong
pull-down4
Weak pull-down
Weak pull-down
ESR05
Strong
pull-down
Strong pull-down
Weak pull-up
ESR1
High impedance
Weak pull-up
Weak pull-up
—
TESTMODE
Weak pull-down
Weak pull-down6
Weak pull-down6
—
GPIO
Weak pull-up4
Weak pull-up
Weak pull-up
—
ANALOG
High impedance
High impedance
High impedance
—
ERROR0
High impedance
High impedance
High impedance
During functional reset, pad state
can be overridden by FCCU
JCOMP
High impedance
Weak pull-down
Weak pull-down
—
TCK
High impedance
Weak pull-down
Weak pull-down
—
TMS
High impedance
Weak pull-up
Weak pull-up
—
TDI
High impedance
Weak pull-up
Weak pull-up
—
TDO
High impedance
Weak pull-up
High impedance
—
Comments
Power-on reset pad
Functional reset pad.
Refer to pinout information for terminal type
POWERUP state is guaranteed from VDD_HV_IO>1.1 V and maintained until supply cross the power-on reset
threshold: VPORUP_LV for LV supply, VPORUP_HV for high voltage supply.
Before software configuration
Pull-down and pull-up strength are provided as part of Table 13 in Section 3.6.1, I/O input DC characteristics.
Pull-up/Pull-down are activated within 2 µs after internal reset has been asserted. Actual pad transition will depend
on external capacitance.
Unlike ESR0, ESR1 is provided as normal GPIO and implements weak pull-up during power-up.
An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the
package TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to VSS_HV_IO on the
board for maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and
has no affect afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up.
The TESTMODE pin can be connected externally directly to ground without any other components.
3.15
Flash memory electrical characteristics
The following sections contain flash memory electrical specifications.
3.15.1
Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this section are defined for a single
embedded flash memory within an SoC, and represent average currents for given supplies
and operations.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
79
Electrical characteristics
Table 40 shows the estimated Program/Erase times.
Table 40. Flash memory program and erase specifications (pending characterization)
Factory
Programming3,4
Symbol
Characteristic1
Typ2 Initial Max
Initial Max
Full Temp
Field Update
Typical
End of
Life5
20°C Ta -40°C TJ -40°C TJ
30°C
150°C
150 °C
tdwpgm Doubleword (64 bits) program time
43
100
150
Lifetime Max6
1,000
cycles
55
Units
250,000
cycles
500
µs
tppgm
Page (256 bits) program time
73
200
300
108
500
µs
tqppgn
Quad-page (1024 bits) program time
268
800
1,200
396
2,000
µs
t16kers
16 KB Block erase time
168
290
320
250
1,000
ms
34
45
50
40
1,000
ms
217
360
390
310
1,200
ms
69
100
110
90
1.200
ms
315
490
590
420
1,600
ms
138
180
210
170
1,600
ms
t256kers 256 KB Block erase time
884
1,520
2,030
1,080
4,000
—
ms
t256kpgm 256 KB Block program time
552
720
880
650
4,000
—
ms
t16kpgn 16 KB Block program time
t32kers
32 KB Block erase time
t32kpgm 32 KB Block program time
t64kers
64 KB Block erase time
t64kpgm 64 KB Block program time
1
2
3
4
5
6
Program times are actual hardware programming times and do not include software overhead. Block program times assume
quad-page programming.
Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
Conditions: 150 cycles, nominal voltage.
Plant Programming times provide guidance for timeout limits used in the factory.
Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical
End of Life program and erase values may be used for throughput calculations.
Conditions: -40°C TJ 150°C; full spec voltage.
MPC5777M Microcontroller Data Sheet, Rev. 6
80
NXP Semiconductors
Electrical characteristics
3.15.2
Flash memory FERS program and erase specifications
Table 41. Flash memory FERS program and erase specifications (pending characterization)
Factory Programming with FERS=1 and Vfers
pin is
5V ± 5%2
Characteristic1
Symbol
Typ3
Initial Max
Initial Max
Full Temp
Units
20°CTA30°C4 -40°CTJ150°C4
tdwpgm
Doubleword (64 bits) program time
30
90
135
µs
tppgm
Page (256 bits) program time
43
145
218
µs
tqppgn
Quad-page (1024 bits) program time
134
530
795
µs
t16kers
16 KB erase time
160
782
782
ms
t16kpgn
16 KB program time
18
24
35
ms
t32kers
32 KB erase time
190
782
782
ms
t32kpgm
32 KB program time
36
47
68
ms
t64kers
64 KB erase time
250
782
782
ms
t64kpgm
64 KB program time
72
94
135
ms
t256kers
256 KB erase time
600
1,380
2,070
ms
t256kpgm
256 KB program time
288
374
568
ms
1
Program times are actual hardware programming times and do not include software overhead. Block program times assume
quad-page programming.
2 Conditions: 150 cycles, nominal voltage.
3 Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
4 Plant Programming times provide guidance for timeout limits used in the factory.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
81
Electrical characteristics
3.15.3
Flash memory Array Integrity and Margin Read specifications
Table 42. Flash memory Array Integrity and Margin Read specifications (characterized but not tested)
Symbol
Characteristic
Min
Typical
Max1
Units2
tai16kseq
Array Integrity time for sequential sequence on 16KB block.
—
—
512 ×
Tperiod ×
Nread
—
tai32kseq
Array Integrity time for sequential sequence on 32KB block.
—
—
1024 ×
Tperiod ×
Nread
—
tai64kseq
Array Integrity time for sequential sequence on 64KB block.
—
—
2048 ×
Tperiod ×
Nread
—
tai256kseq Array Integrity time for sequential sequence on 256KB block.
—
—
8192 ×
Tperiod ×
Nread
—
taifullseq
Array Integrity time for sequential sequence full array.
—
—
3.77e5 ×
Tperiod ×
Nread
—
taifullprop
Array Integrity time for proprietary sequence (applies to full
array or single block).
—
—
9.96e6 ×
Tperiod ×
Nread
—
tmr16kseq Margin Read time for sequential sequence on 16KB block.
73.81
—
110.7
µs
tmr32kseq Margin Read time for sequential sequence on 32KB block.
128.43
—
192.6
µs
tmr64kseq Margin Read time for sequential sequence on 64KB block.
237.65
—
356.5
µs
tmr256kseq Margin Read time for sequential sequence on 256KB block.
893.01
—
1,339.5
µs
45.21
—
60.26
ms
tmrfull
Margin Read time for sequential sequence full array.
1
Array Integrity times need to be calculated and are dependent on system frequency and number of clocks per read.
The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal
5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup
that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read,
and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2
The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
MPC5777M Microcontroller Data Sheet, Rev. 6
82
NXP Semiconductors
Electrical characteristics
3.15.4
Flash memory module life specifications
Table 43. Flash memory module life spec (pending characterization)
Symbol
Array P/E
cycles
Data
retention
1
2
Characteristic
Conditions
Min
Typical
Units
Number of program/erase cycles per
block for 16 KB, 32 KB and 64 KB
blocks.1
—
250,000
—
P/E
cycles
Number of program/erase cycles per
block for 256 KB blocks.2
—
1,000
250,000
P/E
cycles
Blocks with 0 – 1,000 P/E
cycles.
50
—
Years
Blocks with 100,000 P/E
cycles.
20
—
Years
Blocks with 250,000 P/E
cycles.
10
—
Years
Minimum data retention.
Program and erase supported across standard temperature specs.
Program and erase supported across standard temperature specs.
3.15.5
Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window
represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the
qualification limits.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
83
Electrical characteristics
3.15.6
Flash memory AC timing specifications
Table 44. Flash memory AC timing specifications (characterized but not tested)
Symbol
Characteristic
Min
Typical
Max
Units
tpsus
Time from setting the MCR-PSUS bit until MCR-DONE bit
is set to a 1.
—
7 plus four
system
clock
periods
9.1 plus
four
system
clock
periods
µs
tesus
Time from setting the MCR-ESUS bit until MCR-DONE bit
is set to a 1.
—
16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
µs
tres
Time from clearing the MCR-ESUS or PSUS bit with
EHV = 1 until DONE goes low.
—
—
100
ns
tdone
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared.
—
—
5
ns
tdones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1.
—
16 plus
four
system
clock
periods
20.8 plus
four
system
clock
periods
µs
16 plus
seven
system
clock
periods
—
45 plus
seven
system
clock
periods
µs
tdrcv
Time to recover once exiting low power mode.
taistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin
Read or Array Integrity until the UT0-AID bit is cleared.
This time also applies to the resuming from a suspend or
breakpoint by clearing AISUS or clearing NAIBP
—
—
5
ns
taistop
Time from 1 to 0 transition of UTO-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also
applies to the UT0-AISUS to UT0-AID setting in the event
of a Array Integrity suspend request.
—
—
80
plus fifteen
system
clock
periods
ns
tmrstop
Time from 1 to 0 transition of UTO-AIE initiating a Margin
10.36
Read abort until the UT0-AID bit is set. This time also
plus four
applies to the UT0-AISUS to UT0-AID setting in the event system
of a Margin Read suspend request.
clock
periods
—
20.42
plus four
system
clock
periods
µs
3.15.7
Flash read wait state and address pipeline control settings
Table 45 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic
flash access times of the C55FMC array at 150 °C.
MPC5777M Microcontroller Data Sheet, Rev. 6
84
NXP Semiconductors
Electrical characteristics
Table 45. Flash Read Wait State and Address Pipeline Control Combinations
3.16
Flash Frequency
RWSC setting
APC setting
0 MHz < fFLASH 33 MHz
0
0
33 MHz < fFLASH 100 MHz
2
1
100 MHz < fFLASH 133 MHz
3
1
133 MHz < fFLASH 167 MHz
4
1
167 MHz < fFLASH 200 MHz
5
2
AC specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
3.16.1
Debug and calibration interface timing
3.16.1.1
JTAG interface timing
Table 46. JTAG pin AC electrical characteristics1,2
Value
#
Symbol
Characteristic
Unit
Min
Max
1
tJCYC
CC TCK cycle time
100
—
ns
2
tJDC
CC TCK clock pulse width
40
60
%
3
tTCKRISE
CC TCK rise and fall times (40%–70%)
—
3
ns
4
tTMSS, tTDIS
CC TMS, TDI data setup time
5
—
ns
5
tTMSH, tTDIH
CC TMS, TDI data hold time
5
—
ns
ns
6
tTDOV
CC TCK low to TDO data valid
—
163
7
tTDOI
CC TCK low to TDO data invalid
0
—
ns
8
tTDOHZ
CC TCK low to TDO high impedance
—
15
ns
9
tJCMPPW
CC JCOMP assertion time
100
—
ns
10
tJCMPS
CC JCOMP setup time to TCK low
40
—
ns
ns
11
tBSDV
CC TCK falling edge to output valid
—
6004
12
tBSDVZ
CC TCK falling edge to output valid out of high impedance
—
600
ns
13
tBSDHZ
CC TCK falling edge to output high impedance
—
600
ns
14
tBSDST
CC Boundary scan input valid to TCK rising edge
15
—
ns
15
tBSDHT
CC TCK rising edge to boundary scan input invalid
15
—
ns
1
These specifications apply to JTAG boundary scan only. See Table 47 for functional specifications.
JTAG timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
3 Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
85
Electrical characteristics
4
Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG
delay.
TCK
2
3
2
1
3
Figure 22. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
7
8
TDO
Figure 23. JTAG test access port timing
MPC5777M Microcontroller Data Sheet, Rev. 6
86
NXP Semiconductors
Electrical characteristics
TCK
10
JCOMP
9
Figure 24. JTAG JCOMP timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
87
Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 25. JTAG boundary scan timing
3.16.1.2
Nexus interface timing
Table 47. Nexus debug port timing1
Value
#
Symbol
Characteristic
Unit
Min
Max
7
tEVTIPW CC EVTI pulse width
4
—
tCYC2
8
tEVTOPW CC EVTO pulse width
40
—
ns
9
tTCYC
CC TCK cycle time
23,4
—
tCYC2
9
tTCYC
CC Absolute minimum TCK cycle time5 (TDO/TDOC sampled on posedge of
TCK)
406
—
ns
Absolute minimum TCK cycle time7 (TDO/TDOC sampled on negedge of
TCK)
206
—
5
—
118
tNTDIS
CC TDI/TDIC data setup time
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
88
NXP Semiconductors
Electrical characteristics
Table 47. Nexus debug port timing1 (continued)
Value
#
Symbol
12
9
tNTDIH
Characteristic
CC TDI/TDIC data hold time
13
tNTMSS CC TMS/TMSC data setup time
14
tNTMSH CC TMS/TMSC data hold time
15
10
16
Unit
11
—
CC TDO/TDOC propagation delay from falling edge of TCK
—
CC TDO/TDOC hold time with respect to TCK falling edge (minimum
TDO/TDOC propagation delay)
Min
Max
5
—
ns
5
—
ns
5
—
ns
—
16
ns
2.25
—
ns
1
Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
2
tCYC is system clock period.
3 Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is
less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral
frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided
by a number greater than or equal to that specified here.
4 This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
5 This value is TDO/TDOC propagation time 36ns + 4 ns setup time to sampling edge.
6 This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
7 This value is TDO/TDOC propagation time 16ns + 4 ns setup time to sampling edge.
8 TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.
9 TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.
10 TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.
11 Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.
TCK
EVTI
EVTO
9
Figure 26. Nexus event trigger and test clock timings
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
89
Electrical characteristics
TCK
11
13
12
14
TMS/TMSC,
TDI/TDIC
15
16
TDO/TDOC
Figure 27. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing
3.16.1.3
Aurora LVDS interface timing
Table 48. Aurora LVDS interface timing specifications
Value
Symbol
Parameter
Unit
Min
Typ
Max
—
—
1250
Mbps
—
—
5
µs
—
—
5
µs
—
—
4
µs
Data Rate
—
SR Data rate
STARTUP
tSTRT_BIAS
tSTRT_TX
tSTRT_RX
CC Bias startup time1
CC Transmitter startup time2
3
CC Receiver startup time
1
Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
2
Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
MPC5777M Microcontroller Data Sheet, Rev. 6
90
NXP Semiconductors
Electrical characteristics
3
Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
3.16.1.4
Aurora debug port timing
Table 49. Aurora debug port timing
Value
#
Characteristic
Unit
Max
625
1250
MHz
tREFCLK
1a
tMCYC
CC Reference clock rise/fall time
—
400
ps
2
tRCDC
CC Reference clock duty cycle
45
55
%
3
JRC
CC Reference clock jitter
—
40
ps
4
tSTABILITY
CC Reference clock stability
50
—
PPM
5
BER
6
CC Reference clock frequency
Min
1
–12
—
CC Bit error rate
—
10
JD
SR Transmit lane deterministic jitter
—
0.17
OUI
7
JT
SR Transmit lane total jitter
—
0.35
OUI
8
SO
CC Differential output skew
—
20
ps
9
SMO
CC Lane to lane output skew
—
1000
ps
OUI
1
625 Mbps
1600
1600
ps
1.25 Gbps
800
800
10
1
Symbol
CC Aurora lane unit interval
± 100 PPM
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
91
Electrical characteristics
1
2
2
CLOCKREF Zero Crossover
CLOCKREF +
1a
1a
1a
8
8
1a
8
Tx Data Ideal Zero Crossover
Tx Data +
Tx Data [n]
Zero Crossover
Tx Data [n+1]
Zero Crossover
Tx Data [m]
Zero Crossover
9
9
Figure 28. Aurora timings
MPC5777M Microcontroller Data Sheet, Rev. 6
92
NXP Semiconductors
Electrical characteristics
DSPI timing with CMOS and LVDS1 pads
3.16.2
DSPI channel frequency support is shown in Table 50. Timing specifications are shown in Table 51, Table 52, Table 54,
Table 55 and Table 56.
Table 50. DSPI channel frequency support
Max usable
frequency (MHz)1,2
DSPI use mode
CMOS (Master mode)
LVDS (Master mode)3
Full duplex – Classic timing (Table 51)
17
Full duplex – Modified timing (Table 52)
30
Output only mode (SCK/SOUT/PCS) (Table 51 and Table 52)
30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 56)
30
Full duplex – Modified timing (Table 54)
33
Output only mode TSB mode (SCK/SOUT/PCS) (Table 55)
40
1
Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
Maximum usable frequency does not take into account external device propagation delay.
3 µS Channel and LVDS timing is not supported for DSPI12.
2
3.16.2.1
DSPI master mode full duplex timing with CMOS and LVDS pads
3.16.2.1.1
DSPI CMOS Master Mode – Classic Timing
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
Value2
Condition
#
1
2
Symbol
tSCK
tCSC
Characteristic
CC SCK cycle time
Unit
Pad drive3
Load (CL)
Min
Max
SCK drive strength
Very strong
25 pF
33.0
—
Strong
50 pF
80.0
—
Medium
50 pF
200.0
—
25 pF
(N4 × tSYS5) – 16
—
Strong
50 pF
(N4
tSYS5)
– 16
—
Medium
50 pF
(N4 × tSYS5) – 16
—
tSYS5)
—
ns
CC PCS to SCK delay SCK and PCS drive strength
Very strong
PCS medium
PCS = 50 pF
and SCK strong SCK = 50 pF
(N4
×
×
– 29
ns
1. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
93
Electrical characteristics
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
Value2
Condition
#
3
4
Symbol
tASC
tSDC
Characteristic
CC After SCK delay
CC SCK duty cycle7
Unit
Pad drive3
Load (CL)
Min
Max
SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Medium
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
PCS medium
PCS = 0 pF
and SCK strong SCK = 50 pF
(M6 × tSYS5) – 35
—
ns
SCK drive strength
Very strong
Strong
Medium
0 pF
1/
0 pF
1/
0 pF
1/
2tSCK
2tSCK
2tSCK
–2
1/
2tSCK
+2
–2
1/
2tSCK
+2
–5
1/
2tSCK
+5
ns
PCS strobe timing
5
6
tPCSC
tPASC
CC PCSx to PCSS
time8
PCS and PCSS drive strength
CC PCSS to PCSx
time8
PCS and PCSS drive strength
Strong
Strong
25 pF
25 pF
16.0
—
ns
16.0
—
ns
ns
SIN setup time
7
tSUI
CC SIN setup time to
SCK9
SCK drive strength
Very strong
25 pF
25.0
—
Strong
50 pF
32.75
—
Medium
50 pF
52.0
—
–1.0
—
SIN hold time
8
tHI
CC SIN hold time from SCK drive strength
SCK9
Very strong
0 pF
Strong
0 pF
–1.0
—
Medium
0 pF
–1.0
—
ns
SOUT data valid time (after SCK edge)
9
tSUO
CC SOUT data valid
time from SCK10
SOUT and SCK drive strength
Very strong
25 pF
—
7.0
Strong
50 pF
—
8.0
Medium
50 pF
—
16.0
ns
SOUT data hold time (after SCK edge)
MPC5777M Microcontroller Data Sheet, Rev. 6
94
NXP Semiconductors
Electrical characteristics
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
Value2
Condition
#
10
Symbol
tHO
Characteristic
CC SOUT data hold
time after SCK10
Pad drive3
Unit
Load (CL)
Min
Max
SOUT and SCK drive strength
Very strong
25 pF
–7.7
—
Strong
50 pF
–11.0
—
Medium
50 pF
–15.0
—
ns
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
All timing values for output signals in this table are measured to 50% of the output voltage.
3
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
4
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless
TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS
and SCK are driven by the same edge of DSPI_CLKn).
5 t
SYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6 M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
7 t
SDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8 PCSx and PCSS using same pad configuration.
9 Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10 SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
95
Electrical characteristics
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 29. DSPI CMOS master mode – classic timing, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
First Data
Data
tSUO
SOUT
First Data
Data
Last Data
tHO
Last Data
Figure 30. DSPI CMOS master mode – classic timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
96
NXP Semiconductors
Electrical characteristics
tPCSC
tPASC
PCSS
PCSx
Figure 31. DSPI PCS strobe (PCSS) timing (master mode)
3.16.2.1.2
DSPI CMOS Master Mode – Modified Timing
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
Value2
Condition
#
1
2
Symbol
tSCK
tCSC
Characteristic
CC SCK cycle time
CC PCS to SCK delay
Pad drive3
4
tSDC
CC After SCK delay
CC SCK duty cycle7
Max
Very strong
25 pF
33.0
—
Strong
50 pF
80.0
—
Medium
50 pF
200.0
—
25 pF
(N4 × tSYS5) – 16
—
50 pF
(N4
×
tSYS5)
– 16
—
Medium
50 pF
(N4
×
tSYS5)
– 16
—
PCS medium
and SCK
strong
PCS = 50 pF
SCK = 50 pF
(N4 × tSYS5) – 29
—
ns
SCK and PCS drive strength
Strong
tASC
Min
SCK drive strength
Very strong
3
Unit
Load (CL)
ns
SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
Medium
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
PCS medium
and SCK
strong
PCS = 0 pF
SCK = 50 pF
(M6 × tSYS5) – 35
—
ns
SCK drive strength
Very strong
0 pF
1
Strong
0 pF
1/
0 pF
1/
Medium
/2tSCK – 2
2tSCK
2tSCK
1
/2tSCK + 2
–2
1/
2tSCK
+2
–5
1/
2tSCK
+5
ns
PCS strobe timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
97
Electrical characteristics
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
Value2
Condition
#
5
6
Symbol
tPCSC
tPASC
Characteristic
Pad drive3
Unit
Load (CL)
CC PCSx to PCSS
time8
PCS and PCSS drive strength
CC PCSS to PCSx
time8
PCS and PCSS drive strength
Strong
Min
Max
16.0
—
ns
16.0
—
ns
25 – (P10 × tSYS5)
—
ns
25 pF
Strong
25 pF
SIN setup time
7
tSUI
CC SIN setup time to
SCK
CPHA = 09
SIN setup time to
SCK
CPHA = 19
SCK drive strength
Very strong
25 pF
10
Strong
50 pF
32.75 – (P
5
S )
× tSY
—
Medium
50 pF
52 – (P10 × tSYS5)
—
SCK drive strength
Very strong
25 pF
25.0
—
Strong
50 pF
32.75
—
Medium
50 pF
52.0
—
ns
SIN hold time
8
tHI
CC SIN hold time from SCK drive strength
SCK
Very strong
0 pF
CPHA = 09
Strong
0 pF
Medium
0 pF
–1 + (P9 × tSYS4)
—
×
tSYS4)
—
×
tSYS4)
—
–1 +
(P9
–1 +
(P9
SIN hold time from SCK drive strength
SCK
Very strong
0 pF
CPHA = 19
Strong
0 pF
Medium
0 pF
–1.0
—
–1.0
—
–1.0
—
—
7.0 + tSYS5
tSYS5
ns
ns
SOUT data valid time (after SCK edge)
9
tSUO
CC SOUT data valid
time from SCK
CPHA = 010
SOUT data valid
time from SCK
CPHA = 110
SOUT and SCK drive strength
Very strong
25 pF
Strong
50 pF
—
8.0 +
Medium
50 pF
—
16.0 + tSYS5
ns
SOUT and SCK drive strength
Very strong
25 pF
—
7.0
Strong
50 pF
—
8.0
Medium
50 pF
—
16.0
ns
SOUT data hold time (after SCK edge)
MPC5777M Microcontroller Data Sheet, Rev. 6
98
NXP Semiconductors
Electrical characteristics
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
Value2
Condition
#
10
Symbol
tHO
Characteristic
CC SOUT data hold
time after SCK
CPHA = 011
Pad drive3
Min
Max
SOUT and SCK drive strength
Very strong
25 pF
–7.7 + tSYS5
—
Strong
50 pF
–11.0 + tSYS5
—
50 pF
tSYS5
—
Medium
SOUT data hold
time after SCK
CPHA = 111
Unit
Load (CL)
–15.0 +
ns
SOUT and SCK drive strength
Very strong
25 pF
–7.7
—
Strong
50 pF
–11.0
—
Medium
50 pF
–15.0
—
ns
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
All timing values for output signals in this table are measured to 50% of the output voltage.
3 Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
4 N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless
TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS
and SCK are driven by the same edge of DSPI_CLKn).
5 t
SYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
6 M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
7 t
SDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8 PCSx and PCSS using same pad configuration.
9 Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10 P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is
automatically set to 1.
11 SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
99
Electrical characteristics
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 32. DSPI CMOS master mode – modified timing, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
tHI
Data
First Data
tSUO
SOUT
First Data
Data
Last Data
tHO
Last Data
Figure 33. DSPI CMOS master mode – modified timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
100
NXP Semiconductors
Electrical characteristics
tPCSC
tPASC
PCSS
PCSx
Figure 34. DSPI PCS strobe (PCSS) timing (master mode)
3.16.2.1.3
DSPI LVDS Master Mode – Modified Timing
Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1
Value1
Condition
#
Symbol
Characteristic
Unit
Pad drive
Load
Min
Max
15 pF
to 25 pF
differential
30.0
—
ns
(N2 × tSYS3) – 10
—
ns
50 pF
(N2
Medium
50 pF
(N2
Very strong
1
tSCK
CC SCK cycle time
LVDS
2
tCSC
CC PCS to SCK delay PCS drive strength
(LVDS SCK)
Very strong
25 pF
×
tSYS3)
– 10
—
ns
×
tSYS3)
– 32
—
ns
PCS = 0 pF
SCK = 25 pF
(M4 × tSYS3) – 8
—
ns
Strong
PCS = 0 pF
SCK = 25 pF
(M4 × tSYS3) – 8
—
ns
Medium
PCS = 0 pF
SCK = 25 pF
(M4 × tSYS3) – 8
—
ns
LVDS
15 pF
to 25 pF
differential
Strong
3
tASC
CC After SCK delay
(LVDS SCK)
4
tSDC
CC SCK duty cycle5
7
tSUI
CC
1/
2tSCK
–2
1/
2tSCK
+2
ns
SIN setup time
SIN setup time to SCK drive strength
SCK
LVDS
15 pF
CPHA = 06
to 25 pF
differential
23 – (P7 × tSYS3)
—
ns
SIN setup time to SCK drive strength
SCK
LVDS
15 pF
CPHA = 16
to 25 pF
differential
23
—
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
101
Electrical characteristics
Table 53. DSPI LVDS master timing – full duplex – modified transfer format (MTFE = 1), CPHA = 0 or 1
Value1
Condition
#
Symbol
Characteristic
Unit
Pad drive
8
tHI
9
tSUO
10
1
2
3
4
5
6
7
tHO
Load
CC
Min
Max
–1 + (P7 × tSYS3)
—
ns
–1
—
ns
—
7.0 + tSYS3
ns
—
7.0
ns
–7.5 + tSYS3
—
ns
–7.5
—
ns
SIN Hold Time
SIN hold time
from SCK
CPHA = 06
SCK drive strength
SIN hold time
from SCK
CPHA = 16
SCK drive strength
LVDS
LVDS
CC
0 pF differential
0 pF differential
SOUT data valid time (after SCK edge)
SOUT data valid
time from SCK
CPHA = 08
SOUT and SCK drive strength
SOUT data valid
time from SCK
CPHA = 18
SOUT and SCK drive strength
LVDS
LVDS
CC
15 pF
to 25 pF
differential
15 pF
to 25 pF
differential
SOUT data hold time (after SCK edge)
SOUT data hold
time after SCK
CPHA = 08
SOUT and SCK drive strength
SOUT data hold
time after SCK
CPHA = 18
SOUT and SCK drive strength
LVDS
LVDS
15 pF
to 25 pF
differential
15 pF
to 25 pF
differential
All timing values for output signals in this table are measured to 50% of the output voltage.
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
tSYS = 10 ns).
M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
Input timing assumes an input slew rate of 1 ns (10% – 90%) and LVDS differential voltage = ±100 mV.
P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically
set to 1.
MPC5777M Microcontroller Data Sheet, Rev. 6
102
NXP Semiconductors
Electrical characteristics
8
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Table 54. DSPI LVDS slave timing – full duplex – modified transfer format (MTFE = 0/1)1
Condition
#
Symbol
Unit
Pad drive
1
2
tSCK
tCSC
Value
Characteristic
CC SCK cycle time2
Load
Min
Max
—
—
—
62
2
—
—
16
—
ns
2
SR SS to SCK delay
ns
3
tASC
SR SCK to SS delay
—
—
16
—
ns
4
tSDC
CC SCK duty cycle2
—
—
30
—
ns
5
tA
CC Slave Access
Time2, 3, 4 (SS
active to SOUT
driven)
Very strong
25 pF
—
50
ns
Strong
50 pF
—
50
ns
Medium
50 pF
—
60
ns
CC Slave SOUT
Very strong
Disable Time 2, 3,
Strong
4(SS inactive to
SOUT High-Z or Medium
invalid)
25 pF
—
5
ns
50 pF
—
5
ns
50 pF
—
10
ns
6
tDIS
7
tSUI
CC Data setup time —
for inputs2
—
10
—
ns
8
tHI
CC Data hold time for —
inputs2
—
10
—
ns
9
tSUO
CC
SOUT Valid
Very strong
Time2, 3, 4 (after
Strong
SCK edge)
Medium
25 pF
—
30
ns
50 pF
—
30
ns
50 pF
—
50
ns
SOUT Hold
Very strong
Time2, 3, 4 (after
Strong
SCK edge)
Medium
25 pF
2.5
—
ns
50 pF
2.5
—
ns
50 pF
2.5
—
ns
10
tHO
CC
1
DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that
case only.
2 Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
3 All timing values for output signals in this table, are measured to 50% of the output voltage.
4 All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
103
Electrical characteristics
tCSC
tASC
PCSx
tSCK
tSDC
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
tSDC
tSUI
tHI
First Data
Data
Last Data
tSUO
SOUT
tHO
Data
First Data
Last Data
Figure 35. DSPI LVDS master mode – modified timing, CPHA = 0
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI
SIN
tHI
tHI
Data
First Data
tSUO
SOUT
First Data
Data
Last Data
tHO
Last Data
Figure 36. DSPI LVDS master mode – modified timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
104
NXP Semiconductors
Electrical characteristics
3.16.2.1.4
DSPI Master Mode – Output Only
Table 55. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock1,2
Condition
#
Symbol
Value
Characteristic
Unit
Pad drive
Load
Min
Max
25.0
—
ns
1
tSCK
CC SCK cycle time
2
tCSV
CC PCS valid after SCK3 Very strong
(SCK with 50 pF
Strong
differential load cap.)
25 pF
—
6.0
ns
50 pF
—
10.5
ns
CC PCS hold after SCK3 Very strong
(SCK with 50 pF
Strong
differential load cap.)
0 pF
–4.0
—
ns
0 pF
–4.0
—
ns
CC SCK duty cycle
LVDS
(SCK with 50 pF
differential load cap.)
15 pF
to 50 pF
differential
3
4
tCSH
tSDC
LVDS
15 pF
to 50 pF
differential
1/
2tSCK
–2
1/ t
2 SCK
+2
ns
SOUT data valid time (after SCK edge)
5
tSUO
CC SOUT data valid time SOUT and SCK drive strength
from SCK4
LVDS
15 pF
to 50 pF
differential
—
3.5
ns
–3.5
—
ns
SOUT data hold time (after SCK edge)
6
tHO
CC SOUT data hold time SOUT and SCK drive strength
after SCK4
LVDS
15 pF
to 50 pF
differential
1
All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS
with pad driver strength as defined. Timing may degrade for weaker output drivers.
2 TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
3
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of
DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.
4 SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock1,2
Value3
Condition
#
1
Symbol
tSCK
Characteristic
CC SCK cycle time
Unit
Pad drive4
Load (CL)
Min
Max
SCK drive strength
Very strong
25 pF
33.0
—
ns
Strong
50 pF
80.0
—
ns
Medium
50 pF
200.0
—
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
105
Electrical characteristics
Table 56. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1, CPOL = 0 or
1, continuous SCK clock1,2 (continued)
Value3
Condition
#
2
Symbol
tCSV
Characteristic
CC PCS valid after SCK5
Unit
Pad drive4
Load (CL)
4
tCSH
tSDC
CC PCS hold after SCK5
CC SCK duty cycle6
Max
SCK and PCS drive strength
Very strong
25 pF
7
—
ns
Strong
50 pF
8
—
ns
Medium
50 pF
16
—
ns
29
—
ns
PCS medium
PCS = 50 pF
and SCK strong SCK = 50 pF
3
Min
SCK and PCS drive strength
Very strong
PCS = 0 pF
SCK = 50 pF
–14
—
ns
Strong
PCS = 0 pF
SCK = 50 pF
–14
—
ns
Medium
PCS = 0 pF
SCK = 50 pF
–33
—
ns
PCS medium
PCS = 0 pF
and SCK strong SCK = 50 pF
–35
—
ns
SCK drive strength
Very strong
Strong
Medium
0 pF
1/ t
2 SCK
0 pF
1/ t
2 SCK
0 pF
1/ t
2 SCK
–2
1/
2tSCK
+2
ns
–2
1/
2tSCK
+2
ns
–5
1/
2tSCK
+5
ns
SOUT data valid time (after SCK edge)
9
tSUO
CC SOUT data valid time from
SCK
CPHA = 17
SOUT and SCK drive strength
Very strong
25 pF
—
7.0
ns
Strong
50 pF
—
8.0
ns
Medium
50 pF
—
16.0
ns
SOUT data hold time (after SCK edge)
10
tHO
CC SOUT data hold time after
SCK
CPHA = 17
SOUT and SCK drive strength
Very strong
25 pF
–7.7
—
ns
Strong
50 pF
–11.0
—
ns
Medium
50 pF
–15.0
—
ns
1
TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
3 All timing values for output signals in this table are measured to 50% of the output voltage.
4
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
5
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of
DSPI_CLKn. This timing value is due to pad delays and signal propagation delays.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
106
NXP Semiconductors
Electrical characteristics
6
tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
PCSx
tCSV
tSCK
tSDC
tCSH
SCK Output
(CPOL = 0)
tSUO
First Data
SOUT
tHO
Last Data
Data
Figure 37. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1, CHPA = 1
3.16.2.2
Slave Mode timing
Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)1
Condition
#
Symbol
Characteristic
Pad Drive
Load
Min
Max
Unit
1
tSCK
CC
SCK Cycle Time2
-
-
62
—
ns
2
tCSC
SR
SS to SCK Delay2
-
-
16
—
ns
SR
SCK to SS
Delay2
-
-
16
—
ns
SCK Duty
Cycle2
-
-
30
—
ns
Very
Strong
25 pF
—
50
ns
Strong
50 pF
—
50
ns
Medium
50 pF
—
60
ns
Very
Strong
25 pF
—
5
ns
Strong
50 pF
—
5
ns
3
4
5
6
tASC
tSDC
tA
tDIS
CC
CC
CC
Time2,3,4
Slave Access
(SS active to SOUT driven)
Slave SOUT Disable
Time2,3,4
(SS inactive to SOUT High-Z
or invalid)
Medium
50 pF
—
10
ns
Inputs2
—
—
10
—
ns
—
—
10
—
ns
9
tSUI
CC Data Setup Time for
10
tHI
CC Data Hold Time for Inputs2
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
107
Electrical characteristics
Table 57. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)1
Condition
#
11
12
Symbol
tSUO
tHO
Characteristic
CC
CC
Min
Max
Unit
25 pF
—
30
ns
Strong
50 pF
—
30
ns
Medium
50 pF
—
50
ns
Very
Strong
25 pF
2.5
—
ns
Strong
50 pF
2.5
—
ns
Medium
50 pF
2.5
—
ns
Pad Drive
Load
Very
Strong
SOUT Valid Time2,3,4
(after SCK edge)
SOUT Hold Time2,3,4
(after SCK edge)
1
DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for
that case only.
2 Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
3 All timing values for output signals in this table, are measured to 50% of the output voltage.
4 All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
tASC
tCSC
SS
tSCK
SCK Input
(CPOL=0)
tSDC
tSDC
SCK Input
(CPOL=1)
tSUO
tA
SOUT
First Data
Data
tSUI
SIN
First Data
tHO
tDIS
Last Data
tHI
Data
Last Data
Figure 38. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0
MPC5777M Microcontroller Data Sheet, Rev. 6
108
NXP Semiconductors
Electrical characteristics
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
tSUO
tA
SOUT
First Data
tSUI
SIN
tDIS
tHO
Data
Last Data
Data
Last Data
tHI
First Data
Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1
3.16.3
FEC timing
The FEC provides both MII and RMII interfaces in the 416 TEPBGA and 512 TEPBGA packages, and the MII and RMII
signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
3.16.3.1
MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.
Table 58. MII receive signal timing1
Value
Symbol
1
Characteristic
Unit
Min
Max
M1
CC RXD[3:0], RX_DV, RX_ER to RX_CLK setup
5
—
ns
M2
CC RX_CLK to RXD[3:0], RX_DV, RX_ER hold
5
—
ns
M3
CC RX_CLK pulse width high
35%
65%
RX_CLK period
M4
CC RX_CLK pulse width low
35%
65%
RX_CLK period
All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
109
Electrical characteristics
M3
RX_CLK (input)
M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 40. MII receive signal timing diagram
3.16.3.2
MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the MPC5777M Microcontroller Reference Manual’s Fast Ethernet Controller (FEC) chapter for details of this option
and how to enable it.
Table 59. MII transmit signal timing1
Value2
Symbol
1
2
Characteristic
Unit
Min
Max
M5
CC TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
5
—
ns
M6
CC TX_CLK to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
M7
CC TX_CLK pulse width high
35%
65%
TX_CLK period
M8
CC TX_CLK pulse width low
35%
65%
TX_CLK period
All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V.
Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
MPC5777M Microcontroller Data Sheet, Rev. 6
110
NXP Semiconductors
Electrical characteristics
M7
TX_CLK (input)
M5
M8
TXD[3:0] (outputs)
TX_EN
TX_ER
M6
Figure 41. MII transmit signal timing diagram
3.16.3.3
MII async inputs signal timing (CRS and COL)
Table 60. MII async inputs signal timing
Value
Symbol
Characteristic
M9
Unit
CC CRS, COL minimum pulse width
Min
Max
1.5
—
TX_CLK period
CRS, COL
M9
Figure 42. MII async inputs timing diagram
3.16.3.4
MII and RMII serial management channel timing (MDIO and MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 61. MII serial management channel timing1
Value2
Symbol
1
Unit
Characteristic
Min
Max
M10
CC MDC falling edge to MDIO output invalid (minimum
propagation delay)
0
—
ns
M11
CC MDC falling edge to MDIO output valid (max prop
delay)
—
25
ns
M12
CC MDIO (input) to MDC rising edge setup
10
—
ns
M13
CC MDIO (input) to MDC rising edge hold
0
—
ns
M14
CC MDC pulse width high
40%
60%
MDC period
M15
CC MDC pulse width low
40%
60%
MDC period
All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and
2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
111
Electrical characteristics
2
Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Figure 43. MII serial management channel timing diagram
3.16.3.5
RMII receive signal timing (RXD[1:0], CRS_DV)
The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of
the REF_CLK frequency.
Table 62. RMII receive signal timing1
Value
Symbol
1
Characteristic
Unit
Min
Max
R1
CC RXD[1:0], CRS_DV to REF_CLK setup
4
—
ns
R2
CC REF_CLK to RXD[1:0], CRS_DV hold
2
—
ns
R3
CC REF_CLK pulse width high
35%
65%
REF_CLK period
R4
CC REF_CLK pulse width low
35%
65%
REF_CLK period
All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
MPC5777M Microcontroller Data Sheet, Rev. 6
112
NXP Semiconductors
Electrical characteristics
R3
REF_CLK (input)
R4
RXD[1:0] (inputs)
CRS_DV
R2
R1
Figure 44. RMII receive signal timing diagram
3.16.3.6
RMII transmit signal timing (TXD[1:0], TX_EN)
The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency
requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of
the REF_CLK frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK,
and the timing is the same in either case. These options allows the use of non-compliant RMII PHYs.
Table 63. RMII transmit signal timing1, 2
Value3
Symbol
Unit
Characteristic
Min
Max
R5
CC REF_CLK to TXD[1:0], TX_EN invalid
2
—
ns
R6
CC REF_CLK to TXD[1:0], TX_EN valid
—
16
ns
R7
CC REF_CLK pulse width high
35%
65%
REF_CLK period
R8
CC REF_CLK pulse width low
35%
65%
REF_CLK period
1
RMII timing is valid only up to a maximum of 150 oC junction temperature.
All timing specifications are referenced for TTL or CMOS input levels for REF_CLK to the valid output levels, 0.8 V
and 2.0 V.
3
Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
2
R7
REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN
R6
Figure 45. RMII transmit signal timing diagram
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
113
Electrical characteristics
3.16.4
FlexRay timing
This section provides the FlexRay Interface timing characteristics for the input and output signals.
These are recommended numbers as per the FlexRay EPL v3.0 specification.
3.16.4.1
TxEN
TxEN
80 %
20 %
dCCTxENFALL
dCCTxENRISE
Figure 46. TxEN signal
Table 64. TxEN output characteristics1
Value
Symbol
Characteristic
Unit
Min
Max
dCCTxENRISE25 CC Rise time of TxEN signal at CC
—
9
ns
dCCTxENFALL25 CC Fall time of TxEN signal at CC
—
9
ns
1
dCCTxEN01
CC Sum of delay between Clk to Q of the last FF and the final output buffer,
rising edge
—
25
ns
dCCTxEN10
CC Sum of delay between Clk to Q of the last FF and the final output buffer,
falling edge
—
25
ns
TxEN pin load maximum 25 pF
MPC5777M Microcontroller Data Sheet, Rev. 6
114
NXP Semiconductors
Electrical characteristics
PE_Clk
TxEN
dCCTxEN10
dCCTxEN01
Figure 47. TxEN signal propagation delays
3.16.4.2
TxD
TxD
dCCTxD50%
80 %
50 %
20 %
dCCTxDRISE
dCCTxDFALL
Figure 48. TxD signal
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
115
Electrical characteristics
Table 65. TxD output characteristics1,2
Value
Symbol
dCCTxAsym
Characteristic
Unit
CC Asymmetry of sending CC at 25 pF load
(= dCCTxD50% 100 ns)
dCCTxDRISE25+dCCTxDFALL25 CC Sum of Rise and Fall time of TxD signal at the output
pin3,4
1
2
3
4
5
6
Min
Max
–2.45
2.45
ns
—
95
ns
—
96
dCCTxD01
CC Sum of delay between Clk to Q of the last FF and the
final output buffer, rising edge
—
25
ns
dCCTxD10
CC Sum of delay between Clk to Q of the last FF and the
final output buffer, falling edge
—
25
ns
TxD pin load maximum 25 pF
Specifications valid according to FlexRay EPL 3.0.1 standard with 20%–80% levels and a 10pF load at the end of a
50 Ohm, 1 ns stripline. Please refer to the Very Strong I/O pad specifications.
Pad configured as VERY STRONG
Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire
temperature range of the device has been taken into account.
VDD_HV_IO = 5.0 V ± 10%, Transmission line Z = 50 ohms, tdelay = 1 ns, CL = 10 pF
VDD_HV_IO = 3.3 V ± 10%, Transmission line Z = 50 ohms, tdelay = 0.6 ns, CL = 10 pF
PE_Clk*
TxD
dCCTxD10
dCCTxD01
* FlexRay Protocol Engine Clock
Figure 49. TxD Signal propagation delays
MPC5777M Microcontroller Data Sheet, Rev. 6
116
NXP Semiconductors
Electrical characteristics
3.16.4.3
RxD
Table 66. RxD input characteristics1
Value
Symbol
Unit
Min
Max
CC Input capacitance on RxD pin
—
7
pF
uCCLogic_1
CC Threshold for detecting logic high
35
70
%
uCCLogic_0
CC Threshold for detecting logic low
30
65
%
dCCRxD01
CC Sum of delay from actual input to the D input of the first
FF, rising edge
—
10
ns
dCCRxD10
CC Sum of delay from actual input to the D input of the first
FF, falling edge
—
10
ns
dCCRxAsymAccept15
CC Acceptance of asymmetry at receiving CC with 15 pF
load
–31.5
44
ns
dCCRxAsymAccept25
CC Acceptance of asymmetry at receiving CC with 25 pF
load
–30.5
43
ns
C_CCRxD
1
Characteristic
FlexRay RxD timing is valid for Automotive input levels with hysteresis enabled (hysteresis permanently enabled in
Automotive input levels) and CMOS input levels with hysteresis disabled, 4.5 V VDD_HV_IO 5.5 V for both cases.
3.16.5
PSI5 timing
The following table describes the PSI5 timing.
Table 67. PSI5 timing
Value
Symbol
1
Parameter
Unit
Min
Max
tMSG_DLY
CC Delay from last bit of frame (CRC0) to assertion
of new message received interrupt
—
3
µs
tSYNC_DLY
CC Delay from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin
—
2
µs
tMSG_JIT
CC Delay jitter from last bit of frame (CRC0) to
assertion of new message received interrupt
—
1
cycles1
tSYNC_JIT
CC Delay jitter from internal sync pulse to sync pulse
trigger at the SDOUT_PSI5_n pin
—
±(1 PSI5_1µs_CLK +
1 PBRIDGEn_CLK)
cycles
Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.
3.16.6
UART timing
UART channel frequency support is shown in the following table.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
117
Electrical characteristics
Table 68. UART frequency support
LINFlexD clock frequency
LIN_CLK (MHz)
Oversampling rate
80
16
Max usable frequency
(Mbaud)
Voting scheme
3:1 majority voting
5
8
6
5
10
Limited voting on one
sample with configurable
sampling point
4
100
16
5
3:1 majority voting
6.25
12.5
Limited voting on one
sample with configurable
sampling point
4
3.16.7
16
20
8
6
13.33
16.67
20
25
External Bus Interface (EBI) Timing
Table 69. Bus Operation Timing1
66.7 MHz (Ext. Bus Freq)2 3
Spec
Characteristic
Symbol
Unit
Min
1
CLKOUT Period4
2
CLKOUT Duty Cycle
Max
tC
15.15
—
ns
tCDC
45%
55%
tC
ns
3
CLKOUT Rise Time
tCRT
—
—5
4
CLKOUT Fall Time
tCFT
—
—5
ns
5
CLKOUT Posedge to Output Signal Invalid or High Z
(Hold Time)6
tCOH
1.0
—
ns
tCOV
—
8.0
ns
ADDR[12:31]
ADDR[8:11]/WE[0:3]/BE[0:3]
BDIP
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
6
CLKOUT Posedge to Output Signal Valid (Output
Delay)7,8
ADDR[12:31]
ADDR[8:11]/WE[0:3]/BE[0:3]
BDIP
CS[0:3]
DATA[0:31]
OE
RD_WR
TS
MPC5777M Microcontroller Data Sheet, Rev. 6
118
NXP Semiconductors
Electrical characteristics
Table 69. Bus Operation Timing1 (continued)
66.7 MHz (Ext. Bus Freq)2 3
Spec
7
Characteristic
Input Signal Valid to CLKOUT Posedge (Setup Time)
Symbol
Unit
Min
Max
tCIS
7.0
—
ns
tCIH
1.0
—
ns
DATA[0:31]
8
CLKOUT Posedge to Input Signal Invalid (Hold Time)
DATA[0:31]
1
2
3
4
5
6
7
8
EBI timing specified at VDD_HV_IO_EBI and VDD_HV_IO_FLEXE = 3.0 V to 3.6 V, TA = TL to TH, and CL = 30 pF with
DSC = 0b10 for ADDR/CTRL and DSC = 0b11 for CLKOUT/DATA.
Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including PLL jitter.
Depending on the internal bus speed, set the CGM_SC_DC4 register bits correctly not to exceed maximum
external bus frequency. The maximum external bus frequency is 66.7 MHz.
Signals are measured at 50% VDD_HV_IO_EBI or VDD_HV_IO_FLEXE.
Refer to Fast pad timing in Table 18.
CLKOUT may be required at the highest drive strength in order to meet the hold time specification.
One wait state must be added for all write accesses to external memories at the maximum external bus frequency.
One wait state must be added to the outut signal valid delay for external writes.
VOH_F
VDD_HV_IO_EBI / 2
D_CLKOUT
VOL_F
3
2
2
4
1
Figure 50. D_CLKOUT Timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
119
Electrical characteristics
D_CLKOUT
VDD_HV_IO_EBI / 2
6
5
5
Output
Bus
VDD_HV_IO_EBI / 2
6
5
5
Output
Signal
VDD_HV_IO_EBI / 2
6
Output
Signal
VDD_HV_IO_EBI / 2
Figure 51. Synchronous Output Timing
MPC5777M Microcontroller Data Sheet, Rev. 6
120
NXP Semiconductors
Electrical characteristics
D_CLKOUT
VDD_HV_IO_EBI / 2
7
8
VDD_HV_IO_EBI / 2
Input
Bus
7
8
Input
Signal
VDD_HV_IO_EBI / 2
Figure 52. Synchronous Input Timing
3.16.8
I2C timing
The I2C AC timing specifications are provided in the following tables.
Table 70. I2C input timing specifications — SCL and SDA1
Value
No.
Symbol
Parameter
Unit
Min
Max
1
—
CC Start condition hold time
2
—
PER_CLK Cycle2
2
—
CC Clock low time
8
—
PER_CLK Cycle
3
—
CC Bus free time between Start and Stop condition
4.7
—
µs
4
—
CC Data hold time
0.0
—
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
121
Electrical characteristics
Table 70. I2C input timing specifications — SCL and SDA1 (continued)
Value
No.
1
Symbol
Parameter
Unit
Min
Max
5
—
CC Clock high time
4
—
PER_CLK Cycle
6
—
CC Data setup time
0.0
—
ns
7
—
CC Start condition setup time (for repeated start condition only)
2
—
PER_CLK Cycle
8
—
CC Stop condition setup time
2
—
PER_CLK Cycle
2
I C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower
than 1 ns (10% – 90%).
2
PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in
the device reference manual for more detail.
Table 71. I2C output timing specifications — SCL and SDA1,2 ,3,4
Value
No.
Symbol
Parameter
Unit
Min
Max
1
—
CC Start condition hold time
6
—
PER_CLK Cycle5
2
—
CC Clock low time
10
—
PER_CLK Cycle
3
—
CC Bus free time between Start and Stop condition
4.7
—
µs
4
—
CC Data hold time
7
—
PER_CLK Cycle
5
—
CC Clock high time
10
—
PER_CLK Cycle
6
—
CC Data setup time
2
—
PER_CLK Cycle
7
—
CC Start condition setup time (for repeated start condition only)
20
—
PER_CLK Cycle
8
—
CC Stop condition setup time
10
—
PER_CLK Cycle
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3 Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and
may cause incorrect operation.
4 Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum
output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL
low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD
register.
5 PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter
in the device reference manual for more detail.
2
MPC5777M Microcontroller Data Sheet, Rev. 6
122
NXP Semiconductors
Electrical characteristics
2
5
SCL
4
1
8
6
3
7
SDA
Figure 53. I2C input/output timing
3.16.9
GPIO delay timing
The GPIO delay timing specification is provided in the following table.
Table 72. GPIO delay timing
Value
Symbol
IO_delay
Parameter
CC
Unit
Delay from SIUL2 MSCR register bit update to pad function
enable at the input of the I/O pad
Min
Max
5
25
ns
3.16.10 Package characteristics
The following table lists the case numbers for each available package for the device.
Table 73. Package case numbers
Package Type
Device Type
Case Outline Number
416TEPBGA
Production
98ARE10523D
416TEPBGA
Emulation
98ASA00493D
512TEPBGA
Production or Emulation
98ASA00262D
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
123
Electrical characteristics
3.17
416 TEPBGA (production) case drawing
Figure 54. 416 TEPBGA (production) package mechanical drawing (Sheet 1 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
124
NXP Semiconductors
Electrical characteristics
Figure 55. 416 TEPBGA (production) package mechanical drawing (Sheet 2 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
125
Electrical characteristics
3.18
416 TEPBGA (emulation) case drawing
Figure 56. 416 TEPBGA (emulation) package mechanical drawing (Sheet 1 of 3)
MPC5777M Microcontroller Data Sheet, Rev. 6
126
NXP Semiconductors
Electrical characteristics
Figure 57. 416 TEPBGA (emulation) package mechanical drawing (Sheet 2 of 3)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
127
Electrical characteristics
Figure 58. 416 TEPBGA (emulation) package mechanical drawing (Sheet 3 of 3)
MPC5777M Microcontroller Data Sheet, Rev. 6
128
NXP Semiconductors
Electrical characteristics
3.19
512 TEPBGA case drawing
2
Figure 59. 512 TEPBGA package mechanical drawing (Sheet 1 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
129
Electrical characteristics
Figure 60. 512 TEPBGA package mechanical drawing (Sheet 2 of 2)
MPC5777M Microcontroller Data Sheet, Rev. 6
130
NXP Semiconductors
Electrical characteristics
3.20
Thermal characteristics
The following tables describe the thermal characteristics of the device.
.
Table 74. Thermal characteristics
Symbol
RJA
RJMA
1
Parameter
Conditions
416
512
Value Value
Junction-to-Ambient, Natural
Convection
Single Layer board (1s)
25
24.1
Four layer board (2s2p)
17.2
16.8
Junction-to-Moving-Air, Ambient
@200 ft/min., single layer
board (1s)
18.1
16.6
@200 ft/min., four layer board
(2s2p)
13.4
12.4
Unit
Notes
°C/W
1,2
1,2,3
°C/W
1,3
1,3
RJB
Junction-to-board
—
8.6
8.8
°C/W
4
RJC
Junction-to-case
—
5.0
5.0
°C/W
5
JT
Junction-to-package top
Natural convection
0.2
0.2
°C/W
6
JB
Junction-to-package bottom/solder
balls
Natural convection
3.5
3.0
°C/W
7
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on
the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the
junction temperature per JEDEC JESD51-2.
Thermal characterization parameter indicating the temperature difference between package bottom center and
the junction temperature per JEDEC JESD51-12.
2
3
4
5
6
7
3.20.1
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RJA * PD)
Eqn. 1
where:
TA = ambient temperature for the package (oC)
RJA = junction-to-ambient thermal resistance (oC/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for
estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a
four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance
is not a constant. The thermal resistance depends on the:
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
131
Electrical characteristics
•
•
•
•
Construction of the application board (number of planes)
Effective size of the board which cools the component
Quality of the thermal and electrical connections to the planes
Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package
to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance
between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.
As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit
board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:
•
•
•
One oz. (35 micron nominal thickness) internal planes
Components are well separated
Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the
ambient temperature varies widely within the application. For many natural convection and especially closed box applications,
the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the
device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TB + (RJB * PD)
Eqn. 2
where:
TB = board temperature for the package perimeter (oC)
RJB = junction-to-board thermal resistance (oC/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable
if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal
resistance:
RJA = RJC + RCA
Eqn. 3
where:
RJA = junction-to-ambient thermal resistance (oC/W)
RJC = junction-to-case thermal resistance (oC/W)
RCA = case to ambient thermal resistance (oC/W)
RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the
case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the
mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding
the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat
sink to ambient. For most packages, a better model is required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the
junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a
substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the
thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple
estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be
generated upon request.
MPC5777M Microcontroller Data Sheet, Rev. 6
132
NXP Semiconductors
Ordering information
To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization
parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using
the following equation:
TJ = TT + (JT x PD)
Eqn. 4
where:
TT = thermocouple temperature on top of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests
on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from
the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling
effects of the thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter
(JPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed
pad) using the following equation:
TJ = TB + (JPB x PD)
Eqn. 5
where:
TT = thermocouple temperature on bottom of the package (oC)
JT = thermal characterization parameter (oC/W)
PD = power dissipation in the package (W)
4
Ordering information
Table 75 shows the orderable part numbers for the MPC5777M series.
Table 75. Orderable part number summary
Part Number
Device Type1,2
Package
PPC5777MK0MVU8B
Sample
416 TEPBGA
PPC5777MK0MVA8B
Sample
512 TEPBGA
PPC5777M2K0MVU8B
Sample ED
416 TEPBGA
PPC5777M2K0MVA8B
Sample ED
512 TEPBGA
SPC5777MK0MVU8
Production PD
416 TEPBGA
SPC5777MK0MVU8R
Production PD
416 TEPBGA
w/Tape and Reel
SPC5777MK0MVA8
Production PD
512 TEPBGA
SPC5777MK0MVA8R
Production PD
512 TEPBGA
w/Tape and Reel
1
“PD” refers to a production device, orderable in quantity
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
133
Ordering information
2
“ED" refers to an emulation device, orderable in limited quantities. An emulation
device (ED) is for use during system development only and is not to be used in
production. An ED is a Production PD chip combined with a companion chip to form
an Emulation and Debug Device (ED) and includes additional RAM memory and
debug features. EDs are provided “as is" without warranty of any kind. In the event
of a suspected ED failure, NXP agrees to exchange the suspected failing ED from
the customer at no additional charge; however, NXP will not analyze ED returns.
MPC5777M Microcontroller Data Sheet, Rev. 6
134
NXP Semiconductors
Ordering information
Example code:
PC
M
4
57
6
M
Q
F0
M
xx
5
R
MC Qualification Status
Power Architecture Core
Automotive Platform
Processor Core
Flash Memory Size
Product/Family Name
Miscellaneous (Optional)
Fab and Mask Revision
Temperature
Package Code
Maximum Frequency
Tape or Reel
Qualification Status
MPC = Full specification qualified
SPC = Mask specification qualified
PPC = Engineering samples
Automotive Platform
55 = PPC in 130 nm
56 = PPC in 90 nm
57 = PPC in 55 nm
Processor Core
0 = e200z0
1 = e200z1
2 = e200z2
3 = e200z3
4 = e200z4
5 = e200z6 without VLE
6 = e200z6
7 = e200z7
Miscellaneous
D = Dual Core
T = Triple Core
Q = Quad Core
S = Single Core
2 = Emulation Device
Flash Memory Size
z0, z2
z4
z7
1
256 KB
1 MB
1 MB
2
384 KB
1.5 MB
1.5 MB
3
512 KB
2 MB
2 MB
4
768 KB
2.5 MB
3 MB
5
1 MB
3 MB
4 MB
6
1.5 MB
4 MB
6 MB
7
2 MB
5 MB
8 MB
8
2.5 MB
6 MB
12 MB
9
3 MB
8 MB
16 MB
Temperature Specification
C = –40 °C to 85 °C
V = –40 °C to 105 °C
M = –40 °C to 125 °C
K = –40 °C to 135 °C
Fab and Mask Revision
F = ATMC
K = TSMC
0 = Revision
Package Code
ZP = 416 PBGA SnPb
VA = 416 PBGA Pb-free
VA = 512 TEPBGA Pb-free
VU = 416 TEPBGA Pb-free
VF = 208 MAPBGA SnPb
VM = 208 MAPBGA Pb-free
ZQ = 324 PBGA SnPb
VZ = 324 PBGA Pb-free
LQ = 144 LQFP Pb-free
LU = 176 LQFP Pb-free
KU = 176 LQFP ep Pb-free
MP = 292 MAPBGA Pb-free
OU = 216 FQ (176 leads)
Maximum Frequency
0 = 64 MHz
1 = 80 MHz
2 = 120 MHz
3 = 150 MHz
4 = 160 MHz
5 = 200 MHz
8 = 300 MHz
Suffix
A = cut2.0 revision
T = Tape
R = Reel
Figure 61. Product code structure
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
135
Document revision history
5
Document revision history
Table 76 summarizes revisions to this document.
Table 76. Revision history
Revision
Date
1
12/2011
2
4/2013
Description of changes
Initial release
Throughout
• Data sheet now includes both KGD (TJ165 °C) and non-KGD (TJ150 °C)
specifications
• The interfaces and components formerly including the name “DigRF” have been
renamed to “LFAST.”
Introduction
• Changed on-chip general-purpose SRAM to 404 KB (was 384 KB)
• Changed item describing Boot Assist Flash support to “Boot Assist Module (BAM)
supports factory programming using serial bootload through ’UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be: UART/LIN, CAN, FlexRay”
Table 1 (Family comparison):
• Changed feature from “Zipwire/LFAST7 bus” to “Zipwire (SIPI / LFAST7) Interprocessor
Communication Interface”
Figure 1 (Block diagram):
• Changed SRAM from 320 to 340 KB
• Changed figure to include “Triple INTC”
• Added “LFAST Switch” block to Computational Shell
• Added “Debug SIPI” block to the Peripheral Domain 50 MHz Concentrator
Figure 2 (Periphery allocation):
• Added PSI5_S_0 module
• Changed “Peripheral Cluster A” to “Peripheral Cluster B” and “Peripheral Cluster B” to
“Peripheral Cluster A”
• Added PSI5_S_0 module
Package pinouts and signal descriptions
Figure 3 (292-ball BGA production device pinout (top view))
Figure 4 (292-ball BGA emulation device pinout (top view))
Figure 5 (512-ball BGA production device pinout (top view))
Figure 8 (512-ball BGA emulation device pinout (top view)):
• Changed “VDD_HV_PMC_BYP” to “VDD_HV_IO_MAIN”
Table 2 (Power supply and reference pins):
• Removed VDD_HV_PMC_BYP (PMC Voltage Supply Bypass Capacitor) row.
Table 3 (System pins):
• Clarification of TESTMODE pin definition: “TESTMODE pull-down is implemented to
prevent the device from entering TESTMODE. It is recommended to connect the
TESTMODE pin to VSS_HV_IO on the board. The value of the TESTMODE pin is
latched at the negation of reset and has no affect afterward. The device will not exit
reset with the TESTMODE pin asserted during power-up.” (Added detail regarding
when TESTMODE pin value is latched and that device will not exit reset when pin is
asserted during power-up)
MPC5777M Microcontroller Data Sheet, Rev. 6
136
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Package pinouts and signal descriptions (con’t)
Table 4 (LVDS pin descriptions):
• In SIPI/LFAST, Differential DSPI2, and Differential DSPI 5 groups, changed port pin
“PF[7]” to “PD[7]”
• Changed the polarity of the signal assigned to several port pins. For example, the
signal for port pin PD[7] has been changed to “SIPI_RXP” (was SIPI_RXN) and
“Interprocessor Bus LFAST, LVDS Receive Positive Terminal” (was “Interprocessor
Bus LFAST, LVDS Receive Negative Terminal”). This change affects port pins PD[7],
PF[13], PA[14], PD[6], PA[7], PA[8], PD[2], PD[3], PD[0], PD[1], PF[10], PF[9], PF[11],
PF[12], PQ[8], PQ[9], PQ[10], PQ[11], PI[14], and PI[15].
• Added package ball locations
Electrical characteristics—Miscellaneous
Section 3, Electrical characteristics:
• Thermal characteristics section has been moved to Package characteristics section.
• Following note removed: “All parameter values in this document are tested with
nominal supply voltage values (VDD_LV = 1.25 V, VDD_HV = 5.0 V ± 10%,
VDD_HV_IO = 5.0 V ± 10% or 3.3 V ± 10%) and TA = –40 to 125 °C unless otherwise
specified.”. Operating conditions will appear elsewhere in the data sheet.
• Added VDD_HV_IO_FLEX before VDD_HV_FLA in the second note on the page
Electrical characteristics—Absolute maximum ratings
Table 6 (Absolute maximum ratings):
• IMAXD specification now given by pad type (Medium, Strong, and Very Strong)
• IMAXA specification deleted.
• New specification: IINJD (Maximum DC injection current for digital pad)
• New specification: IINJA (Maximum DC injection current for analog pad)
• New specification: IMAXSEG (Maximum current per power segment)
• New specification: VFERS (Flash erase acceleration supply)
• New specification: VDD_HV_IO_EBI (External Bus Interface supply)
• Changed “Emulation module supply” to “BD supply” in the VDD_LV_BD – BDD_LV row
• Maximum junction temperature changed from 125 °C to 165 °C in cumulative time
limits on voltage levels for VDD_LV and VDD_LV_BD
• Footnote added to VFERS: VFERS is a factory test supply pin that is used to reduce the
erase time of the flash. It is only available in bare die devices. There is no VFERS pin in
the packaged devices. The VFERS supply pad can be bonded to ground (VSS_HV) to
disable, or connected to 5.0 V ± 5% to use the flash erase acceleration feature. Pad
can be left at 5 V ± 5% in normal operation.
• Footnote added to VIN: “The maximum input voltage on an I/O pin tracks with the
associated I/O supply maximum. For the injection current condition on a pin, the
voltage will be equal to the supply plus the voltage drop across the internal ESD diode
from I/O pin to supply. The diode voltage varies greatly across process and
temperature, but a value of 0.3V can be used for nominal calculations.“
• Footnote VDD_LV changed: “1.32 – 1.375 V range allowed periodically for supply with
sinusoidal shape and average supply value below 1.288 V at maximum TJ = 165 °C”
(was 1.275)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
137
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Operating conditions
Table 8 (Device operating conditions)
• Changed VSTBY_BO minimum from 0.7V to 0.8V.
Electrical characteristics—DC electrical specifications
Table 10 (DC electrical specifications)
• Replaced table; significant changes throughout, including parameter names,
descriptions, and values.
MPC5777M Microcontroller Data Sheet, Rev. 6
138
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—I/O pad specification
Table 11 (I/O pad specification descriptions)
• Revised “Very strong configuration” description to include EBI data bus.
• Added “EBI configuration” row.
• Changed “Input only pads” description to “These pads, which ensure low input leakage,
are associated with the ADC channels” (was “These pads are associated with the ADC
channels and 32 kHz low power external crystal oscillator providing low input leakage”)
• Changed note following table to “Each I/O pin on the device supports specific drive
configurations. See the signal description table in the device reference manual for the
available drive configurations for each I/O pin” (was “All pads can be configured in all
configurations”)
Table 12 (I/O input DC electrical characteristics)
• New specification: VDRFTTTL (Input VIL/VIH temperature drift TTL)
• New specification: VDRFTAUT (Input VIL/VIH temperature drift)
• New specification: VDRFTCMOS (Input VIL/VIH temperature drift CMOS)
• Conditions for VIHCMOS_H, VIHCMOS, VILCMOS_H, VILCMOS, VHYSCMOS, VDRFTCMOS are
now 3.0 V < VDD_HV_IO < 3.6 V and 4.5 V < VDD_HV_IO < 5.5 V (was 2.7 V < VDD_HV_IO
< 3.6 V and 4.0 V < VDD_HV_IO < 5.5 V)
• New specification: ILKG_MED (Digital input leakage for MEDIUM pad)
• Footnotes give formulas for approximation of the variation of the minimum value with
supply of VIHAUT and VHYSAUT (previously stated formulas approximated upper value
instead of minimum value). Changed formula for VIHAUT to “0.69 x VDD_HV_IO” (was
“0.69 supply”). Changed formula for VHYSAUT to “0.11 x VDD_HV_IO” (was “0.11
supply”).
• Footnote gives formula for approximation of the variation of the maximum value with
supply of VILAUT (previously stated formula approximated upper value instead of
maximum value). Changed formula for VILAUT to “0.49 x VDD_HV_IO” (was “0.49
supply”).
• Added footnote: “In a 1 ms period, assuming stable voltage and a temperature
variation of ±30°C, VIL/VIH shift is within ±50 mV.”
• VHYSAUT conditions column: replaced dash with 4.5V < VDD_HV_IO < 5.5V
• CIN row, changed GPIO input pins conditions Max value from “10” to 7pF and EBI input
pins Max value from “8” to “7pF”
Table 13 (I/O pull-up/pull-down DC electrical characteristics)
• Significant revisions throughout this table, including new conditions for IWPU and
IWPD
• New specification: RWPU (Weak pull-up resistance)
• New specification: RWPD (Weak pull-down resistance)
• New figure: Figure 8 (Weak pull-up electrical characteristics definition)
• New figure: Figure 18 (I/O output DC electrical characteristics definition)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
139
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—I/O pad specification (con’t)
Table 14 (WEAK configuration output buffer electrical characteristics)
• ROH_W (PMOS output impedance weak configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOH < 0.5 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• ROL_W (NMOS output impedance WEAK configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOL < 0.5 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• tTR_W (Transition time output pin WEAK configuration) conditions changed for CL = 25
pF, CL = 50 pF, CL = 200 pF: 4.5 V < VDD_HV_IO < 5.9 V (was 4.0 V < VDD_HV_IO <
5.9 V)
• Specification change: tTR_W, CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V max value is
820 ns (was 1000)
• Specification change: tTR_W, CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 50 ns
(was TBD)
• Specification change: tTR_W, CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 100 ns
(was TBD)
• Specification change: tTR_W, CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is
350 ns (was TBD) and max value is 1050 ns (was TBD)
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
Table 15 (MEDIUM configuration output buffer electrical characteristics)
• ROH_M (PMOS output impedance MEDIUM configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOH < 2 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• ROL_M (NMOS output impedance MEDIUM configuration) condition is now 4.5 V <
VDD_HV_IO < 5.9 V, Push pull IOL < 2 mA (was 4.0 V < VDD_HV_IO < 5.9 V). Removed
3.0 V < VDD_HV_IO < 4.0 V condition.
• tTR_M (Transition time output pin MEDIUM configuration) conditions changed for CL =
25 pF, CL = 50 pF, CL = 200 pF: 4.5 V < VDD_HV_IO < 5.9 V (was 4.0 V < VDD_HV_IO
< 5.9 V)
• Specification change: tTR_M, CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V max value is
200 ns (was 240)
• Specification change: tTR_M, CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 12 ns
(was TBD)
• Specification change: tTR_M, CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 24 ns
(was TBD)
• Specification change: tTR_M, CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 70 ns
(was TBD) and max value is 300 ns (was TBD)
• New specification: IDCMAX_M (Maximum DC current)
• New specification: tSKEW_M(Difference between rise and fall time)
• Formula given for transition time typical value changed to: tTR_M(ns) = 5.6 ns+CL(pF)
x 1.11 ns/pF (when 0 pF < CL < 50 pF) and tTR_M(ns) = 13 ns+CL(pF) x 0.96 ns/pF
(when 50 pF < CL < 200 pF)
• Footnote added: ROX_M(min) may decrease by 10% at TJ = 165 °C.
• Footnote added: ROX_M(max) may increase by 10% at TJ = 165 °C.
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
MPC5777M Microcontroller Data Sheet, Rev. 6
140
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—I/O pad specification (con’t)
Table 16 (STRONG configuration output buffer electrical characteristics)
• New specification: IDCMAX_S (Maximum DC current)
• Renamed: ROH_F (PMOS output impedance STRONG configuration) is now ROH_S
• Renamed: ROL_F (NMOS output impedance STRONG configuration) is now ROL_S
• Renamed: fMAX_M (Output frequency STRONG configuration) is now fMAX_S
• ROH_S condition is now 4.5 V < VDD_HV_IO < 5.9 V, Push pull IOH < 8 mA (was 4.0 V <
VDD_HV_IO < 5.9 V). Removed 3.0 V < VDD_HV_IO < 4.0 V condition.
• ROL_S condition is now 4.5 V < VDD_HV_IO < 5.9 V, Push pull IOH < 8 mA (was 4.0 V <
VDD_HV_IO < 5.9 V). Removed 3.0 V < VDD_HV_IO < 4.0 V condition.
• tTR_S conditions changed for CL = 25 pF, CL = 50 pF, CL = 200 pF: 4.5 V < VDD_HV_IO
< 5.9 V (was 4.0 V < VDD_HV_IO < 5.9 V)
• Specification change: fMAX_S, CL = 200 pF max value is 5 MHz (was “—”)
• Specification change: tTR_S, CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 4 ns
(was TBD) and max value is 15 ns (was TBD)
• Specification change: tTR_S, CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 6 ns
(was TBD) and max value is 27 ns (was TBD)
• Specification change: tTR_S, CL = 200 pF, 3.0 V < VDD_HV_IO < 3.6 V min value is 20 ns
(was TBD) and max value is 83 ns (was TBD)
• Footnote added: ROX_S(min) may decrease by 10% at TJ = 165 °C.
• Footnote added: ROX_S(max) may increase by 10% at TJ = 165 °C.
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
Table 17 (VERY STRONG configuration output buffer electrical characteristics)
• New specification: IDCMAX_M (Maximum DC current)
• New condition added to tTR_V: VDD_HV_IO = 5.0 V ± 10%, CL = 200 pF
• Footnote added: ROX_V(min) may decrease by 10% at TJ = 165 °C.
• Footnote added: ROX_V(max) may increase by 10% at TJ = 165 °C.
• Conditions column heading, added footnote: All VDD_HV_IO conditions for 4.5V to
5.9V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
Table 18 (EBI pad output electrical specification)
• Replaced this table “EBI output driver electrical characteristics” with new table “EBI pad
electrical specification”
Electrical characteristics—I/O pad current specification
New section
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
Section 3.8, Reset pad (PORST, ESR0) electrical characteristics:
• Added note on PORST and active control
Figure 11 (Noise filtering on reset signal):
• Replaced; significant detail added
• Clarification: VESR0 is also described by VPORST behavior shown in illustration.
• Figure prefaced with more detailed PORST description.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
141
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Reset pad (PORST, ESR0) electrical characteristics
(con’t)
Table 20 (Reset electrical characteristics)
• New specification: WFNMI (ESR1 input filtered pulse)
• New specification: WNFNMI (ESR1 input not filtered pulse)
• New specification: VDD_POR (Minimum supply for strong pull-down activation)
• IOL_R condition changed (VDD_HV_IO = 1.0 V is now VDD_HV_IO = VDD_POR, VDD_HV_IO
= 4.0 V is now 3.0 V < VDD_HV_IO < 5.5 V, and VOL = 0.35*VDD_HV_IO is now VOL >
0.9 V)
• Specification change: IOL_R (3.0 V < VDD_HV_IO < 5.5 V, VOL > 0.9 V) min value is
11 mA (was 15)
• Added footnote: An external 4.7 K pull-up resistor is recommended to be used with
the PORST and ESR0 pins for fast negation of the signals.
• Added footnote: IOL_R applies to both PORST and ESR0: Strong pull-down is active on
PHASE0 for PORST. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and
the beginning of PHASE3 for ESR0.
• Added note on reset signal slew rate restrictions
Electrical characteristics—Oscillator and FMPLL
Section 3.12, Oscillator and FMPLL
Table 21 (PLL0 electrical characteristics)
• New specification: fPLL0PHI0 (PLL0 output frequency)
• Specification change: tPLL0LOCK (PLL0 lock time) maximum is 100 µs (was
100–110 µs)
• PLL0LTJ specification parameter and conditions change: “PLL0 output long term jitter,
fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz” (was “PLL0 output long term
jitter, fPLL0IN = 20 MHz (resonator)”). Conditions significantly revised.
• Revised footnote: “VDD_LV noise due to application in the range VDD_LV = 1.25 V ±5%
with frequency below PLL bandwidth (40 KHz) will be filtered” (was “1.25 V ±5%
application noise below 40kHz at VDD_LV pin”)
• Removed “F” from “FXOSC” in footnote 1
Table 22 (PLL1 electrical characteristics)
• Specification change: fPLL1PHI (PLL1 output clock PHI) is now fPLL1PHI0 (PLL1 output
clock PHI0)
• Specification change: fPLL1PHI0 (PLL1 output clock PHI0) max is 200 MHz (was
625 MHz)
• fPLL1PHI parameter, Max column, changed 200MHz to 300MHz.
• Removed “F” from “FXOSC” in footnote 1
MPC5777M Microcontroller Data Sheet, Rev. 6
142
NXP Semiconductors
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—Oscillator and FMPLL (con’t)
Table 23 (External Oscillator electrical specifications):
• New specification: VHYS (Comparator Hysteresis)
• New specification: VEXTAL (Oscillation Amplitude on the EXTAL pin after startup)
• Specification change: fXTAL range values changed: fXTAL ranges are 4–8 MHz,
>8–20 MHz, and >20–40 MHz (previously stated as 4–8 MHz, 8–16 MHz, and
20–40 MHz
• Specification change tcst (Crystal start-up time) is now specified by temperature range
• Specification change: VIHEXT specified at VREF = 0.28 * VDD_HV_IO_JTAG (previously
specified at VDDOSC = 3.0 V and VDDOSC = 5.5 V)
• Specification change: VILEXT specified at VREF = 0.28 * VDD_HV_IO_JTAG (previously
specified at VDDOSC = 3.0 V and VDDOSC = 5.5 V)
• Specification change: CS_EXTAL values specified by package (was previously based on
selected load capacitance value)
• Specification change: CS_XTAL values specified by package (was previously based on
selected load capacitance value)
• Specification change: gm (Oscillator Transconductance) is now specified by
temperature and frequency range conditions (was previously specified without
conditions)
• Footnote added: “All oscillator specifications are valid for
VDD_HV_IO_JTAG = 3.0 V – 5.5 V.“
• Footnote added to CS_EXTAL, CS_XTAL to refer to crystal manufacturer's specifications
for load capacitance values.
• Footnote added: “Amplitude on the EXTAL pin after startup is determined by the ALC
block, i.e., the Automatic Level Control Circuit. The function of the ALC is to provide
high drive current during oscillator startup, but reduce current after oscillation in order
to reduce power, distortion, and RFI, and to avoid over-driving the crystal. The
operating point of the ALC is dependent on the crystal value and loading conditions.”
• Footnote added: “IXTAL is the oscillator bias current out of the XTAL pin with both
EXTAL and XTAL pins grounded. This is the maximum current during startup of the
oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent
on the load and series resistance of the crystal.”
• VILEXT parameter, changed “External Reference” to “External Clock Input”
• VILEXT parameter, added footnote: This parameter is guaranteed by design rather than
100% tested.
Table 24 (Selectable load capacitance):
• Changed footnote 2 from “Values in this table do not include 8 pF routing and ESD
structure on die and package trace capacitance.” to "Values in this table do not include
the die and package capacitances given by Cs_xtal/Cs_extal in Table 23 (External
Oscillator electrical specifications).”
Electrical characteristics—ADC specifications
Section 3.10.1, ADC input description
Table 26 (ADC pin specification)
• ILK_IN specification change: removed TA = 125 °C row from (TA = 125 °C)
• ILK_INUD, ILK_INUSD, ILK_INREF, and ILK_INOUT specification changes to parameters,
conditions, and values.
• Specification change: IINJ min value is –3 mA (was –1)
• Specification change: CS max value is 8.5 pF (was 7)
• Specification change: RSWn max value for SARn channels is 1.1 k (was 0.6)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors
143
Document revision history
Table 76. Revision history (continued)
Revision
Date
Description of changes
2
4/2013
Electrical characteristics—ADC specifications (con’t)
Section 3.10.1, ADC input description
Table 26 (ADC pin specification):
• Specification change: RSWn max value for SARB channels is 1.7 k (was 1.2)
• Specification change: RCMSW max value is 2.6 k(was 2)
• Removed VREF_BG specification
• Added VREF_BG_LR and VREF_BG_TC specifications
• Added footnote: Specifications in this table apply to both packaged parts and Known
Good Die (KGD) parts, except where noted.
• Added footnote: The temperature coefficient and line regulation specifications are
used to calculate the reference voltage drift at an operating point within the specified
voltage and temperature operating conditions.
• Parameter ILK_INOUT description column, changed MEDIUM output buffer with GPIO
output buffer.
Table 27 (SARn ADC electrical specification)
• Replaced table
Section 3.13.3, S/D ADC electrical specification
• Revised sentence to indicate that the ADCs are 14-bit (was 16-bit)
Table 28 (SDn ADC electrical specification)
• New specification: fPASSBAND (Pass band)
• Removed VDD and VSS specifications
• Removed fIN specification
• Throughout table, appended _D to change to VDD_HV_ADV_D (was VDD_HV_ADV),
VSS_HV_ADV_D (was VSS_HV_ADV), VDD_HV_ADR_D (was VDD_HV_ADR), and
VSS_HV_ADR_D (was VSS_HV_ADR).
• VIN_PK2PK (Input range peak to peak VIN_PK2PK= VINP – VINM): single ended
specification extended to include multiple conditions
• Multiple condition changes for the GAIN and SNRDIFF150 parameters
• GAIN: changed maximum value for Before calibration condition to “1.5 %” (was 1 %).
• SFDR conditions revised to include different GAIN settings
• Specification change: VBIAS min value is –2.5% (was –10) and the max value is +2.5%
(was +10)
• Significant revisions to footnotes, including one added to voltage range conditions in
all SNR specs: “In the range 3.6 V< VDD_HV_ADV
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