NXP Semiconductors
Data Sheet: Technical Data
VF3xxR, VF5xxR
Features
• Operating characteristics
– Voltage range 3 V to 3.6 V
– Temperature range(ambient) -40 °C to 85 °C
• ARM® Cortex® A5 Core features
– Up to 400 MHz ARM® Cortex® A5 core
– 32 KB/32 KB I/D L1 Cache
– 1.6 DMIPS/MHz based on ARMv7 architecture
– NEON™ MPE (Media Processing Engine) Coprocessor
– Double Precision Floating Point Unit
– 512 KB L2 cache (on selected part numbers only)
• ARM Cortex M4 Core features
– Up to 133 MHz ARM Cortex M4
– Integrated DSP capability
– 64 KB Tightly Coupled Memory (TCM)
– 16 KB/16 KB I/D L1 Cache
– 1.25 DMIPS/MHz based on ARMv7 architecture
• Clocks
– 24 MHz crystal oscillator
– 32 kHz crystal oscillator
– Internal reference clocks (128 KHz and 24 MHz)
– Phase Locked Loops (PLLs)
– Low Jitter Digital PLLs
• System debug, protection, and power management
– Various stop, wait, and run modes to provide low
power based on application needs
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low voltage warning and detect with selectable trip
points
– Illegal opcode and illegal address detection with
programmable reset or processor exception response
– Hardware CRC module to support fast cyclic
redundancy checks (CRC)
– 128-bit unique chip identifier
– Hardware watchdog
– External Watchdog Monitor (EWM)
– Dual DMA controller with 32 channels (with
DMAMUX)
Document Number VYBRIDRSERIESEC
Rev. 8, 01/2018
VYBRIDRSERIESEC
• Debug
– Standard JTAG
– 16-bit Trace port
• Timers
– Motor control/general purpose timer (FTM)
– Periodic Interrupt Timers (PITs)
– Low-power timer (LPTMR0)
– IEEE 1588 Timer per MAC interface (part of
Ethernet Subsystem)
• Communications
– Six Universal asynchronous receivers/transmitters
(UART)/Serial communications interface (SCI) with
LIN, ISO7816, IrDA, and hardware flow control
– Four Deserial Serial peripheral interface (DSPI)
– Four Inter-Integrated Circuit (I2C) with SMBUS
support
– Dual USB OTG Controller + PHY
– Dual 4/8 bit Secure Digital Host controller
– Local Media Bus (MLB50)
– Dual 10/100 Ethernet (IEEE 1588)
– Dual FlexCAN3
• Security
– ARM TrustZone including the TZ architecture
– Secure Non-Volatile Storage (SNVS)
– Real Time Clock
– Real Time Integrity Checker (RTIC)
– TrustZone Watchdog (TZ WDOG)
– Trust Zone Address Space Controller
– Random Number Generator
– Hashing
– Secure JTAG
• Memory Interfaces
– 8/16-bit DRAM Controller with support for
LPDDR2/DDR3 - Up to 400 MHz (ECC supported
for 8-bit only and not 16-bit)
– 8/16-bit NAND Flash controller with ECC (ECC
supported for 8-bit only and not 16-bit)
– Dual Quad SPI with XIP (Execute-In-Place)
– 8/16/32-bit External bus (Flexbus)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Display and Video
– Dual Display Control Unit (DCU) with support for color TFT display up to WVGA
– Segmented LCD (3V Glass only) configurable as 40x4, 38x8, and 36x6
– Video Interface Unit (VIU) for camera
– Open VG Graphics Processing Unit (GPU)
– VideoADC
• Analog
– Dual 12-bit SAR ADC with 1MS/s
– Dual 12-bit DAC
• Audio
– Four Synchronous Audio Interface (SAI)
– Enhanced Serial Audio Interface (ESAI)
– Sony Philips Digital Interface (SPDIF), Rx and Tx
– Asynchronous Sample Rate Converter (ASRC)
• Human-Machine Interface (HMI)
– GPIO pins with interrupt support, DMA request capability, digital glitch filter.
– Hysteresis and configurable pull up/down device on all input pins
– Configurable slew rate and drive strength on all output pins
• On-Chip Memory
– 512 KB On-chip SRAM with ECC
– 1 MB On-chip graphics SRAM (no ECC). This depends on the part selected. Alternate configuration could be 512 KB
graphics and 512 KB L2 cache.
– 96 KB Boot ROM
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NXP Semiconductors
Table of Contents
1
Ordering parts.....................................................................................5
1.1
2
3
4
5
Power Down Mode............................. 20
Determining valid orderable parts ..........................................5
6.2.6
EMC radiated emissions operating behaviors........ 21
Part identification............................................................................... 5
6.2.7
EMC Radiated Emissions Web Search Procedure
2.1
Description.............................................................................. 5
2.2
Part Number Format................................................................5
2.3
Part Numbers ..........................................................................6
boilerplate............................................................... 21
6.2.8
7
Terminology and guidelines...............................................................7
Capacitance attributes............................................. 21
I/O parameters....................................................................................22
7.1
GPIO parameters..................................................................... 22
3.1
Definition: Operating requirement.......................................... 7
3.2
Definition: Operating behavior............................................... 8
3.3
Definition: Attribute................................................................8
3.4
Definition: Rating....................................................................8
8.1
Power sequencing ...................................................................28
3.5
Result of exceeding a rating.................................................... 9
8.2
Power supply........................................................................... 29
3.6
Relationship between ratings and operating requirements......9
8.3
Absolute maximum ratings..................................................... 31
3.7
Guidelines for ratings and operating requirements................. 10
8.4
Recommended operating conditions....................................... 32
3.8
Definition: Typical value........................................................ 10
8.5
Recommended Connections for Unused Analog Interfaces... 33
3.9
Typical Value Conditions........................................................11
Handling ratings................................................................................. 11
7.1.1
7.2
8
9
Output Buffer Impedance measurement................. 24
DDR parameters......................................................................24
Power supplies and sequencing..........................................................28
Peripheral operating requirements and behaviours............................ 34
9.1
Analog..................................................................................... 34
4.1
ESD handling ratings ............................................................. 11
4.2
Thermal handling ratings........................................................ 12
9.1.1.1
12-bit ADC operating conditions........ 34
4.3
Moisture handling ratings........................................................12
9.1.1.2
12-bit ADC characteristics..................35
9.1.1
Operating Requirements.....................................................................12
5.1
6
6.2.5.1
9.1.2
12-bit ADC electrical characteristics...................... 34
12-bit DAC electrical characteristics...................... 39
Thermal operating requirements............................................. 12
9.1.2.1
12-bit DAC operating requirements....39
General............................................................................................... 12
9.1.2.2
12-bit DAC operating behaviors......... 39
6.1
AC electrical characteristics....................................................12
6.2
Nonswitching electrical specifications ...................................13
6.2.1
6.2.2
6.2.3
9.1.3
9.2
VREG electrical specifications .............................. 13
VideoADC Specifications.......................................43
Display and Video interfaces.................................................. 45
9.2.1
DCU Switching Specifications............................... 45
6.2.1.1
HPREG electrical characteristics........ 13
9.2.1.1
Interface to TFT panels (DCU0/1)......45
6.2.1.2
LPREG electrical characteristics.........14
9.2.1.2
Interface to TFT LCD Panels—Pixel
6.2.1.3
ULPREG electrical characteristics......14
6.2.1.4
WBREG electrical characteristics.......15
6.2.1.5
External NPN Ballast.......................... 15
Level Timings..................................... 46
9.2.1.3
Interface to TFT LCD panels—access
level..................................................... 47
LVD electrical specifications .................................17
9.2.2
Video Input Unit timing..........................................48
6.2.2.1
Main Supply electrical characteristics 17
9.2.3
LCD driver electrical characteristics...................... 49
6.2.2.2
LVD DIG characteristics.....................18
9.3
Ethernet specifications............................................................ 50
LDO electrical specifications .................................18
9.3.1
Ethernet Switching Specifications.......................... 50
6.2.3.1
LDO_1P1............................................ 18
9.3.2
Receive and Transmit signal timing specifications 50
6.2.3.2
LDO_2P5............................................ 19
9.3.3
Receive and Transmit signal timing specifications
6.2.3.3
LDO_3P0 ........................................... 19
6.2.4
Power consumption operating behaviors................ 20
6.2.5
USB PHY current consumption..............................20
for MII interfaces.................................................... 51
9.4
Audio interfaces...................................................................... 53
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NXP Semiconductors
3
9.4.1
Enhanced Serial Audio Interface (ESAI) Timing
9.7.4
Parameters...............................................................53
9.5
9.6
9.7
9.4.2
SPDIF Timing Parameters...................................... 55
9.4.3
SAI/I2S Switching Specifications.......................... 56
Slow internal RC oscillator (128 KHz) electrical
characteristics..........................................................84
9.7.5
PLL1 and PLL2 (528 MHz System PLL)
Electrical Parameters.............................................. 84
Memory interfaces...................................................................58
9.7.6
PLL3 and PLL7 (480 MHz USB PLL) Electrical
9.5.1
QuadSPI timing.......................................................58
Parameters...............................................................84
9.5.2
NAND flash controller specifications.....................61
9.7.7
PLL5 (Ethernet PLL) Electrical Parameters........... 85
9.5.3
FlexBus timing specifications.................................64
9.7.8
PLL4 (Audio PLL) Electrical Parameters...............85
9.5.4
DDR controller specifications................................ 66
9.7.9
PLL6 (Video PLL) Electrical Parameters...............85
9.5.4.1
DDR3 Timing Parameters ..................66
9.8
Debug specifications............................................................... 86
9.5.4.2
DDR3 Read Cycle...............................68
9.8.1
JTAG electricals..................................................... 86
9.5.4.3
DDR3 Write cycle...............................69
9.8.2
Debug trace timing specifications...........................88
9.5.4.4
LPDDR2 Timing Parameter................70
10 Thermal attributes.............................................................................. 89
9.5.4.5
LPDDR2 Read Cycle.......................... 71
10.1 Thermal attributes................................................................... 89
9.5.4.6
LPDDR2 Write Cycle......................... 72
11 Dimensions.........................................................................................90
Communication interfaces.......................................................73
11.1 Obtaining package dimensions ...............................................90
9.6.1
MediaLB (MLB) DC Characteristics..................... 73
12 Pinouts................................................................................................91
9.6.2
MediaLB (MLB) Controller AC Timing Electrical
12.1 Pinouts.....................................................................................91
Specifications..........................................................73
12.2 Pinout diagrams.......................................................................103
9.6.3
DSPI timing specifications..................................... 75
12.2.1
GPIO Mapping........................................................105
9.6.4
I2C timing............................................................... 78
12.2.2
Special Signal ........................................................ 109
9.6.5
SDHC specifications...............................................80
13 Power Supply Pins............................................................................. 111
9.6.6
USB PHY specifications.........................................81
13.1 Power Supply Pins.................................................................. 111
Clocks and PLL Specifications............................................... 81
14 Functional Assignment Pins...............................................................112
9.7.1
24 MHz Oscillator Specifications...........................81
14.1 Functional Assignment Pins....................................................112
9.7.2
32 KHz Oscillator Specifications........................... 82
15 Revision History.................................................................................121
9.7.3
Fast internal RC oscillator (24 MHz) electrical
characteristics..........................................................83
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NXP Semiconductors
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web.
1. To determine the orderable part numbers for this device, go to www.nxp.com and
search the required part number. The part numbering format is described in the
section that follows.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Part Number Format
The figure below represents the format of part number of this device.
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NXP Semiconductors
5
Part identification
S V F 3 1 1 R 3 K1 C MK 2 R
Tape & Reel
R = Tape & Reel
(Optional)
Qualification Status
P = engineering samples
S = automotive qualified
Speed (A5 core)
2 = 266MHz
4 = 400MHz
Brand: V = Vybrid
Series: F = current
Package
KU = 176LQFP
MK = 364BGA
Family
3 = Standard
5 = Advanced
Core
1 = Cortex A5
2 = Cortex A5 + M4
3 = M4 Primary
Graphics
1 = No Open VG
2 = Open VG
Temp Spec
C = -40 to +85C Ta
Option
K1 = 2N02G with VADC
K2 = 3N02G with VADC
N2 = 3N02G with no VADC
Version
R = Auto
Memory Option
3 = Standard (1.5MB SRAM)
2 = Optional (1MB SRAM and 512K L2 Cache)
Figure 1. Part Number Format
2.3 Part Numbers
This table lists the part numbers on the device.
Part Number
Mask
VADC
Package
Description
SVF311R3K2CKU2
3N02G
YES
LQFP-EP 176 24*24*1.6
A5-266, 176LQFP-EP
SVF312R3K2CKU2
3N02G
YES
LQFP-EP 176 24*24*1.6
A5-266, OpenVG GPU, 176LQFP-EP
SVF321R3K2CKU2
3N02G
YES
LQFP-EP 176 24*24*1.6
A5-266, M4, 176LQFP-EP
SVF322R3K2CKU2
3N02G
YES
LQFP-EP 176 24*24*1.6
A5-266, M4, OpenVG GPU, 176LQFP
SVF331R3K2CKU2
3N02G
YES
LQFP-EP 176 24*24*1.6
A5-266, M4 Primary, 176LQFP-EP
SVF332R3K2CKU2
3N02G
YES
LQFP-EP 176 24*24*1.6
A5-266, M4 Primary, OpenVG GPU,
176LQFP-EP
SVF511R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, 364BGA
SVF512R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, OpenVG GPU, 364BGA
SVF521R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4, 364BGA
SVF522R2K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4, L2 Cache, OpenVG GPU,
364BGA
SVF522R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4, OpenVG GPU, 364BG
Table continues on the next page...
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6
NXP Semiconductors
Terminology and guidelines
Part Number
Mask
VADC
Package
Description
SVF531R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, 364BG
SVF532R2K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, L2 Cache OpenVG
GPU, 364BGA
SVF532R3K2CMK4
3N02G
YES
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, OpenVG GPU,
364BGA
SVF311R3N2CKU2
3N02G
NO
LQFP-EP 176 24*24*1.6
A5-266, 176LQFP-EP
SVF312R3N2CKU2
3N02G
NO
LQFP-EP 176 24*24*1.6
A5-266, OpenVG GPU, 176LQFP-EP
SVF321R3N2CKU2
3N02G
NO
LQFP-EP 176 24*24*1.6
A5-266, M4, 176LQFP-EP
SVF322R3N2CKU2
3N02G
NO
LQFP-EP 176 24*24*1.6
A5-266, M4, OpenVG GPU, 176LQFP
SVF331R3N2CKU2
3N02G
NO
LQFP-EP 176 24*24*1.6
A5-266, M4 Primary, 176LQFP-EP
SVF332R3N2CKU2
3N02G
NO
LQFP-EP 176 24*24*1.6
A5-266, M4 Primary, OpenVG GPU,
176LQFP-EP
SVF511R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, 364BGA
SVF512R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, OpenVG GPU, 364BGA
SVF521R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4, 364BGA
SVF522R2N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4, L2 Cache, OpenVG GPU,
364BGA
SVF522R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4, OpenVG GPU, 364BG
SVF531R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, 364BG
SVF532R2N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, L2 Cache OpenVG
GPU, 364BGA
SVF532R3N2CMK4
3N02G
NO
MAP 364 17*17*1.5 P0.8
A5-400, M4 Primary, OpenVG GPU,
364BGA
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
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Terminology and guidelines
3.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values
for a technical characteristic that are guaranteed during operation if you meet the
operating requirements and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
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NXP Semiconductors
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
Max.
–0.3
Unit
1.2
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
O
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.)
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Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
Expected permanent failure
–∞
∞
Operating (power on)
ng
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Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
Handling (power off)
∞
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NXP Semiconductors
9
Terminology and guidelines
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
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NXP Semiconductors
Handling ratings
5000
4500
4000
TJ
3500
150 °C
IDD_STOP (μA)
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Handling ratings
4.1 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
500
V
2
Latch-up Current at ambient temperature of 85 °C
-100
100
mA
ILAT
1. Determined according to the AEC spec AEC-Q100-002 for HBM
2. Determined according to AEC spec AEC-Q100-011
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NXP Semiconductors
11
Operating Requirements
4.2 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
Solder temperature, leaded
—
245
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5 Operating Requirements
5.1 Thermal operating requirements
Table 1. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Ambient temperature
–40
85
°C
TJ
Junction temperature
—
105
°C
6 General
6.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
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NXP Semiconductors
Nonswitching electrical specifications
Input Signal
High
Low
VIH
80%
50%
20%
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
6.2 Nonswitching electrical specifications
6.2.1 VREG electrical specifications
6.2.1.1
HPREG electrical characteristics
Table 2. HPREG electrical characteristics
Parameters
Min
Typ
Max
Unit
Comments
Power supply
3.0
3.3
3.6
V
-
Current Consumption
-
1.2
1.5
mA
@ no load
-
2.0
2.5
mA
@ full load
600
12001
mA
DC load current
1.23
1.26
V
Output current capacity
-
Output voltage @ no load
Output voltage @ full load
1.20
1.21
V
External decoupling cap
4.7
-
μF
-
0.05
0.1
Ohms
ESR of external
cap
20
mOhms
Total effective
PAD+PCB trace
resistances
@ DC @noload
-48
dB
@ DC @full load
-40
@ worst case any frequency
-20
PSRR with 4.7uF output cap
1. This is peak and not continuous maximum value.
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13
VREG electrical specifications
6.2.1.2
LPREG electrical characteristics
Table 3. LPREG electrical characteristics
Parameters
Min
Typ
Max
Unit
Power supply
3.0
3.3
3.6
V
Current Consumption
350
400
-
500
Output current capacity
Output voltage @ no load
Comments
μA
@ no load
650
μA
@ full load
100
200
mA
DC load current
1.22
1.240
V
Output voltage @ full load
1.180
V
External decoupling cap
4.7
μF
0.05
0.1
Ohms
ESR of external cap
20
mOhms
Total PAD+PCB trace
resistance
@ DC @noload
-40
dB
@ DC @full load
-35
Worst case @ any frequency
-12
PSRR with 4.7uF output cap
6.2.1.3
ULPREG electrical characteristics
Table 4. ULPREG electrical characteristics
Parameters
Min
Typ
Max
Unit
Power supply
3.0
3.3
3.6
V
Current Consumption
1.88
2.3
2.86
μA
-
610
670
μA
@ full load
20
mA
DC load current
1.175
V
Output current capacity
Output voltage @ no load
Output voltage @ full load
PSRR with 500 pF output cap
1.125
V
-20
dB
@ DC @noload
-50
@200KHz @noload
-37
@ DC @full load
-42
@200KHz @full load
-37
Worst case @ any frequency
@ any load
-15
Comments
@ no load
Worst case at any frequency
across corners
dB
VF3xxR, VF5xxR, Rev. 8, 01/2018
14
NXP Semiconductors
VREG electrical specifications
6.2.1.4
WBREG electrical characteristics
Table 5. WBREG electrical characteristics
Parameters
Min
Typ
Max
Unit
Comments
Power supply
3
3.3
3.6
V
-
Current Consumption
-
2
5
µA
@ no load
-
2
5
µA
@ full load
-
1
2
mA
DC load current
1.4
1.425
V
Output current capacity
Output voltage @ no load
Output voltage @ full load
1.375
1.398
Output voltage programmability
1.4
1.4
6.2.1.5
V
1.7
V
16 steps of 25
mV each
External NPN Ballast
The internal main regulator requires an external NPN ballast transistor to be connected as
shown in the following figure as well as an external capacitance to be connected to the
device in order to provide a stable 1.2V digital supply to the device. The HPREG design
allows for collector voltage lower than VDDREG value. See AN4807 at www.nxp.com .
NOTE
To not overload BCTRL output, collector voltage should appear
no later than VDDREG / VDD33 (3.3V).
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
15
VREG electrical specifications
Figure 3. External NPN Ballast connections
Table 6. BCTRL OUTPUT specification
Parameter
Value
Comments
BCTRL OUTPUT specification
20mA
BCTRL driver can not drive more than
20mA current
Maximum pin voltage
VDDREG-0.5V
For Example, VDDREG =3.0V BCTRL
should not exceed 2.5V.
Table 7. Assumptions For calculations
Parameter
Value
VDDREG
3.0V to 3.6V with typical value of 3.3V
Max DC Collector current
0.85A @85 °C
Emitter voltage
1.2V to 1.25V
Collector voltage
Equal to VDDREG
Table 8. General guidelines for selection of NPN ballast
Symbol
Parameters
Value
Hfe
Minimum DC
current gain (Beta)
42.5
PD (Junction to
ambient)
Minimum power
dissipation @
TA=85 °C
2.04
Unit
Comments
As BCTRL pin can not drive more than
20mA Minimum value of beta for a
collector current of 0.85A comes out to
be 42.5.
W
Assuming 0.85A collector current with
Collector voltage of Ballast 3.6V(max)
we get VCE= 3.6V-1.2V=2.4V So power
dissipated is 2.4V*0.85A=2.04W . This
should be met for junction to ambient
power dissipation spec of ballast
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
16
NXP Semiconductors
LVD electrical specifications
Table 8. General guidelines for selection of NPN ballast (continued)
Symbol
Parameters
Value
Unit
Comments
IcmaxDC peak
Maximum peak DC
collector current
0.85
A
1.2A and above capacity device
preferable
V
For a VDDREG of 3.0 V (min.), BCTRL
pin can drive voltage up to VDDREG 0.5 V = 2.5 V. Since emitter of ballast is
fixed at 1.25 V (max) if chosen ballast
can supply 0.85 A collector current @ 85
°C with a base-to-emitter voltage of 1.25
V or lower, it is suitable for application.
VBE
Maximum voltage 1.25V for 0.85A @
that BCTRL pin can
85 °C
drive
Ft
Unity current gain
Frequency of
Ballast
50
MHz
Reducing the collector-to-emitter voltage drop lowers the ballast transistor heat
dissipation. This can be implemented in two ways:
1. By introducing series resistor or diode(s) between the collector and VDDREG
(placed far enough from the transistor for proper cooling)
2. By connecting the collector to a separate lower-voltage supply
In both of the above cases the transistor has to stay away from the deep saturation region;
otherwise, due to significant Hfe degradation, its base current exceeds the BCTRL output
maximum value.
In general, the transistor must be selected such that its Vce saturation voltage is lower
than the expected minimum Collector-Emitter voltage, and at the same time, the base
current is less than 20 mA for the maximum expected collector current. More information
can be found in collateral documentation at http://www.nxp.com
6.2.2 LVD electrical specifications
6.2.2.1
Main Supply electrical characteristics
Table 9. LVD_MAIN supply electrical characteristics
Main Supply LVD
Parameters
Min
Typ
Max
Unit
Power supply
3.0
3.3
3.6
V
2.76
2.915
V
Upper voltage threshold
(value @27oC)
Lower voltage threshold
(value @27oC)
Time constant of RC filter at
LVD input (0.69*RC)
2.656
2.73
3.3
Comments
V
μs
3.3 V noise rejection at LVD
comparator input
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
17
LDO electrical specifications
6.2.2.2
LVD DIG characteristics
Table 10. LVD DIG electrical specifications [HPREG(RUN MODE) and LPREG(STOP
MODE)]
LVD DIG
Parameters
Min
Typ
Max
Unit
Power supply
3.0
3.3
3.6
V
Upper voltage
threshold
1.135
1.16
1.185
V
Lower voltage
threshold
1.105
1.13
1.155
V
Time constant of
RC filter at LVD
input
200
Comments
ns
1.2V noise rejection at the input of
LVD comparator
Table 11. LVD DIG electrical specifications [ULPREG(STANDBY
MODE)]
LVD DIG Parameters
Min
Typ
Max
Unit
Power supply
3.0
3.3
3.6
V
Upper voltage threshold
1.105
1.13
1.155
V
Lower voltage threshold
1.075
1.10
1.125
V
Time constant of RC filter at
LVD input
200
Comments
ns
1.2V noise rejection at the
input of LVD comparator
6.2.3 LDO electrical specifications
6.2.3.1
LDO_1P1
Specification
Table 12. LDO_1P1 parameters
Min
Typ
Max
Unit
Comments
VDDIO
3
3.3
3.6
V
IO supply
VDD1P1_OUT
0.9
1.1
1.2
V
Regulator output
I_out
-
150
mA
>= 300mV drop out
1.4
V
Programmable in
25mV steps
Regulator output
0.8
programming range
1.1
Brownout Voltage
0.85
0.94
Brownout offset
step
0
-
175
mV
Programmable in
25mV steps
Minimum external
decoupling
capacitor
1
-
-
µF
low ESR
V
VF3xxR, VF5xxR, Rev. 8, 01/2018
18
NXP Semiconductors
LDO electrical specifications
For additional information, see the device reference manual.
6.2.3.2
LDO_2P5
Specification
Table 13. LDO_2P5 parameters
Min
Typ
Max
Unit
Comments
VDDIO
3
3.3
3.6
V
IO supply
VDD2P5_OUT
2.3
2.5
2.6
V
Regulator output
I_out
-
350
mA
@500mV drop out
2.75
V
Programmable in
25mV steps
Regulator output
2.0
programming range
2.5
[P:][C:] Brownout
Voltage
2.25
2.33
Brownout offset
step
0
-
175
mV
Programmable in
25mV steps
Minimum external
decoupling
capacitor
1
-
-
µF
low ESR
V
For additional information, see the reference manual.
6.2.3.3
LDO_3P0
Specification
Table 14. LDO_3P0 parameters
Min
Typ
Max
Unit
Comments
Input OTG VBUS
Supply
4.4
5.25
V
Input HOST VBUS
Supply
4.4
5.25
V
VDD3P0_OUT
2.9
3.1
V
Regulator output at
default setting
I_out
-
50
mA
500 mV drop-out
voltage
3.4
V
Programmable in
25mV steps
3.0
Regulator output
2.625
programming range
[P:][C:] Brownout
Voltage
2.75
2.85
V
Brownout offset
step
0
-
175
mV
Programmable in
25mV steps
Minimum external
decoupling
capacitor
1
-
-
µF
low ESR
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
19
LDO electrical specifications
NOTE
These values are with Anadig_REG_3P0[ENABLE_ILIMIT]=
0 and Anadig_REG_3P0[ENABLE_LINREG]= 1. It is required
to set these values before using USB.
6.2.4 Power consumption operating behaviors
Table 15. Power consumption operating behaviors
Description
Typ.1
Max.2
Unit
IDD_RUN
Run mode current — All functionalities of the chip
available
400
850
mA
IDD_WAIT
Wait mode high frequency current at 3.3 V ± 10%
80
500
mA
3
Low-power run mode current at 3.3 V ± 10%,
24MHz operation, PLL Bypass.
13
325
mA
4
Ultra-low-power run mode current at 3.3 V ± 10%
12
395
mA
5
Symbol
IDD_LPRUN
IDD_ULPRUN
IDD_STOP
Stop mode current at 3.3 V ± 10%
7
300
mA
6
300
1300
uA
7
Low power stop 2/low power stop 3 with FIRC
disabled, current at 3.3 V ± 10%
50
875
uA
7
Battery backup mode
5
45
uA
8
IDD_LPS2FIRC/IDD_LPS3FIRC Low power stop 2/low power stop 3 with FIRC
enabled, current at 3.3 V ± 10%
IDD_LPS2/IDD_LPS3
IDD_VBAT
Notes
1. The Typ numbers represent the average value taken from a matrix lot of parts across normal process variation at ambient
temperature.
2. The Max numbers represent the single worst case value taken from a matrix lot of parts across normal process variation at
maximum temperature.
3. CA5, CM4 cores halted
4. 24MHz operation, PLL Bypass
5. 32 kHz /128 kHz operation, PLL Off
6. Lowest power mode with all power retained, RAM retention and LVD protection.
7. Standby Mode. 64K and 16K RAM retention. ADCs/DACs optionally power-gated. RTC functional. Wakeup from interrupts.
8. All supplies OFF, SRTC, 32kXOSC ON, tampers and monitors ON. 128k IRC optionally ON.
6.2.5 USB PHY current consumption
6.2.5.1
Power Down Mode
Everything powered down, including the VBUS valid detectors, typ condition.
Table 16. USB PHY Current Consumption in Normal Mode
Current
USBx_VBUS
VDD33_LDOIN
VDD33_LDOIN
(3.0V)
(2.5V)
(1.1V)
Avg
Avg
Avg
5.1 μA
1.7 μA
1, 1->0
pad transitions
Unit
ns
1.18
ns
3.10
ns
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
23
I/O parameters
Table 21. GPIO AC Electrical Characteristics (3.3V power mode) (continued)
Symbol
Drive strength1
Parameter
Low 0 1 1
tpi
Input Pad
Propagation Delay
rise/fall
Slew
rate
Test conditions
Min
Max
fast
4.06
4.09
slow
7.80
8.19
fast
5.72
6.22
1.06
1.31
1.22
1.41
without hysteresis
-
with hysteresis
-
150f Cload on, input
edge rate from pad
=1.2ns
Unit
ns
1. The drive strengths are controlled by the DSE bit of the Software MUX Pad Control Register. For details, see IOMUX
Controller chapter of the device reference manual.
7.1.1 Output Buffer Impedance measurement
Table 22. Output Buffer Average Impedance (3.3V power mode)
Symbol
Rdrv
Drive strength1
Parameter
Output driver
impedance
Min
Typ
Max
001
116
150
220
010
58
75
110
011
39
50
73
100
30
37
58
101
24
30
46
110
20
25
38
17
20
32
Unit
Ohm
Extra drive strength
111
1. The drive strengths are controlled by the DSE bit of the Software MUX Pad Control Register. For details, see IOMUX
Controller chapter of the device reference manual.
7.2 DDR parameters
Table 23. DDR operating conditions
Symbol
Parameter
Min
Typ
Max
Unit
vddi
Core internal supply voltage
1.16
1.23
1.26
V
ovdd
I/O output supply voltage
(DDR3 mode)
1.425
1.5
1.575
V
ovdd
I/O output supply voltage
(LPDDR2 mode)
1.14
1.2
1.26
V
vdd2p5
I/O PD predriver and level
shifters supply voltage
2.25
2.5
2.75
V
VF3xxR, VF5xxR, Rev. 8, 01/2018
24
NXP Semiconductors
I/O parameters
Table 24. LPDDR2 mode DC Electrical characteristics
Symbol
Parameter
Test
condition
Min
Voh
High-level
output voltage
Vol
Low-level
output voltage
Vref
Input
reference
voltage
0.49*ovdd
Vih(dc)
DC input high
voltage
Vil(dc)
Typ
Max
0.9*ovdd
Unit
V
0.1*ovdd
V
0.51*ovdd
V
Vref+0.13
ovdd
V
DC input low
voltage
ovss
Vref-0.13
V
Vih(diff)
DC differential
input logic
high
0.26
Note1
V
Vil(diff)
DC differential
input logic low
Note1
-0.26
V
Iin2
Input current
(no pull-up/
down)
Vin = ovdd or
0
2.5
uA
Tri-state I/O
supply
current2
Icc-ovdd
Vin = ovdd or
0
4
Vi = vddi or 0
1.5
Tri-state
Icc-vdd2p5
vdd2p5 supply
current2
0.5*ovdd
Tri-state core
supply
current2
Icc-vddi
1
Driver unit
(240 Ohm)
calibration
resolution
Rres
10
Notes
Note that the
JEDEC
LPDDR2
specification
(JESD209_2B
) supersedes
any
specification
in this
document.
Ohm
1. The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well
as the limitations for overshoot and undershoot.
2. Typ condition: typ model, 1.2 V, and 25 °C junction. Max condition: bcs model, 1.26V, and -40 °C. Min condition: wcs
model, 1.14V, and Tj 125 °C.
Table 25. DDR3 mode DC Electrical characteristics
Symbol
Parameter
Test
condition
Voh
High-level
output voltage
Vol
Low-level
Iol= 1mA
output voltage
Min
Typ
Max
0.8*ovdd
Unit
V
0.2*ovdd
V
Notes
Note that the
JEDEC
JESD79_3E
specification
supersedes
any
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
25
I/O parameters
Table 25. DDR3 mode DC Electrical characteristics (continued)
Symbol
Parameter
Test
condition
Min
Vref
Input
reference
voltage
0.49*ovdd
Vih(dc)
DC input high
voltage
Vil(dc)
Typ
Unit
0.51*ovdd
V
Vref+0.1
ovdd
V
DC input low
voltage
ovss
Vref-0.1
V
Vih(diff)
DC differential
input logic
high
0.2
Note1
V
Vil(diff)
DC differential
input logic low
Note1
-0.2
V
Vtt2
Termination
voltage
Vin = ovdd or
0
Iin3
Input current
(no pullup/
pulldown)
Vi = 0 Vi =
ovdd
3
Tri-state I/O
supply
current3
Icc-ovdd
Vin = ovdd or
0
5
Vi = vddi or 0
1.5
Tri-state
Icc-vdd2p5
vdd2p5 supply
current3
0.49*ovdd
0.5*ovdd
Max
0.5*ovdd
Notes
specification
in this
document
0.51*ovdd
Tri-state core
supply
current3
Icc-vddi
1
Driver unit
(240 Ohm)
calibration
resolution
Rres
10
uA
Ohm
1. The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well
as the limitations for overshoot and undershoot.
2. Vtt is expected to track ovdd/2.
3. Typ condition: typ model, 1.5 V, and 25 °C. Max condition: bcs model, 1.575V, and -40 °C. Min condition: wcs model,
1.425V, and max Tj °C 125 °C junction
Table 26. LPDDR2 mode AC Electrical characteristics
Symbol
Parameter
Vih(ac)
AC input logic
high
Vil(ac)
AC input logic
low
Vidh(ac)1
AC differential
input high
voltage
Test condition
Min
Vref+0.22
0.44
Max
Unit
ovdd
V
Vref-0.22
V
-
V
Notes
Note that the
Jedec LPDDR2
specification
(JESD209-2B)
supersedes any
specification in
this document.
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
26
NXP Semiconductors
I/O parameters
Table 26. LPDDR2 mode AC Electrical characteristics (continued)
Symbol
Parameter
Test condition
Vidl(ac)1
AC differential
input low voltage
Vix(ac)2
AC differential
Relative to
input crosspoint ovdd/2
voltage
Vpeak
Min
Max
Unit
0.44
V
0.12
V
Over/undershoot
peak
0.35
V
Varea
Over/undershoot at 800MHz data
area (above
rate
ovdd or below
ovss)
0.3
V*ns
tsr
Single output
slew rate
2
V/ns
tskd
Skew between
pad rise/fall
asymmetry +
skew cased by
SSN
0.2
ns
-0.12
0.4
Notes
1. Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac)-Vil(ac).
2. The typical value of Vix(ac) is expected to be about 0.5*ovdd, and Vix(ac) is expected to track variation of ovdd. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 27. DDR3 mode AC Electrical characteristics
Symbol
Parameter
Test condition
Min
Max
Unit
Vih(ac)
AC input logic
high
Vref+0.175
ovdd
V
Vil(ac)
AC input logic
low
ovss
Vref-0.175
V
Vidh(ac)1
AC differential
input high
voltage
0.35
-
V
Vidl(ac)1
AC differential
input low voltage
0.35
Vix(ac)2
AC differential
relative to
input crosspoint ovdd/2
voltage
Vref-0.15
Vpeak
Note that the
JEDEC
JESD79_3E
specification
supersedes any
specification in
this document
V
Vref+0.15
V
Over/undershoot
peak
0.4
V
Varea
Over/undershoot at 800 MHz data
area (above
rate
ovdd or below
ovss)
0.5
V*ns
tsr
Single output
slew rate
2
V/ns
0.4
Notes
Table continues on the next page...
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
27
Power supplies and sequencing
Table 27. DDR3 mode AC Electrical characteristics (continued)
Symbol
tskd
Parameter
Test condition
Min
Skew between
pad rise/fall
asymmetry +
skew cased by
SSN
Max
Unit
0.2
Notes
ns
1. Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac)-Vil(ac).
2. The typical value of Vix(ac) is expected to be about 0.5*ovdd, and Vix(ac) is expected to track variation of ovdd. Vix(ac)
indicates the voltage at which differential input signal must cross.
8 Power supplies and sequencing
8.1 Power sequencing
Table 28. Power sequencing
Power Supply (PKG Board Level
Level)
Power Nets
Parameters
Power
Order
VBAT
VBAT
Battery supply in case of LDOIN
fails
VDD33_LDOIN
VDD33
LDO input supply (LDO1P1,
LDO2P5, LDO1P1_RTC)
1
VDDREG
VDD33
Device PMU regulator and
External ballast supply
1
VDD33
VDD33
GPIO 3.3V IO supply, LCD Supply
1
SDRAMC_VDD1P5
SDRAMC_VDD1P5
1.2/1.5 DDR Main IO supply
VDDA33_ADC
VDDA33_ADC
3.3V supply for ADC, DAC and IO
segment
1
VREFH_ADC
VREFH_ADC
High Reference of ADC, DAC
1
VDDA33_AFE
VDDA33_AFE
3.3V supply of AFE (Video ADC)
1
VDD12_AFE
VDD
1.2V supply for AFE (Video ADC)
2
FA_VDD
VDD
Shorted with VDD at Board Level
in 364BGA (Test pin only)
NA
VDD
VDD
1.2V core supply from External
ballast
USB0_VBUS 1
USB_VBUS
VBUS supply for USB
NA
USB1_VBUS 2
USB_VBUS
VBUS supply for USB
NA
Comment
NA
NA
VDD33_LDOIN,VDDREG and
VDD33 should come from a
common supply source
(represented as 3.3V SMPS in
the Figure 4)
In case the Ballast transistor’s
collector is connected to the
1.5V DRAM supply (instead of
the 3.3V supply), turn this
1.5V supply on before turning
on the 3.3V.
2
1. Power sequencing of USB0_VBUS is independent of any other power supply.
VF3xxR, VF5xxR, Rev. 8, 01/2018
28
NXP Semiconductors
Power supplies and sequencing
2. Power sequencing of USB1_VBUS is independent of any other power supply.
NOTE
NA stands for no sequencing needs, for example, the supply
can come in any order.
NOTE
All supplies grouped together e.g. 1,2, others. These have no
power sequencing restriction in between them.
NOTE
If none of the SDRAMC pins are connected on the board, the
SDRAMC supply could be left floating.
NOTE
At power up, 1.2V supply will follow 3.3V supply. At power
down, it should be checked that 1.2V falls before 3.3V.
NOTE
The standby current on USBx_VBUS is 300 - 500 uA. This is
well below the 2.5 mA limit set by the USB 2.0 specification.
This supply will be ON for applications that need to monitor the
USB bus during standby. This supply can be turned-off during
standby in applications that cannot tolerate the standby current
and do not monitor the USB bus.
8.2 Power supply
VF3xxR, VF5xxR, Rev. 8, 01/2018
NXP Semiconductors
29
Power supplies and sequencing
10uF
VDDA33_AFE
BCTRL
VDD
4.7uF
VDD
VideoADC
HPREG
LPREG
VDDREG
WELL PD1
48K
16K
WBREG*
3.3V
ULPREG
VDD33_LDOIN
GPIO's
PD0
VDD33
DAC x 2
eFUSE
LDO2P5
SNVS_IO
COIN
cell
Battery supply
(See note)
12-bit SAR
ADC x 2
USB 0/1 PHY
PLLs
DDR IO
SDRAMC_VDD2P5
1.5V/1.2V DDR Supply
SDRAMC_VDD1P5
DECAP_V25_LDO_OUT
LDO1P1
SNVS
LDO
VDDA33_ADC
VREFH_ADC
PLLs
SNVS
LDO3P0
USB_DCAP
DECAP_V11_LDO_OUT
USB0_VBUS (5V)
USB1_VBUS (5V)
Figure 4. Power supply
NOTE
VBAT is the backup battery supply. If not required, then VBAT
should be tied to VDDREG.
NOTE
WBREG is the Well Bias Regulator. Supplies PD1 WELL
during well bias modes.
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Power supplies and sequencing
8.3 Absolute maximum ratings
NOTE
These are the values above which device can get damaged.
Refer to the recommended operating conditions table for
intended use case values
Table 29. Absolute maximum ratings
Symbol
Parameters
Min
Max
Unit
USB0_VBUS
VBUS supply for USB
-
5.25
V
USB1_VBUS
VBUS supply for USB
USB_DCAP
USB LDO 5V->3.3V Outpu
-
5.25
V
-0.3
3.6
V
USB0_DP
USBx data line input voltage
-0.3
3.6
V
VBAT
Battery supply in case of LDOIN
fails
-0.3
3.6
V
VDD33_LDOIN
LDO input supply
-0.3
3.6
V
DECAP_V11_LDO_OUT
LDO 3.3V -> 1.1V Output
-0.3
1.3
V
DECAP_V25_LDO_OUT
LDO 3.3V -> 2.5 Output for PLL,
DDR, EFUSE
-0.3
3.6
V
VDD33
GPIO 3.3V IO supply
-0.3
3.6
V
VDDREG
Device PMU regulator and
External ballast supply
-0.3
3.6
V
VDDA33_ADC
3.3V supply for ADC, DAC and IO
segment
-0.3
3.6
V
VREFH_ADC
3.3V supply of AFE (Video ADC)
-0.3
3.6
V
VDDA33_AFE
3.3V supply of AFE (Video ADC)
-0.3
3.6
V
VDD12_AFE
1.2V supply for AFE (Video ADC)
-0.3
1.3
V
FA_VDD
Test purpose only
-0.3
1.3
V
VDD
1.2V core supply
-0.3
1.3
V
SDRAMC_VDD1P5
1.2/1.5 DDR Main IO supply
-0.3
1.975
V
SDRAMC_VDD2P5
2.5V DDR pre-drive supply
DD2P5_LDO_OUT
-0.3
3.6
V
USB0_DN
USB1_DP
USB1_DN
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Power supplies and sequencing
8.4 Recommended operating conditions
Table 30. Recommended operating conditions
Symbol
Parameters
USB0_VBUS
Conditions
Min
Typ
Max
Unit
VBUS supply for USB
w.r.t USB0_GND
4.4
5
5.25
V
USB1_VBUS
VBUS supply for USB
w.r.t USB1_GND
4.4
5
5.25
V
USB_DCAP
USB LDO 5V->3 V
Output
VBAT
Battery supply in case
of LDOIN fails
VDD33_LDOIN
LDO input supply
External DCAP (10uF
termination for
USBREG)
External CAP 0.1uF
3
V
2.4
3.3
3.6
V
3
3.3
3.6
V
DECAP_V11_LDO_OU LDO 3.3V -> 1.1V
T
Output
Recommended
External DCAP:
1uF(Min) 10uF (Max)
1.1
V
DECAP_V25_LDO_OU LDO 3.3V -> 2.5 Output
T
for PLL, DDR predriver, EFUSE
Recommended
External DCAP:
1uF(Min) 10uF (Max)
2.5
V
VDD33
GPIO 3.3V IO supply
External CAP (10uF)
3
3.3
3.6
V
VDDREG
Device PMU regulator
and External ballast
supply
External CAP (10uF)
3
3.3
3.6
V
VDDA33_ADC
3.3V supply for ADC,
DAC and IO segment
External CAP (10uF)
3
3.3
3.6
V
VREFH_ADC
High reference voltage
for ADC and DAC
Relation with
VDDDA33_ADC (1uF)
2.5
3.3
VDDA33_
ADC
V
VREFL_ADC
Low reference voltage
for ADC and DAC
External CAP (10uF)
VDDA33_AFE
3.3V supply of AFE
(Video ADC)
VDD12_AFE
0
External CAP 10uF
V
3
3.3
3.6
V
1.2V supply for AFE
(Video ADC)
1.16
1.23
1.26
V
FA_VDD
For testing purpose
only should be shorted
to VDD on board.
1.16
1.23
1.26
V
VDD1
1.2V core supply
1.16
1.23
1.26
V
USB0_GND
Ground supply for USB
0
V
USB1_GND
Ground supply for USB
0
V
VSS_KEL0
USB LDO ground
output
0
V
VSS
VSS ground
0
V
VSSA33_ADC
Ground supply for ADC,
DAC and IO segment
0
V
4.7uF with a low ESR
value (100 milliohms)
Table continues on the next page...
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Power supplies and sequencing
Table 30. Recommended operating conditions (continued)
Symbol
Parameters
Conditions
Min
VSSA33_AFE
Ground supply of AFE
(Video ADC)
0
V
VSS12_AFE
Ground supply for AFE
(Video ADC)
0
V
SDRAMC_VDD1P5
LPDDR2
External CAP 10uF
1.142
1.2
1.26
V
SDRAMC_VDD1P5
DDR3
External CAP 10uF
1.425
1.5
1.575
V
SDRAMC_VDD2P5
2.5V DDR pre-drive
supply
DD2P5_LDO_OUT
External CAP 10uF
2.25
2.5
2.75
V
-
Maximum power supply
ramp rate (Slew limit for
power-up)
0.1
V/us
-
Typ
Max
Unit
1. For customer applications, this is governed by ballast output which is controlled by the device and appropriate voltage
ranges are maintained.
8.5 Recommended Connections for Unused Analog Interfaces
NOTE
There are two options to handle unused power pins:
1. Connect all unused supplies to their respective voltage. To
save the power, do not enable the module and/or do not
enable clock gate to the module.
2. Keep all unused supplies floating.
If pin is shared by several peripheral, then all peripherals
connected to multiplexer have to be powered. For example: if
pin is shared by GPIO and ADC input and GPIO functionality
is used, then ADC has to be powered due to internal structure of
the multiplexer. Keep unused input signals grounded if power
pins are powered. Keep unused input signals floating if power
pins are floating. Keep unused output signals floating.
Module
Name
Recommendation if Unused
ADC
VDDA33_ADC
3.3V or float (Note: Powers both ADC
and DAC)
VREFH_ADC, VREFL_ADC
VREFH_ADC same as VDDA33_ADC
VREFL_ADC ground or float
ADC0SE8, ADC0SE9, ADC1SE8,
ADC1SE9
Ground or float
CCM
LVDS0P, LVDS0N
Float
DAC
DACO0, DACO1
Float
Table continues on the next page...
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33
Peripheral operating requirements and behaviours
Module
Name
Recommendation if Unused
USB
USB_DCAP, USB0_VBUS,
USB1_VBUS
Connect USBx_VBUS and USB_DCAP
together and tie to ground through a 10K
ohm resistor. Do NOT tie directly to
ground, latch-up risk.
USB0_GND, USB1_GND
Ground
USB0_VBUS_DETECT,
USB1_VBUS_DETECT
Float
USB0_DM, USB0_DP, USB1_DM,
USB1_DP
Float
VDDA33_AFE
3.3V or Float
VDD12_AFE
1.2V or Float
Video ADC
VADC_AFE_BANDGAP
Float
VADCSE0, VADCSE1, VADCSE2,
VADCSE3
Ground or Float
9 Peripheral operating requirements and behaviours
9.1 Analog
9.1.1 12-bit ADC electrical characteristics
9.1.1.1
12-bit ADC operating conditions
Characteristic
Table 31. 12-bit ADC Operating Conditions
Conditions
Symb
Min
Typ
Max
Unit
Comment
1
Supply voltage
Absolute
VDDAD
2.5
-
3.6
V
-
Delta to VDDAD (VDDVDDAD), 2
ΔVDDAD
-100
0
100
mV
-
Ground voltage
Delta to VSSAD (VSSVSSAD)2
ΔVSSAD
-100
0
100
mV
-
Ref Voltage High
-
VREFH
1.5
VDDAD
VDDAD
V
-
Ref Voltage Low
-
VREFL
VSSAD
VSSAD
VSSAD
V
-
Input Voltage
-
VADIN
VREFL
-
VREFH
V
-
Input Capacitance
8/10/12 bit modes
CADIN
-
1.5
2
pF
-
Input Resistance
ADLPC=0, ADHSC=1
RADIN
-
5
7
kohms
-
ADLPC=0, ADHSC=0
-
12.5
15
kohms
-
ADLPC=1, ADHSC=0
-
25
30
kohms
-
Table continues on the next page...
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Analog
Table 31. 12-bit ADC Operating Conditions (continued)
Characteristic
Conditions
Symb
Min
Typ
Max
Unit
Comment
1
kohms
Tsamp=150
ns
1
Analog Source
Resistance
12 bit mode fADCK =
40MHz ADLSMP=0,
ADSTS=10, ADHSC=1
RAS
-
-
RAS depends on Sample Time Setting (ADLSMP, ADSTS) and ADC Power Mode (ADHSC, ADLPC). See charts for Minimum
Sample Time vs RAS
ADC Conversion Clock
Frequency
ADLPC=0, ADHSC=1
12 bit mode
fADCK
4
-
40
MHz
-
ADLPC=0, ADHSC=0
12 bit mode
4
-
30
MHz
-
ADLPC=1, ADHSC=0
12 bit mode
4
-
20
MHz
-
1. Typical values assume VDDAD = 3.3 V, Temp = 25°C, fADCK=20 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference
Simplified input pin
equivalent circuit
Pad
leakage
due to
input
protection
ZAS
RAS
VAS
+
–
CAS
ZADIN
Simplified channel
select circuit
RADIN
ADC SAR
engine
+
VADIN
–
RADIN
Input pin
Input pin
RADIN
RADIN
Input pin
CADIN
Figure 5. 12-bit ADC Input Impedance Equivalency Diagram
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NXP Semiconductors
35
Analog
9.1.1.2
12-bit ADC characteristics
Table 32. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Characteristic
Conditions1
Symb
Supply Current
ADLPC=1, ADHSC=0
IDDAD
Min
Typ 2
250
ADLPC=0, ADHSC=0
350
ADLPC=0, ADHSC=1
400
Supply Current
Stop, Reset, Module
Off
IDDAD
0.01
ADC Asynchronous
Clock Source
ADHSC=0
fADACK
10
Sample Cycles
ADLSMP=0,
ADSTS=00
Conversion Cycles
Conversion Time
ADHSC=1
Csamp
2
4
ADLSMP=0,
ADSTS=10
6
ADLSMP=0,
ADSTS=11
8
ADLSMP=1,
ADSTS=00
12
ADLSMP=1,
ADSTS=01
16
ADLSMP=1,
ADSTS=10
20
ADLSMP=1,
ADSTS=11
24
Cconv
28
ADLSMP=0
ADSTS=01
30
ADLSMP=0
ADSTS=10
32
ADLSMP=0
ADSTS=11
34
ADLSMP=1
ADSTS=00
38
ADLSMP=1
ADSTS=01
42
ADLSMP=1
ADSTS=10
46
ADLSMP=1,
ADSTS=11
50
ADLSMP=0
ADSTS=00
ADLSMP=0
ADSTS=01
0.8
Unit
Comment
µA
ADLSMP=0
ADSTS=10 ADCO=1
µA
MHz
tADACK = 1/fADACK
20
ADLSMP=0,
ADSTS=01
ADLSMP=0
ADSTS=00
Max
Tconv
0.7
cycles
cycles
µs
Fadc=40 MHz
0.75
Table continues on the next page...
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NXP Semiconductors
Analog
Table 32. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Characteristic
Total Unadjusted
Error
Conditions1
Symb
0.8
ADLSMP=0
ADSTS=11
0.85
ADLSMP=1
ADSTS=00
0.95
ADLSMP=1
ADSTS=01
1.05
ADLSMP=1
ADSTS=10
1.15
ADLSMP=1,
ADSTS=11
1.25
12 bit mode
Comment
LSB3
With Max Averaging
LSB3
Waiting for histogram
method confirmation
LSB3
Waiting for histogram
method confirmation
LSB3
VADIN = VREFL With
Max Averaging
LSB3
VADIN = VREFH With
Max Averaging
+5
10 bit mode
-0.5
-
+2
8 bit mode
-0.25
-
+1.5
-
±0.6
±1.5
-
±0.5
±1
-
±0.25
±0.5
-
±2
±4
10bit mode
-
±1
±2
8 bit mode
-
±0.5
±1
-
+1.0
±1.6
10bit mode
-
±0.4
±0.8
8 bit mode
-
±0.1
±0.4
-
±2
±3.5
12 bit mode
DNL
10bit mode
8 bit mode
Quantization Error
Unit
-
Integral Non-Linearity
TUE
Max
-2
12 bit mode
Full-Scale Error
Typ 2
ADLSMP=0
ADSTS=10
Differential NonLinearity
Zero-Scale Error
Min
INL
12 bit mode
EZS
12 bit mode
EFS
10bit mode
-
±0.5
±1
8 bit mode
-
±0.25
±0.75
-
±1 to 0
10bit mode
-
±0.5
8 bit mode
-
±0.5
10.1
10.7
12 bit mode
EQ
LSB3
Effective Number of
Bits
12 bit mode
ENOB
Signal to Noise plus
Distortion
See ENOB
SINAD
SINAD = 6.02 x ENOB + 1.76
dB
Input Leakage Error
all modes
EIL
IIn x RAS
mV
Temperature Sensor
Across the full
Slope
temperature range of
the device
Temperature Sensor
Voltage
25°C
-
Bits
m
--
1.84
--
mV/°C
VTEMP25
-
696
-
mV
Fin = 100Hz
IIn = 400 nA leakage
current
1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
2. Typical values assume VDDAD = 3.3 V, Temp = 25°C, Fadck=20 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
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Analog
3. 1 LSB = (VREFH - VREFL)/2N
NOTE
The ADC electrical spec would be met with the calibration
enabled configuration.
Figure 6. Minimum Sample Time Vs Ras (Cas = 2pF)
Figure 7. Minimum Sample Time Vs Ras (Cas = 5pF)
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NXP Semiconductors
Analog
Figure 8. Minimum Sample Time Vs Ras (Cas = 10pF)
9.1.2 12-bit DAC electrical characteristics
9.1.2.1
12-bit DAC operating requirements
Table 33. 12-bit DAC operating requirements
Symbol
Desciption
Min.
Typ
Max.
Unit
Notes
VDDA33_ADC
Supply voltage
3.0
3.3
3.6
V
VREFH_ADC
Reference voltage
2.5
3.3
VDDA33_
ADC
V
1
CL
Output load capacitance
—
100
pF
2
IL
Output load current
—
1
mA
1. User will need to set up DACx_STATCTRL [DACRFS]=1 to select the valid VREFH_ADC reference. When
DACx_STATCTRL [DACRFS]=0, the DAC reference is connected to an internal ground node and is not a valid voltage
reference. Note that the DAC and ADC share the VREFH_ADC reference simultaneously. )
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
9.1.2.2
Symbol
12-bit DAC operating behaviors
Table 34. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
100
μA
—
—
500
μA
—
10
15
μs
Notes
P
IDDA_DACH Supply current — high-power mode
P
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
Table continues on the next page...
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Analog
Table 34. 12-bit DAC operating behaviors (continued)
Symbol
Description
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
Min.
Typ.
Max.
Unit
Notes
—
3
5
μs
1
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08)
low-power mode
—
5
—
high-power mode
—
1
—
Vdacoutl
DAC output voltage range low — high-speed
mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
3
—
±0.4
±0.8
%FSR
4
—
±0.1
±0.6
%FSR
4
VOFFSET Offset error
EG
PSRR
Power supply rejection ratio, VDDA =3 V, T =
25 C
70
TCO
Temperature coefficient offset voltage
—
3.7
TGE
Temperature coefficient gain error
—
AC
Offset aging coefficient
—
Rop
Output resistance load = 3 kΩ
—
SR
Slew rate -80h→ F7Fh→ 80h
CT
1.
2.
3.
4.
5.
Gain error
dB
—
μV/C
0.000421
—
%FSR/C
—
100
μV/yr
—
250
Ω
V/μs
High power (SPHP)
1.7
3
Low power (SPLP)
0.3
0.6
Channel to channel cross talk
5
—
70
dB
Settling within ±1 LSB
The INL is measured for 0+100mV to VDACR−100 mV
The DNL is measured for 0+100mV to VDACR−100 mV
Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
VDDA = 3.3 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40 °C to 85 °C
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Analog
Figure 9. INL error vs. digital code
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Analog
Figure 10. DNL error vs. digital code
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NXP Semiconductors
Analog
Figure 11. Offset at half scale vs. temperature
9.1.3 VideoADC Specifications
This section describes the electrical specification and characteristics of the VideoADC
Analog Front End.
Table 35. VideoADC Specifications
Symbol
VDDA33_AFE
VDDA12_AFE
Vin
Description
Min.
Typ.
Max.
Unit
Notes
Supply voltage
3.0
3.3
3.6
V
—
Supply current
—
—
41
mA
—
Supply voltage
1.1
1.2
1.26
V
—
Supply current
—
—
14
mA
—
Input signal voltage range
0.5
0
External AC coupling
10
—
1.4
47
V
nF
The external AC coupling
capacitance cannot be too large.
Table continues on the next page...
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Analog
Table 35. VideoADC Specifications (continued)
Symbol
Description
VBG
Bandgap voltage
VDDA33_AFE
—
Typ.
0.6
VSSA33_AFE VDD12_AFE
100nF
(See notes)
VADC_AFE_BANDGAP
Min.
Max.
—
Unit
V
47nF
47nF
100nF
(See notes)
Band Gap
47nF
47nF
Mux,
Clamp
and
Filter
Bandgap voltage on
VADC_AFE_BANDGAP pin. Pin
should be decoupled with a 100nF
capacitor
VSS12_AFE
Control
Interface
100nF
VADCSE0
VADCSE1
VADCSE2
VADCSE3
Notes
ADC
Correction
To Video
Decoder
Figure 12. VideoADC supply scheme
Figure 13. VideoADC supply decoupling
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NXP Semiconductors
Display and Video interfaces
NOTE
VideoADC 3.3V and 1.2V power supply pins should be
decoupled to their respective grounds using low-ESR 100nF
capacitors
NOTE
If possible, avoid using switched voltage regulators for the AFE
power domains. Use linear voltage regulators instead.
NOTE
The 3.3V and 1.2V power domains should be separated from
other circuitry on the board by inductors/beads to filter out high
frequency noise.
9.2 Display and Video interfaces
9.2.1 DCU Switching Specifications
9.2.1.1
Interface to TFT panels (DCU0/1)
This section provides the LCD interface timing for a generic active matrix color TFT
panel. In the figure below, signals are shown with positive polarity. The sequence of
events for active matrix interface timing:
• PCLK latches data into the panel on its positive edge (when positive polarity is
selected). In active mode, PCLK runs continuously. This signal frequency could be
from 5 to 66 MHz depending on the panel type.
• HSYNC causes the panel to start a new line. It always encompasses at least one
PCLK pulse.
• VSYNC causes the panel to start a new frame. It always encompasses at least one
HSYNC pulse.
• DE acts like an output enable signal to the LCD panel. This output enables the data
to be shifted onto the display. When disabled, the data is invalid and the trace is off.
Figure 14. TFT LCD interface timing overview1
1.
In the figure, LD[23:0]” signal is “line data,” an aggregation of the DCU’s RGB signals—R[0:7], G[0:7] and B[0:7].
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45
DCU Switching Specifications
VSYNC
HSYNC
LINE 1
LINE 2
LINE 3
LINE
n-1
LINE 4
LINE n
HSYNC
DE
1
2
3
m-1
m
PCLK
LD[23:0]
9.2.1.2
Interface to TFT LCD Panels—Pixel Level Timings
This section provides the horizontal timing (timing of one line), including both the
horizontal sync pulse and data. All parameters shown in the figure below are
programmable. This timing diagram corresponds to positive polarity of the PCLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of
the HSYNC, VSYNC and DE signals. The user can select the polarity of the HSYNC and
VSYNC signals via the SYN_POL register, whether active-high or active-low. The
default is active-high. The DE signal is always active-high. Pixel clock inversion and a
flexible programmable pixel clock delay are also supported. They are programmed via
the clock divide . The DELTA_X and DELTA_Y parameters are programmed via the
DISP_SIZE register. The PW_H, BP_H and FP_H parameters are programmed via the
HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
Table 36. LCD interface timing parameters—horizontal and vertical
Symbol
Characteristic
Unit
tPCP
Display pixel clock period
11.2
ns
tPWH
HSYNC pulse width
PW_H * tPCP
ns
tBPH
HSYNC back porch width
BP_H * tPCP
ns
tFPH
HSYNC front porch width
FP_H * tPCP
ns
tSW
Screen width
DELTA_X * tPCP
ns
tHSP
HSYNC (line) period
(PW_H + BP_H + FP_H + DELTA_X ) * tPCP
ns
tPWV
VSYNC pulse width
PWV * tHSP
ns
tBPV
VSYNC back porch width
BP_V * tHSP
ns
tFPV
VSYNC front porch width
FP_V * tHSP
ns
tSH
Screen height
DELTA_Y * tHSP
ns
tVSP
VSYNC (frame) period
(PW_V + BP_V + FP_V + DELTA_Y ) * tHSP
ns
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DCU Switching Specifications
tHSP
Start
of line
tPWH
tBPH
tSW
tFPH
tPCP
PCLK
Invalid Data
LD[23:0]
1
3
2
Invalid Data
DELTA_X
HSYNC
DE
Figure 15. Horizontal sync timing
tVSP
Start of
Frame
tPWV
tBPV
tSH
tFPV
tHCP
HSYNC
LD[23:0]
(Line Data)
Invalid Data
1
2
3
Invalid Data
DELTA_Y
HSYNC
DE
Figure 16. Vertical sync pulse
9.2.1.3
Interface to TFT LCD panels—access level
This section provides the access level timing parameters of the LCD interface.
Table 37. LCD Interface Timing Parameters1, 2, 3—Access Level
Symbol
Description
Min
Max
Unit
tCKP
Pixel Clock Period
11.2
_
ns
tDV
TFT interface data valid after pixel clock
_
4.4
ns
tDV
TFT interface HSYNC valid after pixel clock
_
4.4
ns
tDV
TFT interface VSYNC valid after pixel clock
_
4.4
ns
tDV
TFT interface DE valid after pixel clock
_
4.4
ns
tHO
TFT interface output hold time for data and control bits
0
_
ns
Relative skew between the data bits
_
4.4
ns
1. The characteristics in this table are based on the assumption that data is output at +ve edge and displays latch data on -ve
edg6
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DCU Switching Specifications
2. Intra bit skew is less than 2 ns
3. Load CL = 50 pf
tHO
tDV
Figure 17. LCD Interface Timing Parameters—Access Level
9.2.2 Video Input Unit timing
This section provides the timing parameters of the Video Input Unit (VIU) interface.
These are the clocking requirements of the VIU interface:
• The platform bus clock must be 2.5x pixel clock
• If the VIU3 does 2x horizontal upscaling, the ratio must be 3x
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DCU Switching Specifications
tSU tHO
Figure 18. VIU Timing Parameters
Table 38. VIU Timing Parameters
Symbol
Characteristic
Min Value
Max Value
Unit
fPIX_CK
VIU pixel clock frequency
_
64
MHz
tDSU
VIU data setup time
4
_
ns
tDHD
VIU data hold time
1
_
ns
9.2.3 LCD driver electrical characteristics
This section provides LCD driver electrical specification at VDD33 = 3.3 V ± 10%.
Table 39. LCD driver specifications
Symbol
Parameter
Min
VLCD
Voltage on VLCD (LCD supply) pin with
respect to VSS
0
ZBP/FP
LCD output impedance
(BP[n-1:0],FP[m-1:0]) for output levels
VDDE, VSS
_
IBP/FP
LCD output current (BP[n-1:0],FP[m-1:0]) for _
outputs charge/discharge voltage levels
VDDE2/3, VDDE1/2, VDDE/3)1
Typical
Max
Unit
VDD33 +
0.3
V
_
5.0
KΩ
25
_
µA
1. With PWR=10, BSTEN=0, and BSTAO=0
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Ethernet specifications
9.3 Ethernet specifications
9.3.1 Ethernet Switching Specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. All Ethernet
signals use pad type pad_fsr. The timing specifications described i the section assume a
pad slew rate setting of 11 and a load of 50 pF2.
9.3.2 Receive and Transmit signal timing specifications
This section provides timing specs that meet the requirements for RMII interfaces for a
range of transceiver devices.
Table 40. Receive signal timing for RMII interfaces
Characteristic
RMII Mode
Min
Unit
Max
—
EXTAL frequency (RMII input clock RMII_CLK)
—
50
MHz
E3, E7
RMII_CLK pulse width high
35%
65%
RMII_CLK period
E4, E8
RMII_CLK pulse width low
35%
65%
RMII_CLK period
E1
RXD[1:0], CVS_DV, RXER to RMII_CLK setup
4
—
ns
E2
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
E6
RMII_CLK to TXD[1:0], TXEN valid
—
14
ns
E5
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
Figure 19. RMII receive signal timing diagram
2.
These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11).
When operating this interface at lower frequencies, increase the slew rate by using the 10, 01, or 00 setting to increase
edge rise and fall times, thus reducing EMI.
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Ethernet specifications
Figure 20. RMII transmit signal timing diagram
NOTE
See the most current device errata document when using the
internally generated RXCLK and TXCLK clocks.
tCYC
tPWH
RX_CLK
(Input)
tS
tH
RXDn,
RX_DV,
RX_ER
(Input)
(n = 0-3)
Figure 21. MII receive signal timing diagram
Table 41. Receive signal timing for MII interfaces
Characteristic
MII Mode
Min
RX_CLK clock period (100/10 MBPS) tCYC
RX_CLK duty cycle, tPWH/tCYC
Typ
Unit
Max
40/400
45
50
ns
55
%
Input setup time before RX_CLK
tS
5
ns
Input setup time after RX_CLK
tH
5
ns
9.3.3 Receive and Transmit signal timing specifications for MII
interfaces
This section provides timing specs that meet the requirements for MII interfaces for a
range of transceiver devices.
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Ethernet specifications
tCYC
tPWH
RX_CLK
(Input)
tS
tH
RXDn,
RX_DV,
RX_ER
(Input)
(n = 0-3)
Figure 22. MII receive signal timing diagram
Table 42. Receive signal timing for MII interfaces
Characteristic
MII Mode
Min
RX_CLK clock period (100/10 MBPS) tCYC
Unit
Typ
Max
40/400
RX_CLK duty cycle, tPWH/tCYC
45
50
ns
55
%
Input setup time before RX_CLK
ts
5
ns
Input hold time after RX_CLK
th
5
ns
tCYC
tPWH
TX_CLK
(Input)
tD
TXDn,
TX_EN,
TX_ER
(Output)
Note: Device pins applicable to MII interface are applicable to TMII interface,
and operates at 50 MHz reference clock.
Figure 23. MII transmit signal timing diagram
Table 43. Transmit signal timing for MII interfaces
Characteristic
MII Mode
Min
TX_CLK clock period (100/10 MBPS) tCYC
TX_CLK duty cycle, tPWH/tCYC
Out delay from TX_CLK
Max
40/400
45
tD
Typ
Unit
2
50
ns
55
%
25
ns
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9.4 Audio interfaces
9.4.1 Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its
own clock generator. The following table shows the interface timing values.
Table 44. Enhanced Serial Audio Interface (ESAI) Timing
No
1
2
Characteristics
Clock
cycle2
Clock high period:
• master
• slave
Symbol
Min
Max
Condition1
Unit
tSSICC
30.0
—
master
ns
(4 × Tc)
—
—
—
ns
—
—
—
—
—
—
—
6
—
(2 × Tc −
9.0)
15
(2 × Tc)
3
Clock low period:
• master
• slave
—
FSR Input and Data Input setup time before SCKR
(SCK in synchronous mode) falling edge
—
6
—
Slave
—
15
—
Master
FSR Input and Data Input hold time after SCKR
falling edge
—
2
—
Slave
—
0
—
Master
6
SCKT rising edge to FST out and Data out valid
—
—
15
Slave
—
—
6
Master
7
SCKT rising edge to FST out and Data out hold
—
—
0
Slave
—
—
0
Master
8
FST input setup time before SCKT falling edge
—
6
—
Slave
—
15
—
Master
9
FST input hold time after SCKT falling edge
—
2
—
Slave
—
0
—
Master
10
HCKR/HCKT clock cycle
—
15
—
—
ns
11
HCKT input rising edge to SCKT output
—
—
18.0
—
ns
12
HCKR input rising edge to SCKR output
—
—
18.0
—
ns
4
5
—
6 (2 × Tc −
9.0)
ns
15 (2 × Tc)
ns
ns
ns
ns
ns
ns
(2 x TC)
1. SCKT(SCKT pin) = transmit clock SCKR(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) =
receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock
2. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
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Audio interfaces
1
2
3
SCKT
(input/output)
FST (bit) out
6
FST (word) out
First bit
Data out
Last
Lastbitbit
9
FST (bit) in
9
8
FST (word) in
Figure 24. ESAI Transmitter Timing
1
2
SCKR
(input/output)
3
FSR (bit) out
FSR (word) out
5
4
Data in
First bit
Last bit
FSR (bit) in
FSR (word) in
Figure 25. ESAI Receiver Timing
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Audio interfaces
9.4.2 SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase
marking code. When encoding, the SPDIF data signal is modulated by a clock that is
twice the bit rate of the data signal. Table and Figure below show SPDIF timing
parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the
timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the
modulating Tx clock (STCLK) for SPDIF in Tx mode.
Table 45. SPDIF Timing Parameters
Characteristic
Symbol
Timing Parameter Range
Min
SPDIFIN Skew: asynchronous inputs, no specs apply
Max
0.7
SPDIFOUT output (Load = 50pf)
• Skew
• Transition rising
• Transition falling
ns
• 1.5
• 24.2
• 31.3
SPDIFOUT1 output (Load = 30pf) - Skew
1.5
• Transition rising
• Transition falling
Unit
ns
ns
Refer Table 21
Modulating Rx clock (SRCK) period
srckp
40
ns
SRCK high period
srckph
16
ns
SRCK low period
srckpl
16
ns
Modulating Tx clock (STCLK) period
stclkp
40
ns
STCLK high period
stclkph
16
ns
STCLK low period
stclkpl
16
ns
Figure 26. SRCK Timing Diagram
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Audio interfaces
Figure 27. STCLK Timing Diagram
9.4.3 SAI/I2S Switching Specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 46. Master Mode SAI Timing
Num
Characteristic
Min
Max
Unit
S1
SAI_MCLK cycle time
2 x tSYS
—
ns
S2
SAI_MCLK pulse width high/low
40%
60%
MCLK period
S3
SAI_BCLK cycle time
4 x tSYS
—
ns
S4
SAI_BCLK pulse width high/low
40%
60%
BCLK period
S5
SAI_BCLK to SAI_FS output valid
—
15
ns
S6
SAI_BCLK to SAI_FS output invalid
0
—
ns
S7
SAI_BCLK to SAI_TXD valid
—
15
ns
S8
SAI_BCLK to SAI_TXD invalid
0
—
ns
S9
SAI_RXD/SAI_FS input setup before SAI_BCLK
15
—
ns
S10
SAI_RXD/SAI_FS input hold after SAI_BCLK
0
—
ns
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S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 28. SAI Timing — Master Modes
Table 47. Slave Mode SAI Timing
Num
Characteristic
Min
Max
Unit
S11
SAI_BCLK cycle time (input)
4 x tSYS
—
ns
S12
SAI_BCLK pulse width high/low (input)
40%
60%
BCLK period
S13
SAI_FS input setup before SAI_BCLK
10
—
ns
S14
SAI_FS input hold after SAI_BCLK
2
—
ns
S15
SAI_BCLK to SAI_TXD/SAI_FS output valid
—
20
ns
S16
SAI_BCLK to SAI_TXD/SAI_FS output invalid
0
—
ns
S17
SAI_RXD setup before SAI_BCLK
10
—
ns
S18
SAI_RXD hold after SAI_BCLK
2
—
ns
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
S14
I2S_FS (input)
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 29. SAI Timing — Slave Modes
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Memory interfaces
9.5 Memory interfaces
9.5.1 QuadSPI timing
• All data is based on a negative edge data launch from the device and a negative edge
data capture, as shown in the timing diagrams in this section. This corresponds to the
N/1 sample point as shown in the reference manual QSPI section "Internal Sampling
of Serial Flash Input Data."
• Measurements are with a load of 35 pF on output pins. I/P Slew : 1ns
• Timings assume a setting of 0x0000_000x for QSPI_SMPR register (see the
reference manual for details).
SDR mode
Tck
SCK
Tcss
Tcsh
CS
Tis
Tih
Data in
Figure 30. QuadSPI Input/Read timing (SDR mode)
Table 48. QuadSPI Input/Read timing (SDR mode)
Symbol
Parameter
Value
Min
Unit
Max
Tis
Setup time for incoming data
5.4
—
ns
Tih
Hold time requirement for incoming data
0
—
ns
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Memory interfaces
Tck
SCK
Tcss
Tcsh
CS
Toh
Tov
Data out
Figure 31. QuadSPI Output/Write timing (SDR mode)
Table 49. QuadSPI Output/Write timing (SDR mode)
Symbol
Parameter
Value
Min
Unit
Max
Tov
Output Data Valid
-
3.2
ns
Toh
Output Data Hold
0
-
ns
Tck
SCK clock period
-
80
MHz
Tcss
Chip select output setup time
3
-
SCK clock cycles
Tcsh
Chip select output hold time
3
-
SCK clock cycles
•
•
•
•
•
NOTE
Tcss and Tcsh are set by QuadSPI_FLSCH register, the
minimum values of 3 shown are the register default values,
refer to Reference Manual for further details.
The timing in the datasheet is based on default values for
the QuadSPI-SMPR register and is the recommended
setting for highest SCK frequency in SDR mode.
A negative time indicates the actual capture edge inside the
device is earlier than clock appearing at pad.
Frequency calculator guideline (Max read frequency): Tck
> (Flash access time)max + (Tis)max
A negative input hold time has no bearing on the maximum
achievable operating frequency.
DDR Mode
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Memory interfaces
Tck
SCK
Tcss
Tcsh
CS
Tih
Tis
Data in
Figure 32. QuadSPI Input/Read timing (DDR mode)
•
•
•
•
NOTE
The numbers are for a setting of 0x1 in register
QuadSPI_SMPR[DDRSMP]
Read frequency calculations should be: Tck/2 > (flash
access time) + Setup (Tis) (QuadSPI_SMPR[DDRSMP])x Tck/4
Frequency calculator guideline (Max read frequency):
Tck/2 > (Flash access time)max + (Tis)max (QuadSPI_SMPR[DDRSMP]) x Tck/4
Hold timing: flash_access (min) + flash_data_valid (min) >
Tck/2 + HOLD(Tih) + (QuadSPI_SMPR[DDRSMP])Tck/4
Table 50. QuadSPI Input/Read timing (DDR mode)
Symbol
Parameter
Value
Min
Unit
Max
Tis
Setup time for incoming data
6.5
—
ns
Tih
Hold time requirement for incoming data
0
—
ns
NOTE
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Tck
SCK
Tcss
Tcsh
CS
Tov
Toh
Data out
Figure 33. QuadSPI Output/Write timing (DDR mode)
Table 51. QuadSPI Output/Write timing (DDR mode)
Symbol
Parameter
Value
Min
Unit
Max
Tov
Output Data Valid
—
3.9
ns
Toh
Output Data Hold
0
—
ns
Tck
SCK clock period
-
45
MHz
Tcss
Chip select output setup time
3
-
Clk(sck)
Tcsh
Chip select output hold time
3
-
Clk(sck)
9.5.2 NAND flash controller specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
TNFC = TH + TL
NOTE
See the CCM section of the product reference manual for
further details on setting up the NFC clocks
(CCM_CSCDR2[NFC_FRAC_DIV_EN + NFC_FRAC_DIV]
and CCM_CSCDR3[NFC_PRE_DIV]).
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Memory interfaces
Table 52. NFC specifications
Num
Description
Min.
Max.
Unit
tCLS
NFC_CLE setup time
2TH + TL – 1
—
ns
tCLH
NFC_CLE hold time
TH + TL – 1
—
ns
tCS
NFC_CEn setup time
2TH + TL – 1
—
ns
tCH
NFC_CEn hold time
TH + TL
—
ns
tWP
NFC_WP pulse width
TL – 1
—
ns
tALS
NFC_ALE setup time
2TH + TL
—
ns
tALH
NFC_ALE hold time
TH + TL
—
ns
tDS
Data setup time
TL – 1
—
ns
tDH
Data hold time
TH – 1
—
ns
tWC
Write cycle time
TH + TL – 1
—
ns
tWH
NFC_WE hold time
TH – 1
—
ns
tRR
Ready to NFC_RE low
4TH + 3TL + 90
—
ns
tRP
NFC_RE pulse width
TL + 1
—
ns
tRC
Read cycle time
TL + TH – 1
—
ns
tREH
NFC_RE high hold time
TH – 1
—
ns
tIS
Data input setup time
11
—
ns
NFC_CLE
tCLS
tCLH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
tDH
NFC_IOn
Figure 34. Command latch cycle timing
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Memory interfaces
NFC_ALE
tALS
tALH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
NFC_IOn
tDH
address
Figure 35. Address latch cycle timing
tCS
tCH
tWC
NFC_CEn
tWP
tWH
tDS
tDH
NFC_WE
NFC_IOn
data
data
data
Figure 36. Write data latch cycle timing
tCH
tRC
NFC_CEn
tRP
tREH
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 37. Read data latch cycle timing in Slow mode
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Memory interfaces
tCH
tRC
NFC_CEn
tRP
tREH
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 38. Read data latch cycle timing in Fast mode and EDO mode
9.5.3 FlexBus timing specifications
This section provides FlexBus timing parameters. All processor bus timings are
synchronous; input setup/hold and output delay are given in respect to the rising edge of a
reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal
system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the FlexBus output clock (FB_CLK). All other timing relationships can be
derived from these values.
All FlexBus signals use pad type pad_fsr. The following timing specifications assume a
pad slew rate setting of 11 and a load of 50 pF3
Table 53. FlexBus timing specifications
Num
Characteristic
Frequency of operation
Min
—
Max
831
(with
Wait state)
Unit
MHz
572 without
Wait state ,
-1
FB1
Clock Period
12
—
ns
FB4
Input setup
10.6
—
ns
FB5
Input hold
0
—
ns
FB2
Output valid
—
6.4
ns
FB3
Output hold
0
—
ns
1. Freq = 1000/(11+ access time of external memory+ trace delay for clk and data)
2. Freq = 1000/(17+access time of external memory)
3.
These timing parameters are specified assuming maximum operating frequency and the fastest pad slew rate setting (11).
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Figure 39. FlexBus read timing
Figure 40. FlexBus write timing
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65
DDR controller specifications
9.5.4 DDR controller specifications
9.5.4.1
DDR3 Timing Parameters
Figure 41. DDR3 Command and Address Timing Parameters
NOTE
RESET pin has a external weak pull DOWN requirement if
DDR3 memory is NOT required to support content retention in
the device low power modes where core voltage is off but
DRAM voltage is on.
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DDR controller specifications
NOTE
RESET pin has a external weak pull UP requirement if DDR3
memory is required to support content retention in the device
low power modes where core voltage is off but DRAM voltage
is on.
NOTE
CKE pin has a external weak pull down requirement.
Table 54. DDR3 Timing Parameter
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
DDR1
CK clock high-level
width
tCH
0.47
0.53
tCK
DDR2
CK clock low-level
width
tCL
0.47
0.53
tCK
DDR4
CS, RAS, CAS,
CKE, WE, ODT
setup time
tIS
440
-
ps
DDR5
CS, RAS, CAS,
CKE, WE, ODT
hold time
tIH
315
-
ps
DDR6
Address output
setup time
tIS
440
-
ps
DDR7
Address output
hold time
tIH
315
-
ps
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
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9.5.4.2
DDR3 Read Cycle
Figure 42. DDR3 Read Cycle
Table 55. DDR3 Read Cycle
ID
DDR26
Parameter
Symbol
Minimum required DQ valid
window width
-
CK = 400 MHz
Unit
Min
Max
750
-
ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
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9.5.4.3
DDR3 Write cycle
Figure 43. DDR3 Write cycle
Table 56. DDR3 Write cycle
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
DDR17
DQ and DQM setup time to DQS
(differential strobe)
tDS
240
—
ps
DDR18
DQ and DQM hold time to DQS
(differential strobe)
tDH
215
—
ps
DDR21
DQS latching rising transitions to
associated clock edges
tDQSS
-0.25
+0.25
tCK
DDR22
DQS high level width
tDQSH
0.45
0.55
tCK
DDR22
DQS low level width
tDQSL
0.45
0.55
tCK
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
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9.5.4.4
LPDDR2 Timing Parameter
Figure 44. LPDDR2 Command and Address timing parameter
NOTE
RESET pin has a external weak pull DOWN requirement if
LPDDR2 memory is NOT required to support content retention
in the device low power modes where core voltage is off but
DRAM voltage is on.
NOTE
RESET pin has a external weak pull UP requirement if
LPDDR2 memory is required to support content retention in the
device low power modes where core voltage is off but DRAM
voltage is on.
NOTE
CKE pin has a external weak pull down requirement.
Table 57. LPDDR2 Timing Parameter
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
LP1
SDRAM clock high-level width
tCH
0.45
0.55
tCK
LP2
SDRAM clock LOW-level width
tCL
0.45
0.55
tCK
LP3
CS, CKE setup time
tIS
230
-
ps
LP4
CS, CKE hold time
tIH
230
-
ps
LP3
CA setup time
tIS
230
-
ps
LP4
CA hold time
tIH
230
-
ps
NOTE
All measurements are in reference to Vref level.
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NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
9.5.4.5
LPDDR2 Read Cycle
Figure 45. LPDDR2 Read cycle
Table 58. LPDDR2 Read Cycle
ID
Parameter
LP26
Symbol
Minimum required DQ valid
window width for LPDDR2
-
CK = 400 MHz
Unit
Min
Max
270
-
ps
NOTE
To receive the reported setup and hold values, read calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF
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9.5.4.6
LPDDR2 Write Cycle
Figure 46. LPDDR3 Write Cycle
Table 59. LPDDR2 Write Cycle
ID
Parameter
Symbol
CK = 400 MHz
Unit
Min
Max
LP17
DQ and DQM setup time to DQS
(differential strobe)
tDS
220
0.55
ps
LP18
DQ and DQM hold time to DQS
(differential strobe)
tDH
220
0.55
ps
LP21
DQS latching rising transitions to
associated clock edges
tDQSS
-0.25
+0.25
tCK
LP22
DQS high level width
tDQSH
0.4
-
tCK
LP23
DQS low level width
tDQSL
0.4
-
tCK
NOTE
To receive the reported setup and hold values, write calibration
should be performed in order to locate the DQS in the middle of
DQ window.
NOTE
All measurements are in reference to Vref level.
NOTE
Measurements were done using balanced load and 25 ohms
resistor from outputs to VDD_REF.
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9.6 Communication interfaces
9.6.1 MediaLB (MLB) DC Characteristics
The section lists the MediaLB 3-pin interface electrical characteristics.
Table 60. MediaLB 3-Pin Interface Electrical DC Specifications
Parameter
Symbol
Test Conditions
Maximum input voltage
—
—
Low level input threshold
VIL
—
Note1
Min
Max
Unit
—
3.6
V
—
0.7
V
1.8
—
V
High level input threshold
VIH
See
Low level output threshold
VOL
IOL = –6 mA
—
0.4
V
High level output threshold
VOH
IOH = –6 mA
2.0
—
V
Input leakage current
IL
0 < Vin < VDD
—
±10
μA
1. Higher VIH thresholds can be used; however, the risks associated with less noise margin in the system must be evaluated
and assumed by the customer.
9.6.2 MediaLB (MLB) Controller AC Timing Electrical Specifications
This section describes the timing electrical information of the MediaLB module.
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Figure 47. MediaLB 3-PinTiming
Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed =
256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold
as listed below; unless otherwise noted.
Table 61. MLB 256/512 Fs Timing Parameters
Parameter
Symbol
Min
Max
MLBCLK operating frequency
fmck
11.264
MLBCLK rise time
tmckr
Refer Table 21
MLBCLK fall time
tmckf
MLBCLK low
time1
25.6
Unit
Comment
MHz
256xFs at 44.0 kHz,
512xFs at 50.0 kHz
ns
VIL to VIH
ns
VIH to VIL
tmckl
30, 14
—
ns
256xFs, 512xFs
MLBCLK high time
tmckh
30, 14
—
ns
256xFs, 512xFs
MLBSIG/MLBDAT receiver input setup to
MLBCLK falling
tdsmcf
3
—
ns
—
MLBSIG/MLBDAT receiver input hold from
MLBCLK low
tdhmcf
2
—
ns
—
MLBSIG/MLBDAT output valid from
MLBCLK low
tmcfdz
0
16
ns
2
Bus output hold from MLBCLK low
tmdzh
2
—
ns
—
1. MLBCLK low/high time includes the pluse width variation.
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2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
Table 62. MLB 1024 Fs Timing Parameters
Parameter
Symbol
Min
Max
MLBCLK Operating Frequency1
fmck
45.056
MLBCLK rise time
fmckr
Refer Table 21
MLBCLK fall time
fmckf
MLBCLK low time
tmckl
6.1
MLBCLK high time
tmckh
MLBSIG/MLBDAT receiver input setup
to MLBCLK falling
51.2
Unit
Comme
nt
MHz
1024xfs
at 44.0
kHz
1024xfs
at 50.0
kHz
ns
VIL to VIH
ns
VIH to VIL
—
ns
2
9.3
—
ns
tdsmcf
3
—
ns
MLBSIG/MLBDAT receiver input hold
from MLBCLK low
tdhmcf
2
—
ns
MLBSIG/MLBDAT output valid from
MLBCLK low
tmcfdz
-
16
ns
Bus Hold from MLBCLK low
tmdzh
2
—
ns
3
1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a
runt pulse can occur on MLBCLK.
2. MLBCLK low/high time includes the pluse width variation.
3. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final
driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the
maximum load capacitance listed.
9.6.3 DSPI timing specifications
Table 63. DSPI timing
No.
Symbol
Characteristic
Condition
Min
Max
Unit
1
tSCK
SCK Cycle Time
—
tSYS * 2
—
ns
4
tSDC
SCK Clock Pulse Width
—
40%
60%
tSCK
2
tCSC
CS to SCK Delay
Master
16
—
ns
3
tASC
After SCK Delay
Master
16
—
ns
5
tA
Slave Access Time (SS active Slave
to SOUT driven)
—
15
ns
6
tDI
Slave Disable Time (SS
inactive to SOUT High-Z or
invalid)
Slave
—
10
ns
9
tSUI
Data Setup Time for Inputs
Master
9
—
ns
Table continues on the next page...
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Table 63. DSPI timing (continued)
No.
10
11
12
Symbol
tHI
Characteristic
Condition
tHO
Max
Slave
4
—
Master
0
—
Slave
2
—
Data Valid (after SCK edge)
for Outputs
Master
—
5
Slave
—
10
Data Hold Time for Outputs
Master
0
—
Slave
0
—
Data Hold Time for Inputs
tDV
Min
2
Unit
ns
ns
ns
3
CSx
1
4
S C K O utput
(C P O L = 0)
4
S C K O utput
(CP OL = 1 )
9
S IN
10
F irst D a ta
D ata
12
SOUT
F irst D ata
La st D ata
11
D ata
L ast D a ta
Figure 48. DSPI classic SPI timing master, CPHA=0
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CSx
S C K O u tp u t
(C P O L = 0 )
10
S C K O u tp u t
(CP OL = 1 )
9
D a ta
F irs t D a ta
S IN
L a s t D a ta
12
SOUT
11
D a ta
F irs t D a ta
L a st D a ta
Figure 49. DSPI classic SPI timing master, CPHA=1
3
2
SS
1
4
S C K In p u t
(C P O L = 0 )
4
S C K In p u t
(C P O L = 1 )
5
SOUT
F irs t D a ta
9
S IN
11
12
D a ta
L a s t D a ta
D a ta
L a s t D a ta
6
10
F irs t D a ta
Figure 50. DSPI classic SPI timing slave, CPHA=0
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SS
S C K In p u t
(C P O L = 0 )
S C K In p u t
(C P O L = 1 )
11
5
6
12
SOUT
F irst D a ta
9
S IN
D a ta
L a s t D a ta
D a ta
L a s t D a ta
10
F irst D a ta
Figure 51. DSPI classic SPI timing slave, CPHA=1
9.6.4 I2C timing
Table 64. I2C input timing specifications — SCL and SDA 1
No.
Parameter
Min.
Max.
Unit
1
Start condition hold time
2
—
PER_CLK
Cycle2
2
Clock low time
8
—
PER_CLK
Cycle
3
Bus free time between Start and Stop condition
4.7
—
μs
4
Data hold time
0.0
—
μs
5
Clock high time
4
—
PER_CLK
Cycle
6
Data setup time
0.0
—
ns
7
Start condition setup time (for repeated start condition only)
2
—
PER_CLK
Cycle
8
Stop condition setup time
2
—
PER_CLKCyc
le
1. I2C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1
ns (10% – 90%).
2. PER_CLK is the IPG Clock which drives the I2C BIU and module clock inputs. Typically this is 66 MHz. See the Clocking
Overview chapter in the device reference manual for more details.
Table 65. I2C output timing specifications — SCL and SDA 1, 2, 3, 4
No.
1
Parameter
Start condition hold
time
Min
6
Max
—
Unit
PER_CLK Cycle5
Table continues on the next page...
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Table 65. I2C output timing specifications — SCL and SDA 1, 2, 3, 4 (continued)
No.
Parameter
Min
Max
Unit
2
Clock low time
10
—
PER_CLK Cycle
3
Bus free time between 4.7
Start and Stop condition
—
μs
4
Data hold time
7
—
PER_CLK Cycle
5
Clock high time
10
—
PER_CLK Cycle
6
Data setup time
2
—
PER_CLK Cycle
7
Start condition setup
time (for repeated start
condition only)
20
—
PER_CLK Cycle
8
Stop condition setup
time
10
—
PER_CLK Cycle
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package
capacitance is accounted for, and does not need to be subtracted from the 25 pF value.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speedsand may
cause incorrect operation.
4. Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output
timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register.
5. PER_CLK is the IPG Clock which drives the I2C BIU and module clock inputs. Typically this is 66 MHz. See the Clocking
Overview chapter in the device reference manual for more details.
Figure 52. I2C input/output timing
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9.6.5 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface. A load of 50
pF is assumed.
Table 66. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed\high speed)
0
25\50
MHz
fpp
Clock frequency (MMC full speed\high speed)
0
20\50
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
4
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 53. SDHC timing
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Clocks and PLL Specifications
9.6.6 USB PHY specifications
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
The USB PHY meets the electrical compliance requirements defined in the Universal
Serial Bus Revision 2.0 OTG, USB Host with the amendments below (On-The-Go and
Embedded Host Supplement to the USB Revision 2.0 Specification is not applicable to
Host port).
• USB ENGINEERING CHANGE NOTICE
• Title: 5V Short Circuit Withstand Requirement Change
• Applies to: Universal Serial Bus Specification, Revision 2.0
• Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000
• USB ENGINEERING CHANGE NOTICE
• Title: Pull-up/Pull-down resistors
• Applies to: Universal Serial Bus Specification, Revision 2.0
• USB ENGINEERING CHANGE NOTICE
• Title: Suspend Current Limit Changes
• Applies to: Universal Serial Bus Specification, Revision 2.0
• On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
• Revision 2.0 plus errata and ecn June 4, 2010
• Battery Charging Specification (available from USB-IF)
• Revision 1.2, December 7, 2010
9.7 Clocks and PLL Specifications
9.7.1 24 MHz Oscillator Specifications
The system crystal oscillator consists of a Pierce-type structure running off the digital
supply. A straight forward biased-inverter implementation is used. The crystal must be
rated for a drive level of 250 μW or higher. An ESR (equivalent series resistance) of 80 Ω
or less is recommended to achieve a gain margin of 5.
Table 67. 24MHz external oscillator electrical characteristics
Symbol
Parameter
Condition
Value
Min
Typ
Unit
Max
fosc
Crystal oscillator range
—
—
24
—
MHz
Iosc
Startup current
—
—
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