T1022NXN7MQB

QorIQ Communications Platforms T Series i.MX 6SoloX — QorIQ applications T1040/20 processors and and could communication T1042/22 be on two lines processors The QorIQ T1 family of communications processors combines up to four 64-bit cores, built on Power Architecture® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required for networking and telecommunications. OVERVIEW TARGET MARKETS AND APPLICATIONS This scalable, pin-compatible family features the industry’s first 64-bit embedded processor with an integrated Gigabit Ethernet switch, the T1040 (and dual-core T1020), which simplifies hardware design, reduces power and overall system cost. The T1 family is ideally suited for use in mixed control and data plane applications such as fixed routers, switches, Internet access devices, firewall and other packet filtering applications, as well as general-purpose embedded computing. Its high level of integration offers significant performance benefits and greatly helps to simplify board design. }} Enterprise equipment: Fixed routers, Ethernet switches, UTM equipment }} Service provider: Edge routers, mobile backhaul }} Aerospace, defense and government: Ruggedized network appliances }} Industrial computing: Single board computers, factory automation, smart grid QorIQ T1040 AND T1042 COMMUNICATIONS PROCESSORS 256 KB Backside L2 Cache CoreNetTM Coherency Fabric 4x I2S 4x I2S Pattern Match Engine 2.0 Buffer Mgr. 1 GbE 1 GbE 1 GbE 1 GbE 8 Port Switch T1040/ 1 GbE 1 GbE 1 GbE 1 GbE T1020 1 GbE 1 GbE 1 GbE 1 GbE Only 2x USB 2.0 w/PHY Core Complex Complex (CPU, U2, L3 Cache) Accelerators and Memory Control Real-Time Debug Warchpoint Cross Trigger Perf. Monitor Trace Aurora 8-Lane 5 GHz SerDes DIU }} Up to 256 KB of shared platform cache (L3) QUICC Engine TDM/HDLC }} Tightly coupled low latency cache hierarchy 1 GbE T1042/T1022 Only T1040: 2x DMA, T1042: 4x DMA TDM/HDLC 2x DUART Peripheral Access Mgmt. Unit PAMU SAT A 2.0 Parse, Classify, Distribute Security 5.4 Queue (XoR CRC) Mgr. PAMU SAT A 2.0 PAMU PCle PAMU Power Management SDXC/eMMC 32/64-bit DDR3L/4 Memory Controller 256 KB Platform Cache 32 KB I Cache PCle e5500 Core Features }} 32 KB I/D (L1), 256 KB L2 per core 32 KB D Cache Security Fuse Processor Security Monitor }} Supports up to 1.5 GHz core frequencies Power Architecture® e5500 PCle The T1 family is based on the 64-bit e5500 Power Architecture core, which uses a seven-stage pipeline for low latency response to unpredictable code execution paths, boosting singlethreaded performance. PCle e5500 CORE Basic Peripherals and Interconnect Networking Elements }} 3.0 DMIPS/MHz per core }} Up to 64 GB of addressable memory space }} Hybrid 32-bit mode to support legacy software and seamless transition to 64-bit architecture T1 FAMILY FEATURE LIST Two or four e5500 single-threaded cores built on Power Architecture® technology • Three levels of instructions: User, supervisor, hypervisor • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture CoreNet platform cache • 256 KB shared platform cache Hierarchical interconnect fabric • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints VIRTUALIZATION The T1 family includes support for hardware-assisted virtualization. The e5500 core offers an extra core privilege level (hypervisor). Virtualization software for the T1 family includes kernelbased virtual machine (KVM), Linux® OS containers, NXP hypervisor and commercial virtualization software from Green Hills® Software and Enea®. • Up to 1.5 GHz with 64-bit ISA support • QMAN fabric supporting packet-level queue management and quality of service 64-bit DDR3L/4 SDRAM memory controller with ECC support • Up to 1600 MT/s • Packet parsing, classification and distribution DPAA incorporating acceleration for the following functions • Queue management for scheduling, packet sequencing and congestion management • Hardware buffer management for buffer allocation and de-allocation • Cryptography acceleration (SEC 5.x) DATA PATH ACCELERATION ARCHITECTURE (DPAA) SerDes The T1 family integrates the QorIQ DPAA, an innovative multicore infrastructure for scheduling work to cores (physical and virtual), hardware accelerators and network interfaces. Ethernet interfaces • Eight lanes at up to 5 Gb/s • Supports SGMII, QSGMII, PCI Express® and SATA • 8-port Gigabit Ethernet switch (available with T1040 and T1020 only) • Up to 5x 1 Gb/s Ethernet MACs QUICC Engine module • Support for legacy protocols TDM, HDLC, UART and ISDN High-speed peripheral interfaces • Four PCI Express 2.0 controllers • Two serial ATA (SATA 2.0) controllers • Two High-Speed USB 2.0 controllers with integrated PHYs • Enhanced secure digital host controller (SD/MMC/eMMC) DPAA HARDWARE ACCELERATORS Frame manager (FMAN) 13 Gb/s classify, parse and distribute Buffer manager (BMAN) 64 buffer pools Queue manager (QMAN) Security (SEC) Additional peripheral interfaces • Enhanced serial peripheral interface • Two I2C controllers • Four UARTS • Integrated flash controller supporting NAND and NOR flash memory DMA • Dual four channel Up to 2 queues Support for hardware virtualization and partitioning enforcement • Extra privileged level for hypervisor support 5 Gb/s: 3DES, AES QorIQ trust architecture • Secure boot, secure debug, tamper detection, volatile key storage 24 T1 FAMILY COMPARISON T1020 T1022 T1040 T1042 T2081 2 e5500 2 e5500 4 e5500 4 e5500 4 e6500 (dual threaded) 1200–1500 MHz 1200–1500 MHz 1200-1500 MHz 1200-1500 MHz 1200–1800 MHz 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3L/4 to 1600 MT/s 1x DDR3/3L to 2133 MT/s 10/100/1000 Ethernet (with IEEE® 1588v2) 8-port GbE switch + 4x 1 GbE 5x 1 GbE I8-port GbE switch + 4x 1 GbE 5x 1 GbE SerDes Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (5 GHz) Eight lanes (5 GHz) CPU DDR Interface Package 2x 1/10 GbE + 6x 1 GbE Eight lanes (10 GHz) Pin compatible The FMAN, a primary element of the DPAA, parses headers from incoming packets, then classifies and selects data buffers with optional policing and congestion management. The FMAN passes its work to the QMAN which assigns it to cores or accelerators with a multilevel scheduling hierarchy. is supported through three PCI Express® V2.0 controllers that support a variety of lane widths. Other peripherals include SATA, SD/MMC, I2C, UART, SPI, NOR/NAND controller, GPIO and a 1600 MT/s DDR3L/4 controller. GIGABIT ETHERNET SWITCH }} CodeWarrior Development Studio for Power Architecture The T1040 and T1020 processors include an integrated gigabit Ethernet switch that supports wire-speed switching for all packet sizes. Other features include VLAN, QoS processing and ACLs. }} NXP Linux SDK SYSTEM PERIPHERALS AND NETWORKING For networking, the FMAN supports up to five 1 Gb/s MAC controllers that connect to PHYs, switches and backplanes over RGMII and SGMII. The T1040 and T1020 processors also include an integrated 8-port Gigabit Ethernet switch, which supports QSGMII or SGMII interfaces. High-speed system expansion SOFTWARE AND TOOL SUPPORT NXP and our partner network deliver a wide range of tools, run-time software, reference solutions and services to accelerate your designs. }} QorIQ reference design boards }} Reference Platforms –– Enterprise WLAN Access Point –– VortiQa Application Software –– AIS–Application Identification Software –– Enterprise Software for Networking –– ONS–Open Network Switch Software –– OND–Open Network Director Software }} Professional Services & Support –– Commercial Services –– Linux SDK Support Package –– Reference Design Software (RDS) Support Package }} Third Party Software and Tools –– Enea, Green Hills, Mentor Graphics and Wind River www.nxp.com/QorIQ NXP, the NXP logo, and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet and QUICC Engine are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2012, 2013-2016 NXP B.V. Document Number: T1FAMILYFS REV 2