T2081NXN8T1B

QorIQ Communications Platforms T Series i.MX 6SoloX — QorIQ applications T2080 and processors T2081 and could be onprocessors communication two lines The 28 nm QorIQ T2080 and T2081 communications processors bring the architectural innovations of the T series flagship T4240, such as the 1.8 GHz dual-threaded e6500 core, into an eight virtual core mid-range platform at reduced power and price points. OVERVIEW The T2080 processor is primarily intended to succeed our successful P3041 and P2041 mid-range series of quad-core devices as a control plane or integrated control and data plane processor. It provides an excellent migration path, as it offers 2x or better in core capability, cache size, SerDes bandwidth and Ethernet connectivity within a similar power budget. It also provides a value engineering opportunity for P4080 customers, as T2080 provides equivalent performance at much lower price and power. The T2081 is a smaller package version of the T2080, which is pin compatible with the quad-core T1042. This provides T1042 customers an easy upgrade to higher performance if processing requirements increase. It also enables customers to reuse a single board for two different product performance levels. TARGET MARKETS AND APPLICATIONS The T2080 and T2081 processors are targeted at mid-range control plane applications or mixed control and data plane applications. The highly efficient eight virtual core device achieves up to 1.8 GHz even while maintaining a short sevenstage pipeline for better latency response to unpredictable control plane code branches. Advanced virtualization technology facilitates safe partitioning of control and data plane applications within the device. }} Enterprise equipment: Modular Ethernet switches, services cards, UTM equipment, enterprise storage, data center }} Service provider: Core and edge routers, broadband access, metro Ethernet, optical networking }} Wireless infrastructure: Mobile backhaul, NICs, channel cards, control cards in LTE, WCDMA, GSM, WiMAX }} Aerospace and defense: ruggedized or highly secure routers, avionics networking, instrumentation panels, military SBCs }} Industrial computing: SBCs, factory automation, test and measurement Power™ e6500 32 KB D-Cache T2 T1 32 KB I-Cache 32 KB D-Cache 32 KB I-Cache T1 T2 Power™ e6500 32 KB D-Cache 32 KB I-Cache 2MB Banked L2 Security Fuse Processor Security 5.2 (XoR, CRC) Queue Mgr. PME 2.1 RMan Buffer Mgr. Parse, Classify, Distribute HiGig/+ 4x I2C SPI, GPIO DCB Frame Manager 4x 1 / 2.5 / 10G 2x USB2.0 + PHY 8-Lane Core Complex Complex (CPU, L2, L3 Cache) Accelerators and Memory Control Peripheral Access Mgmt Unit 4x 1 / 2.5G 10 GHz SerDes PAMU Real-Time Debug 8ch DMA 8ch DMA 8ch DMA SAT A 2.0 2x DUART DCE 1.0 PAMU SAT A 2.0 IFC sRIO PAMU Power Management SDXC/eMMC 64-bit DDR3/3L Memory Controller 512KB Platform Cache Coherency Fabric Security Monitor Warchpoint Cross Trigger Perf. Monitor CoreNet Trace Aurora 8-Lane 8 GHz SerDes Basic Peripherals and Interconnect Networking Elements T2080 VS. T2081 DIFFERENCES T2080 T2081 16 8 PCIe 2x Gen3 + 2x Gen2 1x Gen3 + 3x Gen2 SRIO 2 + RMan No SATA 2 No Yes No 10 Gb/s MACs Up to four, with XFI, XAUI, HiGig Up to 2x XFI 1 Gb/s MACs Up to eight Up to seven 25 x 25mm, 896 pins, 0.8 mm pitch 23 x 23mm, 780 pins, 0.8 mm pitch, pin compatible with T1042 VIRTUALIZATION TThe T2080 and T2081 processors include support for hardware-assisted virtualization. The e6500 core offers an extra core privilege level (hypervisor) and hardware offload of logical to real address translation. In addition, the T2080 and T2081 include platformlevel enhancements such as SR-IOV and I/O virtualization with DMA memory protection through IOMMUs and configurable “storage profiles,” which provide isolation of I/O buffers between guest environments. Virtualization software for the T2080 and T2081 processors includes kernel virtualization model (KVM), Linux® containers and the NXP hypervisor. T2 Power™ e6500 sRIO 32 KB I-Cache T1 Pre-fetch 32 KB D-Cache T2 PCle Power™ e6500 PCle The four e6500 dual-threaded cores share a low-latency backside 2 MB L2 cache, allowing efficient sharing of code and data. Each e6500 core implements the NXP AltiVec technology-based SIMD engine, dramatically boosting the performance of media and networking algorithms, offering native inline programming and using less power than a separate DSP. T1 PCle The T2080 and T2081 processors are based on the 64-bit e6500 core, built on Power Architecture® technology, and run up to 1.8 GHz. The e6500 core also offers higher aggregate instructions per clock at lower power with an innovative “fused core” approach to threading. The e6500’s fully resourced dual threads provide 1.7 times the performance of a single thread. QorIQ T2080 COMMUNICATIONS PROCESSOR PCle E6500 CORE SerDes Aurora Package DATA PATH ACCELERATION ARCHITECTURE (DPAA) The T2080 and T2081 processors integrate the QorIQ DPAA, an innovative multicore infrastructure for scheduling work to cores (physical and virtual), hardware accelerators and network interfaces. The FMAN, a primary element of the DPAA, parses headers from incoming packets and classifies and selects data buffers with optional policing and congestion management. The FMAN passes its work to the QMAN, which assigns it to cores or accelerators with a multi-level scheduling hierarchy, while maintaining packet ordering. The BMAN manages allocation and de-allocation of packet buffers. The T2080 and T2081’s implementation of DPAA offers accelerators for cryptography, deep packet inspection and compression decompression. SOFTWARE AND TOOL SUPPORT T2080 AND T2081 FEATURES LIST NXP and our partner network deliver a wide range of tools, run-time software, reference solutions and services to accelerate your designs. Four dual-threaded e6500 cores built on Power Architecture® technology }} QorIQ T2080 reference design board (T2080RDB) CoreNet platform cache • 512 KB shared platform cache with prefetch engine }} CodeWarrior Development Studio for Power Architecture Hierarchical interconnect fabric • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints }} NXP Linux SDK Memory controller • Up to 1.8 GHz, 6.0 DMIPS/MHz per core –– Enterprise Software for Networking DPAA incorporating acceleration for the following functions • 72-bit width including ECC • Hardware buffer management for buffer allocation and de-allocation with 64 buffer pools (BMAN) • Cryptography acceleration to 10 Gb/s (SEC) • Decompression/compression acceleration at up to 17.5 Gb/s (DCE) • DPAA chip-to-chip interconnect via RapidIO® message manager (RMAN) (T2080 only) • Pattern matching acceleration to 10 Gb/s (PME) SerDes • 16 lanes at up to 10 GHz (8 on T2081) • Quality of service: Egress traffic shaping and priority flow control for data center bridging in converged data center applications • 8 MACs (7 on T2081), multiplexed over the following options: –– Commercial Services Ethernet interfaces • Up to four 10 Gb/s MACs supporting XFI/KR, XAUI and HiGig • (two on T2081 supporting XFI/KR only) • Up to eight 1 Gb/s MACs (5 on T2080) supporting SGMII –– Reference Design Software (RDS) Support Package • Up to two 2.5 Gb/s SGMII • Up to two RGMII • Two PCI Express 3.0 controllers (one on T2081) }} Third Party Software and Tools –– Enea, Green Hills, Mentor Graphics and Wind River • 64-bit DDR3/3L SDRAM up to 2133 MT/s • Queue management for scheduling, packet sequencing and congestion management of up to 224 queues (QMAN) }} Professional Services & Support –– Linux SDK Support Package • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture • Packet parsing, classification and distribution to 24 Gb/s (FMAN) –– VortiQa open network switch software –– VortiQa open network director software • Three levels of instructions: User, supervisor, hypervisor • Advanced power saving modes include state retention power gating }} VortiQa Application Software –– VortiQa Application Identification Software (AIS) • Shares a 2 MB L2 cache High-speed peripheral interfaces • Two PCI Express 2.0 controllers (three on T2081) • Endpoint SR-IOV • Two Serial RapidIO 2.1 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support (T2080 only) • Two serial ATA (SATA 2.0) controllers (T2080 only) • Two High-Speed USB 2.0 controllers with integrated PHYs Additional peripheral interfaces • Enhanced secure digital host controller (SD/MMC/eMMC) • Enhanced serial peripheral interface • Four I2C controllers • Four UARTS • Integrated flash controller supporting NAND and NOR flash memory DMA • Dual eight channel • Extra privileged level for hypervisor support • Logical to real address translation Support for hardware virtualization and partitioning enforcement • Virtual core aware MMU/TLB • vMPIC (virtualized interrupt controller)/virtual core capable PPC cores • vDMA (user level DMA engine) • PAMU v2 (I/O MMU supporting paging) • DPAA (Ethernet MAC virtualization, accelerator virtualization) QorIQ trust architecture • Secure boot, secure debug, tamper detection (T2080 only), volatile key storage, alternate image and key revocation www.nxp.com/QorIQ NXP, the NXP logo, AltiVec, CodeWarrior and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © 2014, 2016 NXP B.V. Document Number: T2080FS REV 2