TDA8444AT/N4,112

INTEGRATED CIRCUITS DATA SHEET TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus Product specification Supersedes data of March 1991 File under Integrated Circuits, IC01 1999 Apr 29 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus FEATURES • Eight DACs with 6-bit resolution • Adjustable common output swing • Push-pull outputs • Outputs short-circuit protected • Three programmable slave address bits The TDA8444 contains eight programmable 6-bit DAC outputs, an I2C-bus slave receiver with three (two for SO16) programmable address bits and one input (VMAX) to set the maximum output voltage. Each DAC can be programmed separately by a 6-bit word to 64 values, but VMAX determines the maximum output voltage for all DACs. The resolution will be approximately 1⁄64VMAX. • Large supply voltage range • Low temperature coefficient. GENERAL DESCRIPTION The interface circuit is a bipolar IC in a DIP16, SO16, or SO20 package made in an I2L-compatible 18 V process. At power-on all DACs are set to their lowest value. QUICK REFERENCE DATA SYMBOL PARAMETER VCC supply voltage ICC supply current P VVMAX Vo(DACn) DAC output voltage CONDITIONS MIN. TYP. MAX. UNIT 4.5 12 13.2 V − 14 − mA power dissipation − 170 − mW input effective voltage 1 − VCC − 2.0 V 0.1 − VCC − 0.5 V VCC = 12 V VMAX = VCC Vo(DACn)(max) maximum DAC output voltage 1 < VMAX < VCC − 2.0 − VMAX + 0.3 − V Isource(min) minimum DAC source current data = 1FH 2 − − mA Isink(min) minimum DAC sink current data = 1FH 2 − − mA ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA8444 DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 TDA8444T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 TDA8444AT SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1999 Apr 29 2 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus BLOCK DIAGRAM A0 handbook, full pagewidth A1 5 SDA SCL VMAX A2 6 7 VCC VEE 1 8 3 4 I2C BUS SLAVE RECEIVER TDA8444 REFERENCE VOLTAGE GENERATOR 2 DAC0 9 DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 10 11 12 13 14 15 16 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 MGH513 Fig.1 Block diagram. 1999 Apr 29 3 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus PINNING PIN SYMBOL DESCRIPTION TDA8444 (DIP16) TDA8444T (SO16) TDA8444AT (SO20) VCC 1 1 1 supply voltage VMAX 2 2 2 control input for DAC maximum output voltage SDA 3 3 3 I2C-bus serial data input/output SCL 4 4 4 I2C-bus serial clock A0 5 6 7 programmable address bit 0 for I2C-bus slave receiver A1 6 7 8 programmable address bit 1 for I2C-bus slave receiver A2 7 − 9 programmable address bit 2 for I2C-bus slave receiver VEE 8 8 10 ground DAC0 9 9 11 analog voltage output 0 DAC1 10 10 13 analog voltage output 1 DAC2 11 11 14 analog voltage output 2 DAC3 12 12 15 analog voltage output 3 DAC4 13 13 16 analog voltage output 4 DAC5 14 14 17 analog voltage output 5 DAC6 15 15 18 analog voltage output 6 DAC7 16 16 20 analog voltage output 7 n.c. − 5 5, 6, 12, 19 handbook, halfpage not connected handbook, halfpage VCC 1 16 DAC7 VCC 1 16 DAC7 VMAX 2 15 DAC6 VMAX 2 15 DAC6 SDA 3 14 DAC5 SDA 3 14 DAC5 13 DAC4 SCL 4 SCL 4 TDA8444 A0 5 12 DAC3 n.c. 5 12 DAC3 A1 6 11 DAC2 A0 6 11 DAC2 A2 7 10 DAC1 A1 7 10 DAC1 VEE 8 9 DAC0 VEE 8 MGH512 9 DAC0 MGL531 Fig.2 Pin configuration (TDA8444; DIP16). 1999 Apr 29 13 DAC4 TDA8444T Fig.3 Pin configuration (TDA8444T; SO16). 4 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus handbook, halfpage VCC 1 20 DAC7 VMAX 2 19 n.c. SDA 3 18 DAC6 SCL 4 17 DAC5 n.c. 5 16 DAC4 TDA8444AT n.c. 6 15 DAC3 A0 7 14 DAC2 A1 8 13 DAC1 A2 9 12 n.c. VEE 10 11 DAC0 MGL532 Fig.4 Pin configuration (TDA8444AT; SO20). FUNCTIONAL DESCRIPTION I2C-bus interface The I2C-bus interface is a receive-only slave, which accepts data according the format shown in Table 1. Table 1 S I2C-bus format (see note 1) 0 1 0 0 A2 A1 A0 0 A I3 I2 I1 I0 SD SC SB SA A X X D5 D4 D3 D2 D1 D0 A P Note 1. S = START condition; A2 to A0 = programmable address bits; A = Acknowledge; I3 to I0 = Instruction bits; SD to SA = subaddress bits; X = don’t care; D5 to D0 = data bits; P = STOP condition. Valid addresses are: TDA8444 and TDA8444AT: 40H, 42H, 44H, 46H, 48H, 4AH, 4CH and 4EH TDA8444T: 48H, 4AH, 4CH and 4EH (A2 is always logic 1). All other addresses cannot be acknowledged by the circuit. The actual slave address depends on the programmable address bits A2, A1 and A0. This way up to eight circuits can be used on one I2C-bus. Valid instructions are: 00H to 0FH; F0H to FFH. 1999 Apr 29 5 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus connected between these pins and VEE. This means that normal bus line voltage should not exceed 5.5 V. The circuit will not react to other combinations of the 4 instruction bits I3 to I0 than 0 or F, but will still generate an acknowledge. The difference between instruction 0 and F is only important when more than one data byte is sent within one transmission. Instruction 0 causes the data bytes to be written into the DAC-latches with consecutive subaddresses starting with the subaddress given in the instruction byte (auto-increment of subaddress), while instruction F will cause a consecutive writing of the data bytes into the same DAC-latch whose subaddress was given in the instruction byte. In case of only one data byte the DAC-latch with the subaddress equal to the subaddress in the instruction byte will receive the data. The address inputs A0, A1 and A2 can be easily programmed by either a connection to VEE (An = 0) or VCC (An = 1). If the inputs are left floating the result will be An = 1. VMAX The VMAX input gives a means of compressing the DAC output voltage swing. The maximum DAC output voltage will be equal to VMAX + VDAC(min), while the 6-bit resolution is maintained. This enables a higher voltage resolution for smaller output swings. Valid subaddresses are: 0H to 7H. DACs The subaddresses correspond to DAC0 to DAC7. The Auto-Increment (AI) function of instruction 0, however, works on all possible subaddresses 0 to F in such a way that next to subaddress F, subaddress 0 will follow, and so on. The DACs consist of a 6-bit data-latch, current switches and an opamp. The current sources connected to the switches have values with weights 20 to 25. The sum of the switched on currents is converted by the opamp into a voltage between approximately 0.5 and 10.5 V if VMAX = VCC = 12 V. The DAC outputs are short-circuit protected against VCC and VEE. Capacitive load on the DAC outputs should not exceed 2 nF in order to prevent possible oscillations at certain levels. The temperature coefficient for each of the outputs remains in all possible conditions well below 0.1 LSB per Kelvin. The data will be latched into the DAC-latch on the positive-going edge of the acknowledge related clock pulse. The specification of the SCL and SDA I/O meets the I2C-bus specification. For protection against positive voltage pulses on pins 3 and 4, zener diodes are LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCC supply voltage −0.5 +18 V ICC supply current −10 +40 mA P(max) maximum power dissipation − 500 mW Vi(n) input voltage −0.5 +5.9 V pins SDA and SCL −0.5 +5.9 V pins VMAX, A0 to A2 and DAC0 to DAC7 −0.5 VCC + 0.5 V In current in all pins except VCC and VEE − ±10 mA Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −20 +70 °C QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. 1999 Apr 29 6 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 75 K/W in free air TDA8444 TDA8444T note 1 100 K/W TDA8444AT note 1 85 K/W MAX. UNIT Note 1. When mounted on a Printed-Circuit Board (PCB). CHARACTERISTICS VCC = 12 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. Supply VCC supply voltage ICC supply current P Vrst 4.5 12 13.2 V 12 14 19 mA power dissipation − 170 250 mW power reset voltage 1 − 4 V Vi(VMAX) input effective voltage 1 − VCC − 2.0 V Ii input current VMAX = VCC − − 10 µA VMAX = 1 V − − 10 µA V VMAX = VCC = 12 V; data = 00H Pin VMAX Pins SDA and SCL VI input voltage 0 − 5.5 VIL LOW-level input voltage − − 1.0 V VIH HIGH-level input voltage 3.0 − − V IIL LOW-level input current VSDA = VSCL = −0.3 V − − −10 µA IIH HIGH-level input current VSDA = VSCL = 6 V − − ±10 µA VOL LOW-level output voltage IL = 3 mA − − 0.4 V Io(sink) output sink current 3 8 − mA V PIN SDA Address bits (A0 to A2) VI input voltage 0 − VCC VIL LOW-level input voltage − − 1.0 V VIH HIGH-level input voltage 2.2 − − V IIL LOW-level input current VAn = VEE −10 −15 − µA IIH HIGH-level input current VAn = VCC − − 1 µA 1999 Apr 29 7 Philips Semiconductors Product specification TDA8444; TDA8444T; TDA8444AT Octuple 6-bit DACs with I2C-bus SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DACs (DAC0 to DAC7) Vo DAC output voltage VMAX = VCC 0.1 − VCC − 0.5 V Vo(min) minimum output voltage data = 00H; IL = −2 mA 0.1 0.28 0.5 V Vo(max) maximum output voltage data = 3FH; IL = −2 mA VMAX = VCC 10.0 10.5 11.5 V 1 < VMAX < 10 V − note 1 − V Io(sink) output sink current VDAC = VCC; data = 1FH 2 8 15 mA Io(source) output source current VDAC = VEE; data = 1FH −2 − −6 mA Zo output impedance −2 ≤ IL ≤ +2 mA; data = 1FH − 4 50 Ω DNL differential non-linearity VMAX = VCC; IL = −2 mA − − ±0.5 LSB INL integral non-linearity VMAX = VCC; IL = −2 mA − − ±0.5 LSB ∆GFS DC gain match at full-scale data = 3FH; IL = −2 mA − − 5 % ∆G/∆data DC gain versus other DAC data change data = 3FH; IL = −2 mA −