TDA8706AM/C3,118

INTEGRATED CIRCUITS DATA SHEET TDA8706A 6-bit analog-to-digital converter with multiplexer and clamp Product specification Supersedes data of 1996 Jul 30 2003 Jul 21 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A FEATURES APPLICATIONS • 6-bit resolution • General purpose video applications • Binary CMOS compatible outputs • R, G and B signals • CMOS compatible digital inputs • Automotive (car navigation) • TLL clock input • LCD systems • Three multiplexed video inputs • Frame grabber. • R, G and B clamps on code 0 • Single 6-bit Analog-to-Digital Converter (ADC) operation allowed up to 40 MSPS GENERAL DESCRIPTION The TDA8706A is a 6-bit ADC with three analog multiplexed inputs. Each input has an analog clamp on code 0 for RGB video processing. Clamping level can also be adjusted externally up to code 20. It can also be used as a single 6-bit ADC. • External control of clamping level • Internal reference voltage (external reference allowed) • Power dissipation only 36 mW (typical) • Operating temperature of −40 to +85 °C • Operating between 2.7 and 3.6 V • Sine wave clock allowed. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 2.7 3.3 3.6 V VDDD digital supply voltage 2.7 3.3 3.6 V VDDO output stage supply voltage 2.7 3.3 3.6 V IDDA analog supply current − 6.4 10 mA IDDD digital supply current − 4.4 8.5 mA IDDO output stage supply current fclk = 40 MHz; ramp input − − 1.8 mA INL integral non-linearity fclk = 40 MHz; ramp input − ±0.20 ±0.5 LSB DNL differential non-linearity fclk = 40 MHz; ramp input − ±0.10 ±0.35 LSB fclk(max) maximum clock frequency 40 − − MHz Ptot total power dissipation − 36 73 mW fclk = 40 MHz; ramp input ORDERING INFORMATION TYPE NUMBER TDA8706AM 2003 Jul 21 PACKAGE NAME DESCRIPTION VERSION SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 2 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A BLOCK DIAGRAM VCLPR handbook, full pagewidth VCLPB VCLPG 11 12 13 CLP CLK 24 20 D5 CLAMP 4 19 D4 RED 18 D3 8 6-BIT ADC MULTIPLEXER GREEN CMOS OUTPUTS 17 D2 9 16 D1 BLUE 10 15 D0 TDA8706A VSSD 22 VDDA 21 5 23 1 VDDO VDDA VDDD SR REGULATOR 2 3 6 SG SB VRB select inputs Fig.1 Block diagram. 2003 Jul 21 3 7 VSSA 14 VSSO MGD133 digital voltage outputs Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A PINNING SYMBOL PIN DESCRIPTION SR 1 select input RED SG 2 select input GREEN SB 3 select input BLUE CLP 4 clamping pulse input (positive pulse) VDDA 5 analog supply voltage SR 1 24 CLK VRB 6 reference voltage BOTTOM output SG 2 23 VDDD VSSA 7 analog ground SB 3 22 VSSD RED 8 RED input CLP 4 21 VDDO GREEN 9 GREEN input 20 D5 10 BLUE input VDDA 5 BLUE VCLPR 11 RED clamping voltage level input VRB 6 VCLPB 12 BLUE clamping voltage level input VSSA 7 18 D3 VCLPG 13 GREEN clamping voltage level input RED 8 17 D2 VSSO 14 output stage ground GREEN 9 16 D1 D0 15 digital voltage output; bit 0 (LSB) BLUE 10 15 D0 D1 16 digital voltage output; bit 1 D2 17 digital voltage output; bit 2 D3 18 digital voltage output; bit 3 D4 19 digital voltage output; bit 4 D5 20 digital voltage output; bit 5 VDDO 21 output stage supply voltage VSSD 22 digital ground VDDD 23 digital supply voltage CLK 24 clock input 2003 Jul 21 handbook, halfpage 19 D4 TDA8706AM VCLPR 11 14 VSSO VCLPB 12 13 VCLPG MGD132 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage −0.3 +7.0 V VDDD digital supply voltage −0.3 +7.0 V ∆VDD supply voltage difference VDDA − VDDD −1.0 +1.0 V VDDA − VDDO −1.0 +1.0 V VDDD − VDDO −1.0 +1.0 V VI input voltage −0.3 +7.0 V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C Tj junction temperature − 150 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 119 K/W CHARACTERISTICS VDDA = 2.7 to 3.6 V; VDDD = 2.7 to 3.6 V; VDDO = 2.7 to 3.6 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 0.7 V; Tamb = −40 to +85 °C; typical values measured at VDDA = VDDD = VDDO = 3.3 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA analog supply voltage 2.7 3.3 3.6 V VDDD digital supply voltage 2.7 3.3 3.6 V VDDO output stage supply voltage 2.7 3.3 3.6 V ∆VDD supply voltage difference VDDA − VDDD −0.3 − +0.3 V VDDA − VDDO −0.3 − +0.3 V VDDD − VDDO −0.3 − +0.3 V IDDA analog supply current − 6.4 10 mA IDDD digital supply current − 4.4 8.5 mA IDDO output stage supply current − − 1.8 mA 2003 Jul 21 fclk = 40 MHz; ramp input 5 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp SYMBOL Ptot PARAMETER TDA8706A CONDITIONS total power dissipation MIN. TYP. MAX. UNIT − 36 73 mW Inputs CLOCK INPUT CLK (REFERENCED TO VSSD); note 1 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VDDD V IIL LOW-level input current Vclk = 0.8 V −1 0 +1 µA IIH HIGH-level input current Vclk = 2.0 V − 2 10 µA Zi input impedance fclk = 40 MHz − 4 − kΩ Ci input capacitance fclk = 40 MHz − 3 − pF INPUTS SR, SG, SB AND CLP (REFERENCED TO VSSD) VIL LOW-level input voltage 0 − VDDD × 0.3 V VIH HIGH-level input voltage VDDD × 0.7 − VDDD V IIL LOW-level input current VIL = VDDD × 0.2 −1 − − µA IIH HIGH-level input current VIH = VDDD × 0.8 − − +1 µA INPUTS VCLPR, VCLPG AND VCLPB (REFERENCED TO VSSA); see Tables 1 and 2 VCLP input voltage for clamping Vcode(−9) − Vcode(20) V ICLP input current − − 30 µA ACLP clamp accuracy − +1 LSB −1 between inputs RED, GREEN and BLUE of each device; Tamb = 25 °C ANALOG INPUTS RED, GREEN AND BLUE; see Table 1 Vi(p-p) input voltage amplitude (peak-to-peak value) 0.63 0.70 0.77 V Ii input current − − 10 µA Cclamp clamp coupling capacitance 1 10 100 nF Reference voltages for the resistor ladder; see Table 1 VRB VDDA − 1.29 VDDA − 1.21 VDDA − 1.13 V BOTTOM reference voltage Outputs DIGITAL OUTPUTS D5 TO D0 (REFERENCED TO VSSD) VOL LOW-level output voltage IO = 1 mA 0 − 0.5 V VOH HIGH-level output voltage IO = −1 mA VDDO − 0.5 − VDDO V Switching characteristics CLOCK INPUT CLK; see Fig.3; note 1 fclk(max) maximum clock frequency 40 − − MHz fmux(max) maximum multiplexer frequency 20 − − MHz tCPH clock pulse width HIGH 9 − − ns tCPL clock pulse width LOW 9 − − ns 2003 Jul 21 6 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp SYMBOL PARAMETER TDA8706A CONDITIONS MIN. TYP. MAX. UNIT tr clock rise time 10% to 90%; fclk ≤ 40 MHz; − LOW = 0.8 V, HIGH = 2.0 V − 7 ns tf clock fall time 90% to 10%; fclk ≤ 40 MHz; − LOW = 0.8 V, HIGH = 2.0 V − 7 ns Analog signal processing LINEARITY INL integral non-linearity fclk = 40 MHz; ramp input − ±0.20 ±0.5 LSB DNL differential non-linearity fclk = 40 MHz; ramp input − ±0.10 ±0.35 LSB fclk = 40 MHz; fi = 4.43 MHz 5.5 5.8 − bits − − 7 ns EFFECTIVE BITS; note 2 EB effective bits Timing (fclk = 40 MHz; CL = 10 pF); see Fig.3 OUTPUT DATA; note 3 tds sampling delay time th output hold time 6.5 9.0 − ns td output delay time − 12 19 ns SELECT INPUT SIGNALS SR, SG, SB AND CLP set-up time SR, SG and SB with no overlap; see Fig.3 10 − − ns with overlap; see Fig.4 − − − ns tr rise time SR, SG and SB 10% to 90% 4 6 − ns tf fall time SR, SG and SB 90% to 10% 4 6 − ns tover RED, GREEN and BLUE (active) overlap time with respect to select signals SR, SG and SB see Fig.4 0 − − ns tCLPP clamp pulse time CCLP = 10 nF − 3 − µs tMH multiplexer hold time SR, SG and SB 9 − − ns tsu Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. A sine wave with specified amplitude is also allowed. 2. Effective bits are derived from a Fast Fourier Transform (FFT) processing taking 2K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 3. Output data acquisition: the output data is available after the maximum delay time td. 2003 Jul 21 7 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp Table 1 TDA8706A Output coding and input voltage (typical values); VDDA = VDDD = 3.3 V BINARY OUTPUT BITS Vi (V) STEP Table 2 D5 D4 D3 D2 D1 D0 Underflow VDDA − 0.42 1 1 1 1 1 1 Clamping input level (VCLPR, VCLPG and VCLPB) VCLPR, VCLPG, VCLPB CLAMPING LEVEL Open-circuit(1) code 0 Vcode(−9) to Vcode(20) code −9 to code 20 Note 1. Use capacitor ≥10 pF to VSSA. Table 3 Clamp and inputs RED, GREEN and BLUE; VDDA = VDDD = VDDO = 3.3 V SR or SG or SB CLAMP 0 1 1 2003 Jul 21 VCLPR, VCLPG or VCLPB Vi RED or GREEN or BLUE open VDDA − 1.12 V VCLP VCLP open VDDA − 1.12 V 0 VCLP VCLP code (VCLP) 8 DIGITAL OUTPUTS don’t care Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth TDA8706A tCPH tCPL CLK 1.4 V tSU tMH SR SG SB CLAMP tCLPP OUTPUT DATA GREEN td BLUE RED GREEN th MBE859 Fig.3 AC characteristics select signals, clamp and output data. 2003 Jul 21 9 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth TDA8706A CLK SR SG SB tover RED ACTIVE tover GREEN ACTIVE tsu tover BLUE ACTIVE MBE860 Fig.4 Anti-overlap system for analog multiplexer. handbook, full pagewidth RED, GREEN, BLUE (SR, SG, SB inputs) digital outputs = 000000 1 CLAMP input 0 MBE861 Fig.5 AC characteristics select signals; clamp and data. 2003 Jul 21 10 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A INTERNAL PIN CONFIGURATIONS handbook, halfpage handbook, halfpage VDDA VDDO RLAD REGULATOR VRB D5 to D0 VSSO VSSA MGD134 MBE967 Fig.6 CMOS data outputs pins D0 to D5. Fig.7 Output pin VRB. handbook, V halfpage DDD 1.4 V CLK VSSD MGX350 Fig.8 Input pin CLK. 2003 Jul 21 11 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A APPLICATION INFORMATION handbook, full pagewidth SR SG SB CLP VDDA VRB(1) VSSA 100 nF VSSA 100 nF RED GREEN BLUE VCLPR(2) VCLPB(2) 100 nF VSSA 1 24 2 23 3 22 4 21 5 20 19 6 TDA8706A 7 18 8 17 9 16 10 15 11 14 12 13 100 nF MBE969 VSSA CLK VDDD(3) VSSD VDDO 100 nF (3) D5 100 nF D4 D3 D2 D1 D0 VSSO VCLPG(2) 100 nF VSSA The analog and digital supplies should be separated and decoupled. VDDO should be well decoupled with its capacitor in order to be as close as possible to its pin. VRB must not be connected to VCLPR, VCLPB or VCLPG pins. For applications where the black level is clamped to code 0, VCLPR, VCLPB and VCLPG must be left open-circuit with their respective decoupling capacitors. In that event, they may also be connected together in order to use only one single decoupling capacitor. (1) VRB is decoupled to VSSA. An external regulator can also be connected to VRB. (2) VCLPR, VCLPB and VCLPG are decoupled to VSSA. External voltages can also be forced on VCLPR, VCLPB and VCLPG. (3) VDDO and VDDO can be shorted together but the decoupling capacitors should remain as close as possible to its pin. Fig.9 Application diagram. 2003 Jul 21 12 Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A PACKAGE OUTLINE SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 0o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 2003 Jul 21 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 13 o Philips Semiconductors Product specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706A If wave soldering is used the following conditions must be observed for optimal results: SOLDERING Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness