TDA8763M/5/C4,118

INTEGRATED CIRCUITS DATA SHEET TDA8763 10-bit high-speed low-power ADC with internal reference regulator Product specification Supersedes data of 1997 Feb 10 File under Integrated Circuits, IC02 1999 Jan 06 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 FEATURES APPLICATIONS • 10-bit resolution High-speed analog-to-digital conversion for: • Sampling rate up to 50 MHz • Video data digitizing • DC sampling allowed • Radar pulse analysis • One clock cycle conversion only • Transient signal analysis • High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) • High energy physics research • Σ∆ modulators • Medical imaging. • No missing codes guaranteed • In-Range (IR) CMOS output GENERAL DESCRIPTION • Levels TTL and CMOS compatible digital inputs The TDA8763 is a 10-bit high-speed low-power Analog-to-Digital Converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed. • 3 to 5 V CMOS digital outputs • Low-level AC clock input signal allowed • Internal reference voltage regulator • Power dissipation only 235 mW (typical) • Low analog input capacitance, no buffer amplifier required The device includes an internal voltage reference regulator. If the application requires that the reference is driven via external sources the recommendation is to use the TDA8763A. • No sample-and-hold circuit required. ORDERING INFORMATION TYPE NUMBER TDA8763M/3 PACKAGE NAME SSOP28 TDA8763M/4 SSOP28 TDA8763M/5 SSOP28 1999 Jan 06 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 2 VERSION SAMPLING FREQUENCY (MHz) SOT341-1 30 SOT341-1 40 SOT341-1 50 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 3.0 3.3 5.25 V ICCA analog supply current − 30 35 mA ICCD digital supply current − 16 21 mA ICCO output stages supply current fclk = 40 MHz; ramp input − 1 2 mA INL integral non-linearity fclk = 40 MHz; ramp input − ±0.8 ±2.0 LSB DNL differential non-linearity fclk = 40 MHz; ramp input − ±0.5 ±0.9 LSB fclk(max) maximum clock frequency 30 − − MHz TDA8763M/3 Ptot 1999 Jan 06 TDA8763M/4 40 − − MHz TDA8763M/5 50 − − MHz − 235 305 mW total power dissipation fclk = 40 MHz; ramp input 3 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 BLOCK DIAGRAM handbook, full pagewidth V CCA DEC CLK VCCD2 OE 3 5 1 11 10 REFERENCE VOLTAGE REGULATOR VRT 2 CLOCK DRIVER TC TDA8763 9 25 D9 MSB 24 D8 23 D7 22 D6 RLAD analog voltage input 21 D5 VI 8 VRM 7 ANALOG -TO - DIGITAL CONVERTER LATCHES CMOS OUTPUTS data outputs 20 D4 19 D3 18 D2 17 D1 16 D0 13 VRB 6 IN-RANGE LATCH CMOS OUTPUT 26 LSB VCCO IR output 28 4 AGND analog ground 12 14 OGND DGND2 digital ground output ground Fig.1 Block diagram. 1999 Jan 06 4 VCCD1 27 DGND1 digital ground MBE553 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 PINNING SYMBOL PIN DESCRIPTION CLK 1 clock input TC 2 two’s complement input (active LOW) VCCA 3 analog supply voltage (+5 V) AGND 4 analog ground DEC 5 decoupling input VRB 6 reference voltage BOTTOM input VRM 7 reference voltage MIDDLE input VI 8 analog input voltage VRT 9 reference voltage TOP input OE 10 output enable input (CMOS level input, active LOW) VCCD2 11 DGND2 VCCO handbook, halfpage CLK 1 28 VCCD1 TC 2 27 DGND1 VCCA 3 26 IR AGND 4 25 D9 digital supply voltage 2 (+5 V) DEC 5 24 D8 12 digital ground 2 VRB 6 23 D7 13 supply voltage for output stages (3 to 5 V) VRM 7 VI 8 21 D5 VRT 9 20 D4 OE 10 19 D3 22 D6 TDA8763 OGND 14 output ground n.c. 15 not connected D0 16 data output; bit 0 (LSB) D1 17 data output; bit 1 V CCD2 11 18 D2 D2 18 data output; bit 2 DGND2 12 17 D1 D3 19 data output; bit 3 V CCO 13 16 D0 D4 20 data output; bit 4 OGND 14 15 n.c. D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (MSB) IR 26 in range data output DGND1 27 digital ground 1 VCCD1 28 digital supply voltage 1 (+5 V) 1999 Jan 06 MBE552 Fig.2 Pin configuration. 5 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference VCCA − VCCD −1.0 +1.0 V VCCA − VCCO −1.0 +4.0 V VCCD − VCCO −1.0 +4.0 V VI input voltage −0.3 +7.0 V Vi(sw)(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature −40 +85 °C Tj junction temperature − 150 °C referenced to AGND Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences ∆VCC are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 1999 Jan 06 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 6 VALUE UNIT 110 K/W Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 CHARACTERISTICS VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5.0 5.25 V VCCD1 digital supply voltage 1 4.75 5.0 5.25 V VCCD2 digital supply voltage 2 4.75 5.0 5.25 V VCCO output stages supply voltage 3.0 3.3 5.25 V ∆VCC supply voltage difference VCCA − VCCD −0.20 − +0.20 V VCCA − VCCO −0.20 − +2.25 V VCCD − VCCO −0.20 − +2.25 V ICCA analog supply current − 30 35 mA ICCD digital supply current − 16 21 mA ICCO output stages supply current − 1 2 mA fclk = 40 MHz; ramp input Inputs CLOCK INPUT CLK (REFERENCED TO DGND); note 1 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current Vclk = 0.8 V −1 0 +1 µA IIH HIGH-level input current Vclk = 2 V − 2 10 µA Zi input impedance fclk = 40 MHz Ci input capacitance − 2 − kΩ − 2 − pF INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2 − VCCD V IIL LOW-level input current VIL = 0.8 V −1 − − µA IIH HIGH-level input current VIH = 2 V − − 1 µA VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) IIL LOW-level input current VI = VRB = 1.3 V − 0 − µA IIH HIGH-level input current VI = VRT = 3.67 V − 35 − µA Zi input impedance fi = 4.43 MHz − 8 − kΩ Ci input capacitance − 5 − pF 1999 Jan 06 7 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8763 CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1 VRB reference voltage BOTTOM 1.1 1.3 1.5 V VRT reference voltage TOP 3.4 3.6 3.8 V Vdiff differential reference voltage VRT − VRB 2.25 2.3 2.35 V Iref reference current − 9.39 − mA Rlad resistor ladder − 245 − Ω TCRlad temperature coefficient of the resistor ladder − 1860 − ppm − 456 − mΩ/K Voffset(B) offset voltage BOTTOM note 2 − 175 − mV Voffset(T) offset voltage TOP note 2 − 175 − mV Vi(p-p) analog input voltage (peak-to-peak value) note 3 1.90 1.95 2.00 V − Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND) VOL LOW-level output voltage IOL = 1 mA 0 0.5 V VOH HIGH-level output voltage IOH = −1 mA VCCO − 0.5 − VCCO V IOZ output current in 3-state mode 0.5 V < Vo < VCCO −20 − +20 µA TDA8763M/3 30 − − MHz TDA8763M/4 40 − − MHz TDA8763M/5 50 − − MHz Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fclk(max) maximum clock frequency tCPH clock pulse width HIGH full effective bandwidth 8.5 − − ns tCPL clock pulse width LOW full effective bandwidth 5.5 − − ns fclk = 40 MHz; ramp input − ±0.8 ±2.0 LSB Analog signal processing LINEARITY INL integral non-linearity DNL differential non-linearity fclk = 40 MHz; ramp input − ±0.5 ±0.9 LSB Eoffset offset error middle code − ±1 − LSB EG gain error (from device to device) note 4 using internal reference voltage − ±3 − % 1999 Jan 06 8 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8763 CONDITIONS MIN. TYP. MAX. UNIT BANDWIDTH (fclk = 40 MHz) B analog bandwidth full-scale sine wave; note 5 − 15 − MHz 75% full-scale sine wave; note 5 − 20 − MHz small signal at mid-scale; VI = ±10 LSB at code 512; note 5 − 350 − MHz tstLH analog input settling time LOW-to-HIGH full-scale square wave; see Fig.6; note 6 − 1.5 3.0 ns tstHL analog input settling time HIGH-to-LOW full-scale square wave; see Fig.6; note 6 − 1.5 3.0 ns − − 0 dB second harmonics − −70 −63 dB third harmonics − −72 −63 dB − −61 − dB 55 58 − dB fi = 4.43 MHz − 9.4 − bits fi = 7.5 MHz − 9.1 − bits fi = 4.43 MHz − 9.3 − bits fi = 7.5 MHz − 9.0 − bits fi = 10 MHz − 8.9 − bits fi = 15 MHz − 8.1 − bits fi = 4.43 MHz − 9.3 − bits fi = 7.5 MHz − 8.9 − bits fi = 10 MHz − 8.8 − bits fi = 15 MHz − 8.0 − bits HARMONICS (fclk = 40 MHZ); see Figs 7 and 8 Hfund(FS) fundamental harmonics (full-scale) fi = 4.43 MHz Hall(FS) harmonics (full-scale); all components fi = 4.43 MHz THD total harmonic distortion fi = 4.43 MHz SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 7 SNRFS signal-to-noise ratio (full-scale) without harmonics; fclk = 40 MHz; fi = 4.43 MHz EFFECTIVE BITS; see Figs 7 and 8; note 7 EB effective bits TDA8763M/3; fclk = 30 MHz TDA8763M/4; fclk = 40 MHz TDA8763M/5; fclk = 50 MHz 1999 Jan 06 9 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator SYMBOL PARAMETER TDA8763 CONDITIONS MIN. TYP. MAX. UNIT TWO-TONE; note 8 TTIR two-tone intermodulation rejection fclk = 40 MHz − −69 − dB fclk = 50 MHz; fi = 4.43 MHz; VI = ±16 LSB at code 512 − 10−13 − times/ sample fclk = 40 MHz; PAL modulated ramp − 0.8 − % fclk = 40 MHz; PAL modulated ramp − 0.4 − deg BIT ERROR RATE BER bit error rate DIFFERENTIAL GAIN; note 9 Gdiff differential gain DIFFERENTIAL PHASE; note 9 ϕdiff differential phase Timing (fclk = 40 MHz; CL = 15 pF); see Fig.4; note 10 tds sampling delay time − 3 − ns th output hold time 4 − − ns td output delay time VCCO = 4.75 V − 10 13 ns VCCO = 3.15 V − 12 15 ns − − 15 pF CL digital output load capacitance 3-state output delay times; see Fig.5 tdZH enable HIGH − 5.5 8.5 ns tdZL enable LOW − 12 15 ns tdHZ disable HIGH − 19 24 ns tdLZ disable LOW − 12 15 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. Analog input voltages producing code 0 up to and including code 1023: a) Voffset(B) (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) Voffset(T) (voltage offset TOP) is the difference between reference voltage TOP (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 °C. 1999 Jan 06 10 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. V RT – V RB a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter, R OB + R L + R OT RL ˙ 848 × ( V to cover code 0 to code 1023, is V I = R L × I L = ----------------------------------------- × ( V RT – V RB ) = 0. RT – V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ------------------------------------------ will be kept reasonably constant from device to device. Consequently variation of the output R OB + R L + R OT codes at a given input voltage depends mainly on the difference VRT − VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. ( V 1023 – V 0 ) – V i ( p – p ) E G = ------------------------------------------------------------ × 100 Vi ( p – p) 5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal. 6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. 7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB × 6.02 + 1.76 dB. 8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. 10. Output data acquisition: the output data is available after the maximum delay time of td(max). For 50 MHz version it is recommended to have the lowest possible output load. handbook, halfpage VRT ROT code 1023 RL VRM IL RLAD code 0 ROB VRB MGD281 Fig.3 Explanation of note 3. 1999 Jan 06 11 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator Table 1 TDA8763 Output coding and input voltage (typical values; referenced to AGND) BINARY OUTPUT BITS TWOS COMPLEMENT OUTPUT BITS Vi(p-p) IR U/F 3.405 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 Table 2 Mode selection TC OE D9 to D0 IR X 1 high impedance 0 0 active; two’s complement active 1 0 active; binary active high impedance t CPL handbook, full pagewidth t CPH VCCO 50% CLK 0V sample N sample N + 1 sample N + 2 Vl t ds DATA D0 to D9 th VCCO DATA N-2 DATA N-1 DATA N DATA N+1 50% 0V td Fig.4 Timing diagram. 1999 Jan 06 12 MBG916 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator handbook, full pagewidth TDA8763 V CCD 50% OE t dHZ t dZH HIGH 90% output data 50% t dLZ LOW t dZL HIGH output data 50% LOW 10% V CCD 3.3 kΩ S1 TDA8763 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ DGND t dZH DGND OE MBE555 - 1 fOE = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. t STHL t STLH code 1023 VI 50% 50% code 0 2 ns 2 ns CLK MBE566 50% 50% 0.5 ns Fig.6 Analog input settling-time diagram. 1999 Jan 06 13 0.5 ns Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 MGD862 0 handbook, full pagewidth amplitude (dB) −20 −40 −60 −80 −100 −120 −140 0 2.50 7.50 5.00 10.0 12.5 15.0 17.5 f (MHz) 20.0 Effective bits: 9.42; THD = −71.8 dB. Harmonic levels (dB): 2nd = −83.19; 3rd = −78.09; 4th = −78.72; 5th = −78.33; 6th = −77.55. Fig.7 Typical Fast Fourier Transform (fclk = 40 MHz; fi = 4.43 MHz). MGD863 0 handbook, full pagewidth amplitude (dB) −20 −40 −60 −80 −100 −120 −140 0 2.50 5.00 7.50 10.0 12.5 15.0 17.5 20.0 Effective bits: 8.91; THD = −62.96 dB. Harmonic levels (dB): 2nd = −71.38; 3rd = −71.54; 4th = −74.14; 5th = −65.15; 6th = −77.16. Fig.8 Typical Fast Fourier Transform (fclk = 50 MHz; fi = 10 MHz). 1999 Jan 06 14 22.5 25.0 f (MHz) Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 INTERNAL PIN CONFIGURATIONS handbook, halfpage handbook, halfpage VCCO V CCA D9 to D0 IR VI OGND AGND MGC040 - 1 MBG915 Fig.9 CMOS data and in range outputs. Fig.10 Analog inputs. DEC handbook, halfpage VCCA handbook, halfpage V CCO VRT VRM OE TC RLAD REGULATOR VRB OGND MBE557 AGND MBE558 - 1 Fig.11 OE and TC input. 1999 Jan 06 Fig.12 VRB, VRM and VRT. 15 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 handbook, halfpage VCCD 1.5 V CLK DGND MBE559 - 1 Fig.13 CLK input. 1999 Jan 06 16 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 APPLICATION INFORMATION handbook, full pagewidth CLK TC VCCA 100 nF (3) AGND DEC 4.7 nF AGND VRB(1) VRM(1) 1 nF AGND VI 1 nF VRT(1) AGND 100 nF OE AGND V CCD2 100 nF 28 2 27 3 26 4 25 5 24 6 23 7 22 TDA8763 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCCD1 DGND1 (3) 100 nF IR D9 D8 D7 D6 D5 D4 D3 D2 (3) DGND2 VCCO 100 nF 1 (3) OGND D1 D0 n.c.(2) FCE167 The analog and digital supplies should be separated and well decoupled. An application note is available and describes the design and the realization of a demonstration board that uses the version TDA8763M with an application environment. (1) VRB, VRM and VRT are decoupled to AGND. (2) Pin 15 may be connected to DGND in order to prevent noise influence. (3) Decoupling capacitor for supplies: must be placed close to the device. Fig.14 Application diagram. 1999 Jan 06 17 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1999 Jan 06 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 18 o Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1999 Jan 06 TDA8763 19 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator TDA8763 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable suitable LQFP, QFP, TQFP not recommended(3)(4) suitable SSOP, TSSOP, VSO not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Jan 06 20 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator NOTES 1999 Jan 06 21 TDA8763 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator NOTES 1999 Jan 06 22 TDA8763 Philips Semiconductors Product specification 10-bit high-speed low-power ADC with internal reference regulator NOTES 1999 Jan 06 23 TDA8763 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/750/04/pp24 Date of release: 1999 Jan 06 Document order number: 9397 750 04692