TDA9965HL/C3,151

INTEGRATED CIRCUITS DATA SHEET TDA9965 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras Product specification Supersedes data of 2003 Nov 26 2004 Jul 05 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 • TTL compatible inputs; TTL and CMOS compatible outputs. FEATURES • Clamp and Track/Hold (CTH) circuit with adjustable bandwidth, Programmable Gain Amplifier (PGA), 12-bit Analog-to-Digital Converter (ADC) and reference regulator APPLICATIONS • CCD camera systems. • Fully programmable via a 3-wire serial interface • Sampling frequency up to 30 MHz GENERAL DESCRIPTION • PGA gain from 0 to 36 dB (in 0.05 dB steps) The TDA9965 is a 12-bit analog-to-digital interface for a CCD camera. The device includes a CTH circuit, PGA and a low-power 12-bit ADC, together with its reference voltage regulator. • CTH programmable bandwidth from 35 to 284 MHz typical • Standby mode (20 mW typical) • Low power consumption of only 425 mW typical The CTH has a bandwidth circuit controlled by on-chip DACs via a serial interface. • 5 V operation and 2.5 to 5.25 V operation for the digital outputs A 10-bit digital clamp controls the ADC input clamp level. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION TDA9965HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5 5.25 V VCCD digital supply voltage 4.75 5 5.25 V VCCO digital output supply voltage 2.5 3 5.25 V ICCA analog supply current with internal regulator − 65 − mA ICCD digital supply current with internal regulator − 19 − mA ICCO digital output supply current fpix = 30 MHz; CL = 10 pF on all − data outputs; ramp input 1 − mA ADCres ADC resolution − 12 − bits Vi(IN)(p-p) CTH input voltage (peak-to-peak value) − 2 − V GCTH CTH output amplifier gain − 0 − dB PGAdyn PGA dynamic range − 36 − dB fpix(max) maximum pixel frequency code fco(CTH) = 0000 30 − − MHz Ntot(rms) total noise from CTH input to ADC output (RMS value) GPGA = 0 dB; code fco(CTH) = 0000 − 0.85 − LSB Vn(i)(eq)(rms) equivalent input noise (RMS value) GPGA = 30 dB; code fco(CTH) = 0000; note 1 − 90 − µV Ptot total power consumption − 425 − mW Note 1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB. 2004 Jul 05 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... IN AGND5 STGE AGND1 VCCA1 1 2 45 46 CLPADC CLPOB 44 VCCD1 CLKADC DGND1 STDBY D11 43 42 41 40 39 38 D10 37 CLAMP CLAMP 36 CLOCK TRACK AND HOLD 3 35 4 34 5 10 33 4-BIT DAC 6 32 AGND2 7 8 Vref 9 PGAOUT 12-BIT ADC OUTPUT BUFFER 31 30 10 29 PGA 28 10-BIT DAC ADCIN D7 D6 VCCO2 OGND2 VCCO1 OGND1 27 D5 D4 11 26 n.c. D8 REF = 3.2 V 12 INIT-ONPOWER REGULATOR 14 15 17 REF32 19 20 21 SDATA SEN AGND3 Fig.1 Block diagram. 22 SCLK 23 D0 24 D1 D2 FCE424 TDA9965 VRT 18 VCCA3 DEC VRB REGEN 16 25 SERIAL INTERFACE D3 Product specification 13 handbook, full pagewidth 3 VCCA2 TDA9965 12 D9 Philips Semiconductors AGND4 47 SHP 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras 48 SHD BLOCK DIAGRAM 2004 Jul 05 VCCD2 DGND2 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 PINNING SYMBOL PIN DESCRIPTION AGND4 1 analog ground 4 IN 2 data input signal from CCD AGND5 3 analog ground 5 STGE 4 clamp storage capacitor pin AGND1 5 analog ground 1 VCCA1 6 analog supply voltage 1 AGND2 7 analog ground 2 VCCA2 8 analog supply voltage 2 Vref 9 ADC clamp reference voltage input; short-circuited to ground via a capacitor PGAOUT 10 PGA amplifier signal output ADCIN 11 ADC analog signal input; externally connected to pin PGAOUT n.c. 12 not connected REGEN 13 regulator enable input (active HIGH) VRB 14 regulator reference voltage bottom VRT 15 regulator reference voltage top DEC 16 regulator decoupling; decoupled to ground via a capacitor REF32 17 internal reference voltage; decoupled to ground via a capacitor VCCA3 18 analog supply voltage 3 AGND3 19 analog ground 3 SEN 20 enable input for the serial interface shift register (active LOW) SCLK 21 serial clock input for the serial interface SDATA 22 serial data input: 10-bit PGA gain, 4-bit DAC for the frequency cut-off, 10 low significant bits for the digital ADC clamp and edge pulse control D0 23 ADC digital output 0 (LSB) D1 24 ADC digital output 1 D2 25 ADC digital output 2 D3 26 ADC digital output 3 D4 27 ADC digital output 4 D5 28 ADC digital output 5 OGND1 29 digital output ground 1 VCCO1 30 digital output supply voltage 1 OGND2 31 digital output ground 2 VCCO2 32 digital output supply voltage 2 D6 33 ADC digital output 6 D7 34 ADC digital output 7 D8 35 ADC digital output 8 D9 36 ADC digital output 9 D10 37 ADC digital output 10 D11 38 ADC digital output 11 (MSB) STDBY 39 standby control input (active HIGH); all output bits are logic 0 when standby is enabled 2004 Jul 05 4 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras DESCRIPTION CLPOB 44 clamp control pulse input at optical black SHP 45 preset sample and hold pulse input SHD 46 data sample and hold pulse input VCCD2 47 digital supply voltage 2 DGND2 48 digital ground 2 handbook, full pagewidth 39 STDBY clamp control pulse input for ADC analog input signal 40 VCCD1 43 41 DGND1 CLPADC 42 CLKADC ADC clock input 43 CLPADC digital ground 1 42 44 CLPOB 41 CLKADC 45 SHP DGND1 46 SHD digital supply voltage 1 47 VCCD2 40 48 DGND2 VCCD1 37 D10 PIN 38 D11 SYMBOL TDA9965 AGND4 1 36 D9 IN 2 35 D8 3 34 D7 STGE 4 33 D6 AGND5 AGND1 5 32 VCCO2 VCCA1 6 31 OGND2 TDA9965HL AGND2 7 30 VCCO1 VCCA2 8 29 OGND1 Vref Fig.2 Pin configuration. 2004 Jul 05 5 D1 24 D0 23 SDATA 22 SCLK 21 SEN 20 25 D2 AGND3 19 n.c. 12 VCCA3 18 26 D3 REF32 17 ADCIN 11 DEC 16 27 D4 VRT 15 PGAOUT 10 VRB 14 28 D5 REGEN 13 9 FCE531 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO digital output supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage difference between VCCA and VCCD −1.0 +1.0 V between VCCD and VCCO −1.0 +4.0 V Vi input voltage −0.3 +7.0 V Io output current −10 +10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −20 +75 °C Tj junction temperature − 150 °C referenced to AGND Note 1. All supplies are connected together. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2004 Jul 05 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 6 VALUE UNIT 76 K/W Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 CHARACTERISTICS VCCA = VCCD = 5 V; VCCO = 3 V; fpix = 30 MHz; Tamb = −20 to +75 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA analog supply voltage 4.75 5 5.25 V VCCD digital supply voltage 4.75 5 5.25 V VCCO digital output supply voltage 2.5 3 5.25 V ICCA analog supply current with internal regulator − 65 − mA ICCD digital supply current with internal regulator − 19 − mA ICCO digital output supply current fpix = 30 MHz; CL = 10 pF on all data outputs; ramp input − 1 − mA Digital inputs CLOCK INPUT: PIN CLKADC (REFERENCED TO DGND) VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VCCD V IIL LOW-level input current VCLKADC = 0.8 V −1 − +1 µA IIH HIGH-level input current VCLKADC = 2.0 V − − 20 µA Zi input impedance − 63 − kΩ Ci input capacitance − 1 − pF CONTROL INPUTS: PINS SEN, SCLK, SDATA, STDBY, CLPOB, CLPADC AND REGEN VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VCCD V Ii input current −2 − +2 µA SAMPLE AND HOLD INPUTS: PINS SHP AND SHD VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VCCD V Ii input current −10 − +10 µA Clamp and Track/Hold (CTH) circuit: pins IN, SHD and SHP Vi(IN)(p-p) CTH input voltage (peak-to-peak value) − 2 − V Ii(IN) input current −3 − +3 µA tW(SHP) SHP pulse width 9 − − ns 2004 Jul 05 Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 7 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras SYMBOL tW(SHD) PARAMETER SHD pulse width TDA9965 CONDITIONS MIN. TYP. MAX. UNIT 9 − − ns 0000 − 8 − ns 0001 − 13 − ns Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; see Fig.5 code fco(CTH) 0010 − 17 − ns 0100 − 23 − ns 1000 − 33 − ns 1111 − 51 − ns th(IN-SHP) CTH input hold time compared see Fig.5 to control pulse SHP − 3 − ns th(IN-SHD) CTH input hold time compared see Fig.5 to control pulse SHD − 3 − ns − 2000 − mV Programmable Gain Amplifier (PGA) output: pin PGAOUT VPGAOUT(p-p) PGA output amplifier dynamic voltage level (peak-to-peak value) VPGAOUT(b) PGA output amplifier black level voltage code C(CLP) = 0 − 1.475 − V ZPGAOUT PGA output amplifier output impedance fpix at 10 kHz for minimum and maximum values − 5 − Ω IPGAOUT PGA output current drive static − − 1 mA GPGA(min) minimum gain of PGA circuit code GPGA = 0 − 0 − dB GPGA(max) maximum gain of PGA circuit code GPGA ≥767 − 36 − dB Analog-to-Digital Converter (ADC) fpix(max) maximum pixel frequency 30 − − MHz tW(CLKADC)H CLKADC pulse width HIGH Vi(IN) = 1000 mV; transition (99.5%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128; see Fig.5 12 − − ns tW(CLKADC)L CLKADC pulse width LOW Vi(IN) = 1000 mV; transition (99.5%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128 12 − − ns SRCLKADC CLKADC input slew rate rising and falling edges; 10% to 90% 0.5 − − V/ns Vi(ADCIN)(p-p) ADC input voltage (peak-to-peak value) with internal regulator − 2 − V Ii(ADCIN) ADC input current −2 − +120 µA VRB ADC reference voltage bottom − 1.30 − V VRT ADC reference voltage top − 3.65 − V 2004 Jul 05 8 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras SYMBOL PARAMETER TDA9965 CONDITIONS MIN. TYP. MAX. UNIT DNL differential non linearity ramp input − ±0.5 ±0.9 LSB td(s) sampling delay see Fig.5 − − 5 ns Total chain characteristics (CTH + PGA + ADC) td(SHD-CLKADC) delay between SHD and CLKADC Vi(IN) = 1000 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 128; see Fig.5 − 13 − ns th(SHD-CLKADC) SHD hold time compared to CLKADC Vi(IN) = 32 mV; transition (99%) in 1 pixel; code fco(CTH) = 0000; code GPGA = 767; see Fig.5 − 0 − ns Ntot(rms) GPGA = 0 dB; code fco(CTH) = 0000 − 0.85 − LSB GPGA = 30 dB; code fco(CTH) = 0000; note 1 − 6 − LSB total noise from CTH input to ADC output (RMS value) OCCD(max) maximum offset voltage between CCD floating level and CCD dark pixel level see Fig.11 −200 − +200 mV Vn(i)(eq)(rms) equivalent input noise (RMS value) GPGA = 30 dB; code fco(CTH) = 0000; note 1 − 90 − µV VCCO V 0.5 V Digital outputs (fpix = 30 MHz; CL = 10 pF) VOH HIGH-level output voltage IOH = −1 mA VCCO − 0.5 − VOL LOW-level output voltage IOL = 1 mA 0 th(o) output hold time see Fig.5 10 − − ns td(o) output delay VCCO = 5.25 V − 20 25 ns VCCO = 3 V − 26 31 ns VCCO = 2.5 V − 30 35 ns 5 − − MHz − Serial interface fSCLK(max) maximum clock frequency of serial interface Note 1. Noise and clamp behaviour are not guaranteed for a PGA gain higher than 30 dB. 2004 Jul 05 9 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras handbook, full pagewidth SDATA TDA9965 SHIFT REGISTER SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 A0 SCLK LSB A1 MSB 10 LATCH SELECTION SEN (SD0 to SD9) (SD0 to SD3) (SD0 to SD2) PGA GAIN LATCHES FREQUENCY LATCHES EDGE CONTROL LATCHES PGA control frequency control CTH edge control clocks (SD0 to SD9) CLAMP ADC LATCHES 10-bit LSB ADC clamp FCE709 Fig.3 Serial interface block diagram. tsu2 handbook, full pagewidth th1 MSB SDATA A1 A0 SD9 SD8 SD7 LSB SD6 SD5 SD4 SD3 SD2 SD1 SD0 SCLK SEN tsu1 th2 tsu3 MGU158 tsu1 = tsu2 = tsu3 = 4 ns (minimum); th1 = th2 = 4 ns (minimum). Fig.4 Loading sequence of control DACs input data via the serial interface. 2004 Jul 05 10 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras Table 1 TDA9965 Serial interface programming ADDRESS BITS SDATA BITS SD0 to SD9 A1 A0 0 0 clamp reference of ADC (SD0 to SD9), note 1 0 1 cut-off frequency of CTH (SD0 to SD3) 1 0 PGA gain control (SD0 to SD9) 1 1 edge control for pulses SHP, SHD, CLPOB, CLPADC and CLKADC (note 2): SD0 = 1, SHP and SHD sample on LOW level SD1 = 1, CLPADC and CLPOB activated on HIGH level SD2 = 1, CLKADC activated with rising edge Notes 1. PGA gain register must always be refreshed after clamp code register content has been changed. 2. When pin CLPADC = HIGH (SD1 = 1; serial interface), the ADC input is clamped to the voltage level of Vref. Pin Vref is connected to ground via a capacitor. When the power supplies increase from zero to VCC, the init-on-power block initializes the circuit as follows: • Cut-off frequency of the CTH circuit is set to: code fco(CTH) = 0 • PGA gain control is set to: code GPGA = 0 • Clamp code of the ADC is set to: code ADCCLP = 0 • SHP and SHD sample on HIGH level; CLKADC activated with rising edge • CLPOB and CLPADC activated on HIGH level. Table 2 Standby selection PIN STDBY DATA BITS SD9 to SD0 ICCA + ICCD HIGH logic 0 4 mA (typical); note 1 LOW active 84 mA (typical) Note 1. In case an external regulator is used, it has to be switched off in standby mode in order to avoid an extra power consumption of the TDA9965. 2004 Jul 05 11 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 handbook, full pagewidth IN from CCD N+2 N+1 N N+3 th(IN-SHP) tW(SHP) 2.0 V SHP 0.8 V th(IN-SHD) tW(SHD) 2.0 V SHD 0.8 V ADCIN N−1 N+1 N td(SHD-CLKADC) N+2 th(SHD-CLKADC) tW(CLKADC)H CLKADC 2.0 V td(s) 50% 0.8 V th(o) td(o) 90% DATA N−3 N−2 N−1 N 10% MGU389 The polarities used in this case are: - SHP and SHD sample on HIGH level - CLKADC activated with rising edge. Fig.5 Pixel frequency timing diagram. 2004 Jul 05 12 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 1 pixel handbook, full pagewidth PGAOUT VIDEO OPTICAL BLACK 1 pixel HORIZONTAL FLYBLACK DUMMY VIDEO CLPOB WINDOW CLPOB (active HIGH) CLPADC WINDOW CLPADC WINDOW CLPADC (active HIGH) MGU861 Fig.6 Line frequency timing diagram. FCE775 FCE758 300 48 handbook, halfpage handbook, halfpage GPGA (dB) BW (MHz) 36 200 24 100 12 0 0000 0 0 Fig.7 256 512 768 1024 PGA control DAC input code PGA gain as a function of PGA control DAC input code. 2004 Jul 05 Fig.8 13 0010 0100 1000 1111 CTH control code CTH bandwidth as a function of CTH control code. Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 handbook,I halfpage FCE689 (µA) handbook,I halfpage (µA) 400 600 50 0 V (V) 2.4 0 VO − 64 LSB −50 − 600 VO VO + 64 LSB V (V) (1) 70 mV MCE191 −400 (1) VO depends on the clamp code. Fig.9 Typical clamp current as a function of voltage on pin STGE. Fig.10 Typical clamp current as a function of voltage on pin Vref. handbook, halfpage +200 mV −200 mV FCE688 Fig.11 Maximum offset voltage between CCD floating and dark pixel level. 2004 Jul 05 14 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 APPLICATION DIAGRAM from timing generator 5.0 V 5.0 V Vref (3) 100 nF PGAOUT (1) ADCIN D11 VCCD1 DGND1 CLKADC CLPADC CLPOB SHP SHD D10 37 D9 36 2 35 3 34 4 33 5 32 6 31 TDA9965 7 30 8 29 9 28 10 27 11 26 12 13 REGEN n.c. 38 14 15 1 nF 1 nF 17 16 18 1 µF 2.2 nF 19 20 21 22 23 25 24 D8 D7 D6 VCCO2 OGND2 (2) VCCO1 OGND1 (2) D5 D4 D3 D2 D1 VCCA2 39 D0 (2) 5.0 V 40 SDATA AGND2 41 SCLK 5.0 V VCCA1 42 SEN (2) 43 AGND3 AGND1 44 VCCA3 STGE (3) 45 REF32 AGND5 47 nF 46 DEC 33 pF 47 VRT IN CCD 48 1 VRB AGND4 (2) VCCD2 DGND2 (2) STDBY handbook, full pagewidth (2) 5.0 V serial interface MGU195 (1) The clamp level of the signal input at pin ADCIN can be tuned from code 0 to code 1023 in one LSB step of the ADC via the serial interface (clamp ADC activated). (2) All supply pins must be decoupled with 100 nF capacitors as closely as possible to the device. (3) The capacitors on pins STGE and Vref have typical values, performing a typical device start-up time of 300 µs from standby to active (supplies on). Fig.12 Application diagram. 2004 Jul 05 15 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras from timing generator 5.0 V 5.0 V 31 6 TDA9965 7 30 8 29 9 28 10 27 11 26 12 13 14 15 VRB 16 17 18 1 µF 1 nF 2.2 nF 19 20 VCCA1 AGND2 (2) 5.0 V VCCA2 Vref (3) 100 nF PGAOUT (1) ADCIN DGND1 CLKADC CLPADC CLPOB SHP SHD VCCD1 40 39 38 35 3 34 4 33 5 32 6 31 TDA9965 7 30 8 29 9 28 10 27 11 26 12 13 OGND1 (2) D5 D4 D3 D2 37 D9 36 2 REGEN n.c. 41 14 15 16 17 18 19 20 SEN 5.0 V 42 21 SCLK (2) 43 AGND3 AGND1 44 REF32 (3) 45 VCCA3 STGE 46 DEC 47 nF 47 VRT AGND5 25 24 (2) VCCO1 5.0 V 1 VRB 33 pF 23 OGND2 (2) VCCD2 DGND2 CCD2 22 VCCO2 serial interface 5.0 V (2) 48 21 D7 D6 (2) from timing generator 5.0 V IN D10 32 1 nF AGND4 D11 VCCD1 CLKADC DGND1 CLPADC CLPOB SHP SHD 33 5 REGEN n.c. 4 D1 ADCIN 34 D10 (1) 3 D8 22 23 25 24 D8 D7 D6 VCCO2 OGND2 (2) VCCO1 OGND1 (2) D5 D4 D3 D2 D1 Vref (3) 100 nF PGAOUT 35 D0 VCCA2 37 D9 36 2 SDATA 5.0 V 38 D11 AGND2 (2) 39 STDBY 5.0 V VCCA1 40 D0 (2) 41 SDATA AGND1 42 SEN (3) 43 SCLK STGE 44 AGND3 47 nF 45 REF32 AGND5 46 VCCA3 33 pF 47 DEC IN CCD1 48 1 VRT AGND4 (2) VCCD2 DGND2 (2) STDBY handbook, full pagewidth TDA9965 2.2 nF (2) 5.0 V 1 nF 1 nF serial interface 1 µF Fig.13 Application diagram with 2 CCDs. 2004 Jul 05 16 For notes (1), (2) and (3) see Fig.12 FCE825 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras Power and grounding recommendations In a two-ground system, in order to minimize the noise from package and die parasitics, the following recommendations must be implemented: Care must be taken to minimize noise when designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras. • The ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. The analog and digital ground planes must be connected with an inductor as close as possible to the IC package, in order to have the same DC voltage on the ground planes. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational amplifiers) must be taken into account, particularly with respect to power and ground connections. • The digital output pins and their associated lines should be shielded by the digital ground plane, which can be used as return path for the digital signals. The connections between CCD interface and CTH input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analog and digital supplies provide the best performance. If it is not possible to do this on the board, then decouple the analog supply pins effectively from the digital supply pins. The decoupling capacitors must be placed as close as possible to the IC package. 2004 Jul 05 TDA9965 17 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 o 0 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 2004 Jul 05 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 18 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 To overcome these problems the double-wave soldering method was specifically developed. SOLDERING Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON-T and SSOP-T packages – for packages with a thickness ≥ 2.5 mm Manual soldering – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2004 Jul 05 19 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2004 Jul 05 20 Philips Semiconductors Product specification 12-bit, 5.0 V, 30 Msps analog-to-digital interface for CCD cameras TDA9965 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Jul 05 21 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R78/07/pp22 Date of release: 2004 Jul 05 Document order number: 9397 750 13311