TDF8530
I2C-bus controlled quad channel 45 W/2 class-D power
amplifier with full diagnostics
Rev. 3 — 20 October 2011
Product short data sheet
1. General description
The TDF8530 is a quad Bridge-Tied Load (BTL) car audio amplifier comprising an
NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low power
dissipation enables the TDF8530 high-efficiency, class-D amplifier to be used with a
smaller heat sink than those normally used with standard class-AB amplifiers.
The TDF8530 can operate in either non-I2C-bus mode or I2C-bus mode. When in I2C-bus
mode, DC load detection results and fault conditions can be easily read back from the
device. Up to 12 I2C-bus addresses can be selected depending on the value of the
external resistors connected to pins ADS and MOD.
When pin ADS is short circuited to ground, the TDF8530 operates in non-I2C-bus mode.
Switching between Operating mode and Mute mode in non-I2C-bus mode is only possible
using pins EN and SEL_MUTE.
2. Features and benefits
High-efficiency
Low quiescent current
Operating voltage from 6 V to 24 V
4 or 2 capable BTL channels
Fast-mode I2C-bus
I2C-bus mode with 12 I2C-bus addresses or non-I2C-bus mode operation
Clip detect selectable at 0.2 % or 10 % THD
Independent short-circuit protection for each channel
Advanced short-circuit protection for load, GND and supply
Load dump protection to 50 V
Thermal foldback and thermal protection
DC offset protection
Selectable AD or BD modulation
Advanced clocking:
Switchable oscillator clock source: internal for Master mode or external for Slave
mode
Spread spectrum mode
Phase staggering
Frequency hopping
No ‘pop noise’ caused by DC output offset voltage
I2C-bus mode:
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Load diagnostics
Speaker load, open load and shorted load
Amplifier output to ground and to supply shorts
Tweeter detection
Thermal pre-warning diagnostic level setting
Identification of activated protections or warnings
Selectable diagnostic information available using DIAG pin
Qualified in accordance with AEC-Q100
3. Applications
Car audio
Audio entertainment systems
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
6
14.4
24
V
General; VP = 14.4 V
VP
supply voltage
IP
supply current
off state; VEN < 0.8 V
-
2
10
A
Iq
quiescent current
no load, snubbers and output filter
connected
-
185
200
mA
RL = 4 ; THD = 10 %
24
26
-
W
RL = 2 ; THD = 10 %
39
45
-
W
RL = 4 ; THD = 10 %
-
70
-
W
RL = 2 ; THD = 10 %
-
100
-
W
Quad BTL channel; VP = 14.4 V
output power
Po
Quad BTL channel; VP = 24 V
output power
Po
5. Ordering information
Table 2.
Ordering information
Type number
TDF8530TH
Package
Name
Description
Version
HSOP44
plastic, heatsink small outline package; 44 leads; low stand-off height
SOT1131-1
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
6. Block diagram
VDDA
30
VP1
VP2
6
17
TDF8530
AGND
SVRR
ACGND
29
1
STABI1
31
28
CHANNEL 1 OF 4
PWM
CONTROL
IN2P
IN3P
IN4P
5, 8,
15, 18
BOOT1N
BOOT2N
BOOT3N
BOOT4N
4, 9,
14, 19
OUT1N
OUT2N
OUT3N
OUT4N
2, 11,
12, 21
BOOT1P
BOOT2P
BOOT3P
BOOT4P
3, 10,
13, 20
OUT1P
OUT2P
OUT3P
OUT4P
PVDD
DRIVER
HIGH
IN1P
VSTAB1
26
DRIVER
LOW
25
PGND
24
PVDD
DRIVER
HIGH
23
PWM
CONTROL
DRIVER
LOW
PGND
INN
OSCSET
OSCIO
SSM
MOD
VDDD
EN
SEL_MUTE
SCL
SDA
ADS
27
41
42
40
TDF8530_SDS
Product short data sheet
VSTAB2
36
43
5 V STABI
33
32
38
39
MODE
SELECT
+
I2C-BUS
DIAGNOSTICS
44
34
PROTECTION
OVP, OCP, OTP
UVP, TFP, WP, DCP
37
GNDD/HW
Fig 1.
22
STABI2
OSCILLATOR
DIAG
35
DCP
7
16
PGND1
PGND2
aaa-000198
Block diagram
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TDF8530
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I2C-bus controlled quad channel Class-D power amplifier
7. Pinning information
7.1 Pinning
GNDD/HW 44
1
VSTAB1
VDDD 43
2
BOOT1P
OSCIO 42
3
OUT1P
OSCET 41
4
OUT1N
SSM 40
5
BOOT1N
SDA 39
6
VP1
SCL 38
7
PGND1
ADS 37
8
BOOT2N
MOD 36
9
OUT2N
DCP 35
DIAG 34
EN 33
10 OUT2P
11 BOOT2P
TDF8530TH
12 BOOT3P
SEL_MUTE 32
13 OUT3P
SVRR 31
14 OUT3N
15 BOOT3N
VDDA 30
16 PGND2
AGND 29
ACGND 28
17 VP2
18 BOOT4N
INN 27
IN1P 26
19 OUT4N
IN2P 25
20 OUT4P
IN3P 24
21 BOOT4P
IN4P 23
22 VSTAB2
aaa-000199
Fig 2.
Heatsink up (top view) pin configuration TDF8530TH
7.2 Pin description
TDF8530_SDS
Product short data sheet
Table 3.
Pin description
Symbol
Pin
VSTAB1
1
decoupling internal stabilizer 1 for DMOST drivers
BOOT1P
2
bootstrap capacitor for channel 1 positive
OUT1P
3
O
channel 1 positive PWM output
OUT1N
4
O
channel 1 negative PWM output
BOOT1N
5
VP1
6
P
channel 1 power supply voltage
PGND1
7
G
channel 1 power ground
BOOT2N
8
OUT2N
9
O
channel 2 negative PWM output
OUT2P
10
O
channel 2 positive PWM output
BOOT2P
11
bootstrap capacitor for channel 2 positive
BOOT3P
12
bootstrap capacitor for channel 3 positive
Type[1]
Description
bootstrap capacitor for channel 1 negative
bootstrap capacitor for channel 2 negative
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 3.
TDF8530_SDS
Product short data sheet
Pin description …continued
Symbol
Pin
Type[1]
Description
OUT3P
13
O
channel 3 positive PWM output
OUT3N
14
O
channel 3 negative PWM output
BOOT3N
15
PGND2
16
G
channel 2 power ground
VP2
17
P
channel 2 power supply voltage
BOOT4N
18
OUT4N
19
O
channel 4 negative PWM output
OUT4P
20
O
channel 4 positive PWM output
BOOT4P
21
bootstrap capacitor for channel 4 positive
VSTAB2
22
decoupling internal stabilizer 2 for DMOST drivers
IN4P
23
I
channel 4 positive audio input
IN3P
24
I
channel 3 positive audio input
IN2P
25
I
channel 2 positive audio input
IN1P
26
I
channel 1 positive audio input
INN
27
I
common negative audio input
ACGND
28
I
decoupling for input reference voltage
AGND
29
G
analog supply ground
VDDA
30
P
analog supply voltage
SVRR
31
I
decoupling for internal half supply reference voltage
bootstrap capacitor for channel 3 negative
bootstrap capacitor for channel 4 negative
SEL_MUTE
32
I
select mute or unmute
EN
33
I
enable input:
non-I2C-bus mode: switch between off and Mute mode
I2C-bus mode: off and Standby mode
DIAG
34
O
diagnostic output; open-drain
DCP
35
I
DC protection input for the filtered output voltages
MOD
36
I
modulation mode and phase shift select
ADS
37
I
non-I2C-bus mode: connected to ground
I2C-bus mode: selection and address selection pin
SCL
38
I
I2C-bus clock input
SDA
39
I/O
I2C-bus data input and output
SSM
40
master setting: Spread spectrum mode frequency
slave setting: phase lock operation
OSCSET
41
master/slave oscillator setting
master only setting: set internal oscillator frequency
OSCIO
42
VDDD
43
GNDD/HW
44
I/O
external oscillator slave setting: input
internal oscillator master setting: output
decoupling of the internal 5 V logic supply
G
ground digital supply voltage and handle wafer connection
[1]
I = input, O = output, I/O = input/output, G = ground and P = power supply.
[2]
In this data sheet supply voltage VP describes VP1, VP2 and VDDA.
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TDF8530
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I2C-bus controlled quad channel Class-D power amplifier
8. Functional description
8.1 Master and slave mode selection
In a master and slave configuration, multiple TDF8530 devices are daisy-chained together
in one audio application with a single device providing the clock frequency signal for all
other devices. In this situation, it is recommended that the oscillators of all devices are
synchronized for optimum EMI behavior as follows:
All OSCIO pins are connected together and one TDF8530 in the application is configured
as the clock-master. All other TDF8530 devices are configured as clock-slaves.
• The clock-master pin OSCIO is configured as the oscillator output. When a resistor
(Rosc) is connected between pins OSCSET and AGND, the TDF8530 is in Master
mode.
• The clock-slave pins OSCIO are configured as the oscillator inputs. When pin
OSCSET is directly connected to pin AGND, the TDF8530 is in Slave mode.
See Table 4 for all oscillator modes. IB3[D2] = 0 in non-I2C-bus mode.
Table 4.
Oscillator modes
OSCSET pin
OSCIO pin
SSM pin
IB3[D2]
Oscillator modes
Rosc > 22 k
output
CSSM to pin AGND
0
master, spread spectrum[1]
1
master, spread spectrum[2]
0
master, no spread spectrum[1]
1
master, no spread spectrum[2]
0
slave, PLL enabled[1]
1
slave, PLL enabled[2]
0
slave, PLL disabled[1]
no 1⁄2 phase staggering
1
slave, PLL disabled[2]
shorted to pin AGND
Rosc = 0
input
CPLL + RPLL to pin AGND
shorted to pin AGND
[1]
fOSCIO = fosc.
[2]
fOSCIO = 2 fosc.
8.2 Operation mode selection
Pin MOD is used to select specific operating modes. The resistor (RMOD) connected
between pins MOD and AGND together with the non-I2C-bus/I2C-bus mode determine the
operating mode (see Table 5). This in turn is determined by the resistor value connected
between pins ADS and AGND.
In non-I2C-bus mode, pin MOD is used to select:
• AD or BD modulation (see Section 8.2.1).
• 2⁄8 phase shift when oscillator is used in Slave mode (see Section 8.2.2).
In I2C-bus mode, pin MOD can only select the I2C-bus address range. The modulation
mode and phase shift are programmed using I2C-bus commands.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 5.
Operation mode selection with the MOD pin
RMOD (k)
Non-I2C-bus mode[1]
0 (short to AGND)
AD modulation: no phase shift in Slave mode
6.8
BD modulation: no phase shift in Slave mode
33
AD modulation: 2⁄8 phase shift in Slave mode
100
BD modulation: 2⁄8 phase shift in Slave mode
[1]
RADS = 0 ; pin ADS is short circuited to pin AGND.
8.2.1 Modulation mode
In non-I2C-bus mode, pin MOD is used to select either AD or BD modulation mode (see
Table 5). In I2C-bus mode, the modulation mode is selected using I2C-bus command
IB3[D0].
• AD modulation mode: the bridge halves switch in opposite phase.
• BD modulation mode: the bridge halves switch in phase.
Figure 4 and Figure 5 show simplified representations of AD and BD modulation.
+VP
INxP
+VP
OUTP OUTN
INxN
AD
BD
001aai778
Fig 3.
AD/BD modulation switching circuit
INxP
OUTxP
001aai779
a. Bridge half 1.
INxN
OUTxN
001aai780
b. Bridge half 2 switched in the opposite phase to bridge half 1.
Fig 4.
TDF8530_SDS
Product short data sheet
AD modulation
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
INxP
OUTxP
OUTxP - OUTxN
001aai781
a. Phase switching cycle.
INxN
OUTxN
001aai782
b. Inverted signal to the modulator.
Fig 5.
BD modulation
8.2.2 Phase staggering (Slave mode)
In Slave mode with phase lock operation enabled, a phase shift with respect to the
incoming clock signal can be selected to distribute the switching moments over time in
multi-amplifier applications. In non-I2C-bus mode, 2⁄8 phase shift can be programmed
using pin MOD. In I2C-bus mode, three different phase shifts (1⁄8 , 2⁄8 , 3⁄8 ) can be
selected using the I2C-bus bits (IB4[D2:D3]). See Table 5 for selection of the phase shift in
non-I2C-bus mode with pin MOD.
By default there is a 1⁄2 phase staggering between channels 1 and 2 and channels 3 and
4 of the TDF8530 independent of Master or Slave mode. This 1⁄2 phase staggering can
be disabled using the I2C-bus bit IB4[D4] resulting in all channels switching at the same
time.
Figure 6 shows an example of the use of 2⁄8 phase shift with BD modulation.
TDF8530_SDS
Product short data sheet
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TDF8530
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I2C-bus controlled quad channel Class-D power amplifier
OUT1P
phase
0
OUT1N
OUT2P
OUT2N
1
2
master
OUT3P
OUT3N
OUT4P
3
2
OUT4N
OUT1P
2
8
OUT1N
OUT2P
10
8
OUT2N
slave
OUT3P
6
8
OUT3N
OUT4P
14
8
OUT4N
aaa-000445
Fig 6.
Master and slave operation with 2⁄8 phase shift
8.3 Protection
The TDF8530 includes a range of built-in protection functions. All protections are
asynchronous and do not need an (external) clock signal at pin OSCIO to be operational.
How the TDF8530 manages the various possible fault conditions for each protection is
described in the following sections:
Table 6.
TDF8530_SDS
Product short data sheet
Overview of protection types
Protection type
Reference
Thermal foldback
Section 8.3.1
Overtemperature
Section 8.3.2
Overcurrent
Section 8.3.3
Window
Section 8.3.4
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 6.
Overview of protection types …continued
Protection type
Reference
DC Offset
Section 8.3.5
Undervoltage
Section 8.3.6
Overvoltage
Section 8.3.6
8.3.1 Thermal foldback
The TDF8530 has a built-in Thermal Foldback Protection (TFP) which is tripped when the
average junction temperature exceeds the threshold level. TFP decreases amplifier gain
such that the combination of power dissipation and Rth(j-a) create a junction temperature
around the threshold level. The device will not completely switch off but remains
operational at the lower output power levels. If the average junction temperature
continues to increase, a second built-in temperature protection threshold level shuts down
the amplifier completely.
8.3.2 Overtemperature protection
If the average junction temperature (Tj) > 160 C, OverTemperature Protection (OTP) is
tripped and the power stages shut down immediately.
8.3.3 Overcurrent protection
OverCurrent Protection (OCP) is tripped when the output current exceeds the threshold.
OCP regulates the output voltage such that the maximum output current is limited. The
amplifier outputs keep switching and the amplifier is NOT shutdown completely. This is
called current limiting.
OCP also detects when the loudspeaker terminals are short circuited or one of the
amplifier’s demodulated outputs is short circuited to one of the supply lines. In either case,
the shorted channel(s) are switched off.
The amplifier can distinguish between loudspeaker impedance drops and a low-ohmic
short across the load or one of the supply lines. This impedance threshold depends on the
supply voltage used. When a short is made across the load causing the impedance to
drop below the threshold level, the shorted channel(s) are switched off. They try to restart
every 50 ms. If the short circuit condition is still present after 50 ms, the cycle repeats. The
average power dissipation will be low because of this reduced duty cycle.
When a channel is switched off due to a short circuit on one of the supply lines, Window
Protection (WP) is activated. WP ensures that the amplifier does not start up after 50 ms
until the supply line short circuit is removed.
8.3.4 Window protection
Window Protection (WP) checks the PWM output voltage before switching from Standby
mode to Mute mode (with both outputs switching) and is activated as follows:
• During the start-up sequence:
– When the TDF8530 is switched from standby to mute (td(stb-mute)). When a short
circuit on one of the output terminals (to VP or GND) is detected, the start-up
procedure for that channel is interrupted and the TDF8530 waits for open circuit
outputs. No large currents flow in the event of a short circuit to the supply lines
because the check is performed before the power stages are enabled.
TDF8530_SDS
Product short data sheet
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TDF8530
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I2C-bus controlled quad channel Class-D power amplifier
• During operation:
– A short circuit to one of the supply lines trips OCP causing the amplifier channel to
shut down. After 50 ms the amplifier channel restarts and WP is activated.
However, the corresponding amplifier channel will not start up until the supply line
short circuit has been removed.
8.3.5 DC offset protection
DC Protection (DCP) is activated (using IB1[D6] or IB2[D6]) when the DC content in the
demodulated output voltage exceeds a set threshold (typically 2 V). DCP is active in both
Mute mode and Operating mode. False triggering of the DCP by low frequencies in the
audio signal is prevented by use of an external capacitor between pin DCP and pin AGND
to generate a cut-off frequency. Connecting pin DCP to pin AGND disables DCP in both
I2C-bus and non-I2C-bus modes. The DCP is always disabled when the supply voltage on
pin VDDA drops below 8 V.
8.3.6 Supply voltage protection
UnderVoltage Protection (UVP) is activated when the supply voltage drops below the UVP
threshold. UVP triggers the UVP circuit causing the system to first mute and then stop
switching. The SVRR and SEL_MUTE pin capacitors will discharge. The information on
the MOD and ADS pins is latched while UVP is active. When the supply voltage rises
above the UVP threshold level, the system restarts. The UVP threshold is set at 6 V
minimum supply by default but can be changed to 8 V minimum supply using bit IB4[D7].
OverVoltage Protection (OVP) is activated when the supply voltage exceeds the OVP
threshold. The OVP (or load dump) circuit is activated and the power stages are shut
down. The SVRR and SEL_MUTE pin capacitors will discharge. When the supply voltage
drops below the OVP threshold level the system restarts.
8.4 Diagnostic output
8.4.1 Diagnostic table
The diagnostic information for I2C-bus mode and non-I2C-bus mode is shown in Table 7.
The instruction bitmap and data bytes are described in Table 9 and Table 11.
Pin DIAG has an open-drain output which must have an external pull-up resistor
connected to an external voltage. Pin DIAG can show both fixed and I2C-bus selectable
information.
Pin DIAG goes LOW when a short-circuit to one of the amplifier outputs occurs. The
microprocessor reads the failure information using the I2C-bus. The I2C-bus bits are set
for a short-circuit. These bits can be reset with the I2C-bus read command.
Even after the short circuit has been removed, the microprocessor knows what was wrong
after reading the I2C-bus. Old information is read when a single I2C-bus read command is
used. To read the current information, two read commands must be sent, one after
another.
When selected, pin DIAG gives the current diagnostic information. Pin DIAG is released
instantly when the failure is removed, independent of the I2C-bus latches.
TDF8530_SDS
Product short data sheet
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TDF8530
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I2C-bus controlled quad channel Class-D power amplifier
In non-I2C-bus mode, pins SCL and SDA behave as open drain outputs showing clip
detection diagnostics. Pin SCL shows clip diagnostics from channels 1 and 2. Pin SDA
shows clip diagnostics from channels 3 and 4.
Table 7.
Available data on pins DIAG, SCL and SDA
I2C-bus mode Non-I2C-bus mode
Diagnostic
Pin DIAG
Pin DIAG
Pin SCL
Pin SDA
Power-on reset
yes
yes
no
no
UVP or OVP
yes
yes
no
no
Clip detection
selectable
no
channels 1
and 2
channels 3
and 4
Temperature pre-warning
selectable
yes
no
no
OCP/WP
yes
yes
no
no
DCP
selectable
yes
no
no
OTP
yes
yes
no
no
Watchdog alarm
yes
yes
no
no
AC load detection; see Section 8.4.2.2
selectable
no
no
no
When OCP is triggered, the open-drain DIAG output is activated. The diagnostic output
signal during different short circuit conditions is illustrated in Figure 7.
shorted load
short to GND or VP line
AMPLIFIER
RESTART
NO
RESTART
pull up V
AGND = 0 V
≈50 ms ≈50 ms ≈50 ms
Fig 7.
001aai786
Diagnostic output for short circuit conditions
8.4.2 Load identification (I2C-bus mode only)
8.4.2.1
DC load detection
DC load detection is only available in I2C-bus mode and is controlled using bit IB2[D2].
The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load
detection is enabled when bit IB2[D2] = 1. Load detection takes place before the SVRR
capacitor is charged and before the class-D amplifier output stage starts switching. The
start-up time from Standby mode to Mute mode is increased by tdet(DCload) (see Figure 8).
TDF8530_SDS
Product short data sheet
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TDF8530
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I2C-bus controlled quad channel Class-D power amplifier
VP
OUTN
comparators
DOOR-SLAM
PROCESSOR
SPIKE
FILTER
OFFSET
GENERATOR
PGND1
VP
RL
OUTP
I2C bits
LOAD
DETECTION
Fig 8.
PGND2
001aao370
DC load detection circuit
out (V)
t (s)
tdet(DCload)
td(stb-mute)
Fig 9.
001aao371
DC load detection procedure
An inaudible current test pulse is created between the amplifier outputs. The external
capacitor connected to pin SEL_MUTE is used for timing. Load diagnostics based on the
voltage difference between pins OUTxP and OUTxN are shown in Figure 8 and Figure 9
SHORTED LOAD
SPEAKER LOAD
IB3[D3]= 0 (2 Ω speaker load detection) 0.5 Ω
1.6 Ω
IB3[D3]= 1 (4 Ω speaker load detection) 1.5 Ω
3.2 Ω
OPEN LOAD
20 Ω
80 Ω
aaa-000446
Fig 10. DC load detection limits
DC Load detection has built in spike filtering and a door-slam processor to remove
disturbances caused by switching relays in the wiring harness, EMI or the closing of a car
door. Reliable load detection is performed in one diagnostic cycle with these filter
techniques.
8.4.2.2
AC load detection (tweeter detection)
AC load detection is only available in I2C-bus mode and is controlled using bit IB1[D2].
The default setting for bit IB1[D2] = 0 disables AC load detection. When AC load detection
is enabled, the average amplifier load current is measured and compared with a reference
level. Pin DIAG is activated when this threshold is reached. Using this information, AC
load detection can be performed using a predetermined input signal frequency and level.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
The frequency and signal level should be chosen so that the average load current
exceeds the programmed current threshold when the AC coupled load (tweeter) is
present.
8.4.3 Clip detection
Clip detection gives information for clip levels exceeding a threshold defined as the THD
level of a sinusoidal output signal. The default value of this threshold is set at 0.2 %, but
can be set to 10 % using IB3[D4] = 1.
In non-I2C-bus mode pins SCL and SDA behave as open drain outputs showing
THD = 0.2 % clip detection diagnostics. Pin SCL shows clip diagnostics from channels 1
and 2. Pin SDA shows clip diagnostics from channels 3 and 4.
In I2C-bus mode pin DIAG is used as output of the clip detection circuitry for all channels
Setting bit IBx[D5] to logic 0 in I2C-bus mode defines which channel reports clip
information on the DIAG pin. Clip detection is disabled when the AC load detection is
active.
8.4.4 Start-up and shutdown sequence
To prevent switch on or switch off ‘pop noises’, a capacitor (CSVRR) connected to pin
SVRR is used to smooth start-up and shutdown. During start-up and shutdown, the output
voltage tracks the voltage on pin SVRR. Increasing CSVRR results in a longer start-up and
shutdown time. Enhanced pop noise performance is achieved by muting the amplifier until
the SVRR voltage reaches its final value and the outputs start switching. The value of
capacitor CON connected to pin SEL_MUTE determines the unmute and mute timing. The
voltage on pin SEL_MUTE determines the amplifier gain. Increasing CON increases the
unmute and mute times. In addition, a larger CON value increases the DC load detection
cycle time.
When the amplifier is switched off with an I2C-bus command or by pulling pin EN LOW,
the amplifier is first muted and then capacitor (CSVRR) is discharged.
In Slave mode, the device enters the off state immediately after capacitor (CSVRR) is
discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of
approximately 50 ms to allow slave devices to enter the off state.
A clock signal is needed during the start-up and shutdown sequence. When an external
clock is connected to pin OSCIO (in Slave mode), the clock must remain active during the
shutdown sequence for delay (td(1)) to ensure that the slaved TDF8530 devices are able to
enter the off state. A watchdog is added to protect against clock failure.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
VDDA
DIAG
td(1)
EN
ACGND
td(3)
IB1[D0] and
IB2[D0] = 0
DB4[D2]
td(mute-fgain)
td(2)
SEL_MUTE
SVRR
twake
td(stb-mute)
OUTn
tdet(DCload)
aaa-000447
(1) Shutdown hold delay.
(2) Master mode shutdown delay.
(3) Shutdown delay.
Fig 11. Start-up and shutdown timing in I2C-bus mode with DC load detection
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
VDDA
DIAG
td(2)
td(1)
EN
ACGND
td(mute-fgain)
td(3)
SEL_MUTE
SVRR
td(stb-mute)
OUTn
aaa-000649
(1) Shutdown hold delay.
(2) Shutdown delay.
(3) Master mode shutdown delay.
Fig 12. Start-up and shutdown timing in non-I2C-bus mode
9. I2C-bus specification
TDF8530 address with hardware address select.
Table 8.
RADS (k)
Product short data sheet
RMOD (k)
R/W
0[1]
6.8
33
100
100
44h
54h
64h
74h
1 = Read from TDF8530
33
42h
52h
62h
72h
0 = Write to TDF8530
6.8
40h
50h
60h
70h
0[1]
non-I2C-bus
[1]
TDF8530_SDS
I2C-bus write address selection using pins MOD and ADS
mode select
Short circuited to ground.
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
SCL
SCL
SDA
SDA
Mμp
START
Mμp
STOP
(1)
SLAVE
(1)
SLAVE
(2)
001aai792
001aai793
(1) When SCL is HIGH, SDA changes to form the start or
stop condition.
(1) SDA is allowed to change.
(2) All data bits must be valid on the positive edges of SCL.
Fig 13. I2C-bus start and stop conditions
SCL
1
MSB − 1
MSB
SDA
2
Mμp START
Fig 14. Data bits sent from Master microprocessor
(Mp)
7
8
LSB + 1
ADDRESS
9
ACK
1
2
MSB − 1
MSB
WRITE
SLAVE
7
LSB + 1
8
LSB
9
ACK
WRITE DATA
STOP
ACK(1)
ACK
001aai794
(1) To stop the transfer after the last acknowledge a stop condition must be generated.
Fig 15. I2C-bus write
SCL
1
MSB
SDA
Mμp
START
SLAVE
2
7
MSB − 1
LSB + 1
ADDRESS
8
9
ACK
1
MSB
2
7
MSB − 1
LSB + 1
8
9
LSB
ACK(1)
READ
ACKNOWLEDGE
STOP
READ DATA
001aai795
(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.
Fig 16. I2C-bus read
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
9.1 Instruction bytes
If R/W bit = 0, the TDF8530 expects four instruction bytes: IB1, IB2 IB3, and IB4.
Reserved instruction bits must be programmed to zero. After a power-on reset, all
instruction bits are set to zero.
Table 9.
Instruction byte descriptions
Bit Value Description
Instruction byte IB1
Instruction byte IB2
Instruction byte IB3
Instruction byte IB4
offset detection on pin
DIAG
offset protection on
latch information on pins
ADS and MOD when the
amplifier starts switching
undervoltage protection
threshold for 6 V minimum
supply
no offset detection on pin
DIAG
offset protection off
latch information on pins
ADS and MOD
undervoltage protection
threshold for 8 V minimum
supply
D6 0
channel 1 offset
monitoring on
channel 2 offset
monitoring on
channel 3 offset
monitoring on
channel 4 offset
monitoring on
1
channel 1 offset
monitoring off
channel 2 offset
monitoring off
channel 3 offset
monitoring off
channel 4 offset
monitoring off
D5 0
channel 1 clip detect on
pin DIAG
channel 2 clip detect on
pin DIAG
channel 3 clip detect on
pin DIAG
channel 4 clip detect on
pin DIAG
1
channel 1 no clip detect
on pin DIAG
channel 2 no clip detect
on pin DIAG
channel 3 no clip detect
on pin DIAG
channel 4 no clip detect
on pin DIAG
clip detection at
THD = 0.2 %
enable phase staggering
between channels 1 and
2, and 3 and 4
no thermal pre-warning on clip detection at
pin DIAG
THD = 10 %
no phase staggering
between channels 1 and
2, and 3 and 4
D7 0
1
D4 0
1
disable frequency hopping thermal pre-warning on
pin DIAG
enable frequency
hopping[1]
D3 0
oscillator frequency as set temperature pre-warning
at 140 C
with Rosc 10 %
1 detection level for
shorted load detection
1
oscillator frequency as set temperature pre-warning
at 120 C
with Rosc + 10 %
2 detection level for
shorted load detection
disable AC-load detection DC-load detection
on pin DIAG
disabled
fOSCIO = fosc[3]
enable AC-load detection
on pin DIAG
DC-load detection
enabled
fOSCIO = 2 fosc[3]
D1 0
channel 1 enabled
channel 2 enabled
channel 3 enabled
channel 4 enabled
1
channel 1 disabled
channel 2 disabled
channel 3 disabled
channel 4 disabled
D0 0
TDF8530 in Standby
mode
all channels operating
AD modulation
oscillator watchdog
enabled during amplifier
shut down only
1
TDF8530 in Mute or
Operating modes[4]
all channels muted
BD modulation
oscillator watchdog
enabled
D2 0
1
[1]
See IB1[D3].
[2]
See Table 10 “Phase shift bit settings” for information on IB4[D3] to IB4[D2].
[3]
See Table 4 “Oscillator modes”
[4]
See IB2[D0].
TDF8530_SDS
Product short data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 October 2011
phase shift in slave mode
with respect to master
clock, oscillator phase
shift bits IB4[D3] to
IB4[D2[2]
© NXP B.V. 2011. All rights reserved.
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 10.
Phase shift bit settings
D3
D2
0
0
0
0
1
1⁄
8
1
0
2⁄
8
1
3⁄
8
1
Phase
9.2 Data bytes
If R/W = 1, the TDF8530 sends four data bytes to the microprocessor (DB1, DB2, DB3
and DB4). All short diagnostic and offset protection bits and bits OTP, UVP and OVP are
latched. In addition, all bits are reset after a read operation except the DC load detection
bits (DBx[D3,D4], DB1[D6]). The default setting for all bits is logic 0.
Table 11.
Description of data bytes
Bit
Value DB1 channel 1
DB2 channel 2
DB3 channel 3
DB4 channel 4
D7
0
at least 1 instruction bit
set to logic 1
below maximum
temperature
reserved
reserved
1
all instruction bits are set
to logic 0
maximum temperature
protection occurred
-
-
0
invalid DC load data
no temperature warning
reserved
reserved
1
valid DC load data
temperature pre-warning
active
-
-
0
no overvoltage
no undervoltage
reserved
reserved
1
overvoltage protection
occurred
undervoltage protection
occurred
-
-
0
speaker load channel 1
speaker load channel 2
speaker load channel 3
speaker load channel 4
1
open load channel 1
open load channel 2
open load channel 3
open load channel 4
0
no shorted load channel 1 no shorted load channel 2 no shorted load channel 3 no shorted load channel 4
1
shorted load channel 1
shorted load channel 2
shorted load channel 3
shorted load channel 4
0
no offset
PLL not locked (slave
mode)
clock running
start up diagnostics
finished
1
offset detected on
channels selected with
IBx[D6]
PLL locked (slave mode)
clock failure
start up diagnostics in
progress
0
no short to VP channel 1
no short to VP channel 2
no short to VP channel 3
no short to VP channel 4
1
short to VP channel 1
short to VP channel 2
short to VP channel 3
short to VP channel 4
0
no short to ground
channel 1
no short to ground
channel 2
no short to ground
channel 3
no short to ground
channel 4
1
short to ground channel 1 short to ground channel 2 short to ground channel 3 short to ground channel 4
D6
D5
D4
D3
D2
D1
D0
Data byte DB1[D7] indicates whether the instruction bits have been set to logic 0. In
principle, DB1[D7] is set after a POR or when all the instruction bits are programmed to
logic 0. Pin DIAG is driven LOW when bit DB1[D7] = 1.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
10. Limiting values
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VP
supply voltage
Operating mode
off state
[1]
load dump; duration
50 ms; tr > 2.5 ms
[2]
Unit
-
29
V
1
+50
V
-
50
V
8
-
A
repetitive peak output
current
maximum output current
limiting
IOM
peak output current
non-repetitive
-
18
A
Isink(max)
maximum sink current
pin DIAG
0
5
mA
Vi
input voltage
referred to GNDD:
pins SCL, SDA and
OSCIO
0
5.5
V
referred to AGND:
pins ADS, MOD, SSM,
EN and SEL_MUTE
0
5.5
V
referred to AGND:
pins IN1P, IN2P, IN3P,
IN4P and INN
0
10
V
Vo
output voltage
referred to GNDD:
pin DIAG
0
10
V
RESR
equivalent series resistance
as seen between pins VP
and PGNDx
-
200
m
Tj
junction temperature
-
150
C
Tstg
storage temperature
55
+150
C
Tamb
ambient temperature
40
+85
C
-
2000
V
non-corner pins
(except pin 30, VDDA)
-
500
V
pin 30, VDDA
-
300
V
-
750
V
0
VP
V
electrostatic discharge
voltage
HBM
[3]
C = 100 pF;
Rs = 1.5 k
CDM
[4]
corner pins
V(prot)
Product short data sheet
Max
IORM
VESD
TDF8530_SDS
Min
protection voltage
[1]
Floating condition assumed for outputs.
[2]
Current limiting concept.
AC and DC short circuit
voltage of output pins
across load and to
supply and ground
[5]
[3]
Human Body Model (HBM).
[4]
Charged-Device Model (CDM).
[5]
The output pins are defined as the output pins of the filter connected between the TDF8530 output pins and
the load.
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
11. Thermal characteristics
Table 13.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
Rth(j-c)
Conditions
Typ
Unit
thermal resistance from junction to ambient in free air
35
K/W
thermal resistance from junction to case
1
K/W
12. Static characteristics
Table 14. Static characteristics
VP = 14.4 V; fosc = 315 kHz; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VP
supply voltage
Operating mode; on pins VDDA and
VP1 and VP2
6
14.4
24
V
IP
supply current
off state; Tj 85 C; VP = 14.4 V
-
2
10
A
Iq(tot)
total quiescent current
Operating mode; no load, no
snubbers and no filter connected
-
185
200
mA
Supply
I2C-bus interface: pins SCL and SDA
VIL
LOW-level input voltage
0
-
1.5
V
VIH
HIGH-level input voltage
2.3
-
5.5
V
VOL
LOW-level output voltage
0
-
0.4
V
0
-
0.8
V
2
-
5
V
pin EN; Mute mode or Operating
mode; non-I2C-bus mode
2
-
5
V
pin SEL_MUTE; Mute mode;
voltage on pin EN > 2 V
0
-
0.8
V
pin SEL_MUTE; Operating mode;
voltage on pin EN > 2 V
3
-
5
V
pin EN; 2.5 V
-
-
5
A
pin SEL_MUTE; Operating mode;
0.8 V
-
-
50
A
pin SDA; Iload = 5 mA
Enable and SEL_MUTE input: pins EN and SEL_MUTE
Vi
input voltage
pin EN; off state
pin EN; Standby mode;
mode
Ii
input current
TDF8530_SDS
Product short data sheet
I2C-bus
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 14. Static characteristics …continued
VP = 14.4 V; fosc = 315 kHz; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THDclip
total harmonic distortion clip
detection level
IB3[D4] = 0
-
0.2
-
%
-
10
-
%
Vth(offset)
threshold voltage for offset
detection
VDDA > 8 V
1
2
3
V
VOL
LOW-level output voltage
DIAG, SCL or SDA pins; diagnostic
activated; Io = 1 mA
-
-
0.3
V
IL
leakage current
DIAG, SCL or SDA pins; diagnostic
not activated
-
-
50
A
-
2.45
-
V
input ACGND pin
-
2.45
-
V
half supply reference SVRR pin
-
7.2
-
V
-
-
25
mV
-
-
70
mV
stabilizer output in Mute mode and
Operating mode
-
11
-
V
undervoltage protection level 1;
falling supply; IB4[D7] = 0
5.5
5.75
6
V
undervoltage protection level 2;
falling supply; IB4[D7] = 1
7.2
7.6
8
V
overvoltage protection level
26.2
27
-
V
VP at which a POR occurs
-
4.4
-
V
current limiting concept
8
9
-
A
Diagnostic output
IB3[D4] = 1
[1]
Audio inputs; pins INN, IN1P, IN2P, IN3P and IN4P
Vi
input voltage
SVRR voltage and ACGND input bias voltage in Mute and Operating modes
Vref
reference voltage
Amplifier outputs; pins OUT1N, OUT1P, OUT2N, OUT2P, OUT3N, OUT3P, OUT4N and OUT4P
VO(offset)
output offset voltage
Mute mode
Operating mode
[2]
Stabilizer output; pins VSTAB1 and VSTAB2
Vo
output voltage
Voltage protections
V(prot)
protection voltage
Current protection
IO(ocp)
overcurrent protection output
current
Temperature protection
Tprot
protection temperature
-
152
-
C
Tact(th_fold)
thermal foldback activation
temperature
gain = 1 dB
-
145
-
C
Tj(AV)(warn1)
average junction temperature
for pre-warning 1
IB2[D3] = 0; non-I2C-bus mode
-
140
-
C
Tj(AV)(warn2)
average junction temperature
for pre-warning 2
IB2[D3] = 1
-
120
-
C
DC load detection levels: I2C-bus mode only
TDF8530_SDS
Product short data sheet
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22 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 14. Static characteristics …continued
VP = 14.4 V; fosc = 315 kHz; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Zth(load)
load detection threshold
impedance
for normal speaker load;
IB3[D3] = 0; 1 shorted load
detection level
1.6
-
20
for normal speaker load;
IB3[D3] = 1; 2 shorted load
detection level
3.2
-
20
80
-
-
for shorted speaker load;
IB3[D3] = 0; 1 shorted load
detection level
-
-
0.5
for shorted speaker load;
IB3[D3] = 1; 2 shorted load
detection level
-
-
1.5
-
500
-
mA
Zth(open)
open load detection threshold
impedance
Zth(short)
shorted load detection
threshold impedance
AC load detection levels: I2C-bus mode only
Ith(o)det(load)AC
AC load detection output
threshold current
Start-up/shut-down/mute timing
twake
wake-up time
on pin EN before first I2C-bus
transmission is recognized
[3]
-
-
500
s
tdet(DCload)
DC load detection time
CON = 470 nF
[3]
-
320
-
ms
td(stb-mute)
delay time from standby to
mute
measured from amplifier enabling
to start of unmute (no DC load
detection); CSVRR = 47 F
-
125
-
ms
td(mute-fgain)
mute to full gain delay time
CON = 470 nF
-
50
-
ms
td
delay time
shutdown delay time from EN pin
LOW to SVRR LOW; voltage on
pin SVRR < 1 V; CSVRR = 47 F;
CON = 470 nF
130
190
250
ms
shutdown hold delay time from pin
EN LOW to ACGND LOW; voltage
on pin ACGND < 1 V; Master
mode
-
400
-
ms
hold delay in Master mode to allow
slaved devices to shut down
fosc = 315 kHz
-
50
-
ms
[1]
[4]
Maximum leakage current from DCP pin to ground = 3 A.
[2]
DC output offset voltage is applied to the output gradually during the transition between Mute mode and Operating mode.
[3]
I2C-bus mode only.
[4]
The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.
TDF8530_SDS
Product short data sheet
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23 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
12.1 Switching characteristics
Table 15. Switching characteristics
VP = 14.4 V; Tamb = 25 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Internal oscillator
fPWM
PWM frequency
Rosc = 39 k
-
315
-
kHz
fPWM(range)
PWM frequency range
typical fixed frequency and Spread
spectrum mode frequency based on
the resistor value connected to pin
OSCSET for the master setting
-
300 to 500 -
kHz
22
39
49
k
Master/slave setting (OSCIO pin)
Rosc
oscillator resistance
resistor value on pin OSCSET;
master setting
VOL
LOW-level output voltage
output
-
-
0.8
V
VOH
HIGH-level output voltage
output
4
-
-
V
fo
output frequency
IB3[D2] = 0; Rosc = 49 k
200
250
300
kHz
IB3[D2] = 1; Rosc = 49 k
400
500
600
kHz
IB3[D2] = 0; Rosc = 22 k
460
500
575
kHz
IB3[D2] = 1; Rosc = 22 k
920
1050
1150
kHz
VIL
LOW-level input voltage
input
-
-
0.8
V
VIH
HIGH-level input voltage
input
3
-
-
V
fi
input frequency
IB3[D2] = 0
300
-
500
kHz
600
-
1000
kHz
output, used by slave with PLL
operation
-
-
560
pF
output, used by slave without PLL
operation
-
-
68
pF
IB3[D2] = 1
COSCIO
capacitance on pin OSCIO
[1]
Spread spectrum mode setting
fosc
oscillator frequency variation
between maximum and minimum
values; Spread spectrum mode
activated
-
10
-
%
fsw
switching frequency
Spread spectrum mode activated;
CSSM = 1 F
-
7
-
Hz
change positive; IB1[D4] = 1;
IB1[D3] = 1
-
fosc + 10 % -
kHz
change negative; IB1[D4] = 1;
IB1[D3] = 0
-
fosc 10 % -
kHz
Frequency hopping
fosc(int)
[1]
internal oscillator frequency
Amplifier output stage switching frequency is half the external oscillator frequency.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
13. Dynamic characteristics
Table 16. Dynamic characteristics
VP = 14.4 V; RL = 4 ; fi = 1 kHz; fosc = 315 kHz; Rs(L) < 0.04 [1]; Tamb = 25 C; unless otherwise specified.
Symbol
Po
Parameter
Conditions
output power
THD = 1 %; RL = 4
[2]
Min
Typ
Max
Unit
18
20
-
W
THD = 10 %; RL = 4
24
26
-
W
square wave (EIAJ); RL = 4
-
40
-
W
VP = 24 V; THD = 10 %; RL = 4
-
70
-
W
THD = 1 %; RL = 2
29
33
-
W
THD = 10 %; RL = 2
39
45
-
W
square wave (EIAJ); RL = 2
-
66
-
W
-
100
-
W
-
0.02
0.1
%
25
26
27
dB
60
70
-
dB
VP = 24 V; THD = 10 %; RL = 2
fi = 1 kHz; Po = 1 W
THD
total harmonic distortion
Gv(cl)
closed-loop voltage gain
cs
channel separation
fi = 1 kHz; Po = 1 W
SVRR
supply voltage rejection ratio
Operating mode
[3]
BD mode; fripple = 100 Hz
[4]
-
70
-
dB
BD mode; fripple = 1 kHz
[4]
-
70
-
dB
[4]
-
70
-
dB
[4]
-
70
-
dB
30
50
75
k
Mute mode
BD mode; fripple = 1 kHz
Off or Standby mode
BD mode; fripple = 1 kHz
Zi(dif)
differential input impedance
Vn(o)
output noise voltage
Operating mode
BD mode
[5]
-
60
77
V
AD mode
[5]
-
100
140
V
BD mode
[6]
-
25
32
V
AD mode
[6]
-
95
110
V
-
0
1
dB
70
-
-
dB
Mute mode
bal(ch)
channel balance
mute
mute attenuation
CMRR
common mode rejection ratio
Vi(cm) = 1 V RMS
65
80
-
dB
po
output power efficiency
Po = 20 W
-
90
-
%
[7]
[1]
Rs(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB
traces or wiring between the output pin of the TDF8530 and the inductor to the measurement point. LC filter dimensioning is L = 10 H,
C = 1 F for 4 load and L = 5 H, C = 2.2 F for 2 load.
[2]
Output power is measured indirectly based on RDSon measurement.
[3]
Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may
not be 100 % tested.
[4]
Vripple = Vripple(max) = 1 V (p-p); Rs = 0 .
[5]
B = 22 Hz to 20 kHz, AES brick wall, Rs = 0 .
[6]
B = 22 Hz to 20 kHz, AES brick wall, independent of Rs.
[7]
Vi = Vi(max) = 0.5 V RMS.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
14. Application information
14.1 Output power estimation
The output power, just before clipping, can be estimated using Equation 1:
Po 1
2
RL
f osc
1 – t
---------------------------------------------------- -------- V P
w
min
R L + 2 R DSon + R s
2
= ------------------------------------------------------------------------------------------------------------------------------------- W
2 RL
(1)
Where,
•
•
•
•
•
•
VP = supply voltage (V)
RL = load impedance ()
RDSon = drain source on-state resistance ()
Rs = series resistance of the output inductor ()
tw(min) = minimum pulse width(s) depending on output current
fosc = oscillator frequency in Hz (typically 315 kHz)
The output power at 10 % THD can be estimated using Equation 2:
P o 2 = 1.25 P o 1
(2)
where Po(1) = 0.5 % and Po(2) = 10 %
Figure 17 and Figure 18 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of supply voltage for different load impedances.
TDF8530_SDS
Product short data sheet
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26 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
aaa-000448
100
Po
(W)
aaa-000449
120
Po
(W)
80
80
60
(1)
(1)
40
(2)
(2)
40
20
0
0
8
12
16
20
24
8
12
VP (V)
16
20
24
VP (V)
THD = 0.5 %.
THD = 10 %.
RDSon = 0.190 (at Tj = 100 C), Rs = 0.05 ,
tw(min) = 150 ns and IO(ocp) = 9 A (typical).
RDSon = 0.190 (at Tj = 100 C), Rs = 0.05 ,
tw(min) = 150 ns and IO(ocp) = 9 A (typical).
(1) RL = 2 .
(1) RL = 2 .
(2) RL = 4 .
(2) RL = 4 .
Fig 17. Po as a function of VP with THD = 0.5 %
Fig 18. Po as a function of VP with THD = 10 %
14.2 Output current limiting
The peak output current is internally limited to 8 A minimum. During normal operation, the
output current should not exceed this threshold level otherwise the output signal will be
distorted. The peak output current can be estimated using Equation 3:
VP
I o ----------------------------------------------------- 8 [A]
R L + 2 R DSon + R s
•
•
•
•
•
(3)
Io = output current (A)
VP = supply voltage (V)
RL = load impedance ()
RDSon = on-resistance of power switch ()
Rs = series resistance of output inductor ()
Example: A 2 speaker can be used with a supply voltage of 22 V before current limiting
is triggered.
Current limiting (clipping) avoids audio holes but causes distortion similar to voltage
clipping.
14.3 Speaker configuration and impedance
A flat-frequency response (due to a 2nd order Butterworth filter) is obtained by changing
the values of low-pass filter components (LLC, CLC) based on the speaker configuration
and impedance. Figure 19 shows the circuit and Table 17 gives the required values.
TDF8530_SDS
Product short data sheet
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27 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
out-
LLC
CLC
TDF8530
load
out+
LLC
CLC
aaa-000450
Fig 19. Filter component values
Table 17.
Filter component values
Load impedance ()
LLC (H)
CLC (F)
2
5
2.2
4
10
1
14.4 Heat sink requirements
In most applications, it is necessary to connect an external heat sink to the TDF8530.
Thermal foldback activates at Tj = 140 C. The expression in Equation 4 shows the
relationship between the maximum power dissipation before activation of thermal foldback
and the total thermal resistance from junction to ambient:
T j max – T amb
R th j-a = ----------------------------------- K/W
P max
(4)
Pmax is determined by the efficiency () of the TDF8530. The efficiency measured as a
function of output power is given in Figure 25. The power dissipation can be derived as a
function of output power (see Figure 24).
Example 1:
•
•
•
•
•
•
VP = 14.4 V
Po = 4 25 W into 4 (THD = 10 % continuous)
Tj(max) = 140 C
Tamb = 25 C
Pmax = 9.5 W (from Figure 24)
The required Rth(j-a) = 115 C / 9.5 W = 12 K/W
The total thermal resistance Rth(j-a) consists of: Rth(j-c) + Rth(c-h) + Rth(h-a)
Where:
• Thermal resistance from junction to case (Rth(j-c)) = 1 K/W
• Thermal resistance from case to heat sink (Rth(c-h)) = 0.5 K/W to 1 K/W (depending on
mounting)
• Thermal resistance from heat sink to ambient (Rth(h-a)) would then be
12 (1 + 1) = 10 K/W.
If an audio signal has a crest factor of 10 (the ratio between peak power and average
power = 10 dB) then Tj will be much lower.
TDF8530_SDS
Product short data sheet
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Example 2:
•
•
•
•
•
•
VP = 14.4 V
Po = 4 (25 W / 10) = 4 2.5 W into 4 (audio with crest factor of 10)
Tamb = 25 C
Pmax = 4 W (from Figure 24)
Rth(j-a) = 12 K/W
Tj(max) = 25 C + (4 W 12 K/W) = 73 C
14.5 Curves measured in reference design
aaa-000451
102
THD + N
(%)
THD + N
(%)
10
10
1
1
10-1
aaa-000452
102
(1)
(1)
10-1
(2)
(2)
10-2
(3)
10-3
10-1
1
10-2
102
10
10-3
10-1
(3)
1
Po (W)
(1) VP = 14.4 V; RL = 2 at 10 kHz.
(1) VP = 14.4 V; RL = 4 at 10 kHz.
(2) VP = 14.4 V; RL = 2 at 1 kHz.
(2) VP = 14.4 V; RL = 4 at 1 kHz.
(3) VP = 14.4 V; RL = 2 at 100 kHz.
(3) VP = 14.4 V; RL = 4 at 100 kHz.
Fig 20. THD + N as a function of output power with a
2 load
TDF8530_SDS
Product short data sheet
102
10
Po (W)
Fig 21. THD + N as a function of output power with a
4 load
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
aaa-000453
1
aaa-000454
1
THD + N
(%)
THD + N
(%)
10-1
10-1
(2)
(1)
(1)
10-2
10-2
10-3
102
10
103
104
105
(2)
10-3
102
10
103
104
f (Hz)
(1) VP = 14.4 V; RL = 2 at 10 W.
(1) VP = 14.4 V; RL = 4 at 10 W.
(2) VP = 14.4 V; RL = 2 at 1 W.
(2) VP = 14.4 V; RL = 4 at 1 W.
Fig 22. THD + N as a function of frequency with a 2
load
aaa-000456
14
PD
(W)
12
105
f (Hz)
Fig 23. THD + N as a function of frequency with a 4
load
aaa-000455
100
ƞ
(%)
80
10
60
8
6
40
4
20
2
0
0
0
5
10
15
20
25
30
Po (W)
35
VP = 14.4 V; RL = 4 ; f = 1 kHz.
Product short data sheet
5
10
15
20
25
30
Po (W)
35
VP = 14.4 V; RL = 4 ; f = 1 kHz.
Fig 24. Power dissipation as a function of output
power with a 4 load; all channels driven
TDF8530_SDS
0
Fig 25. Efficiency as a function of output power with a
4 load; all channels driven
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30 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
aaa-000458
35
PD
(W)
30
aaa-000457
100
ƞ
(%)
80
25
60
20
15
40
10
20
5
0
0
0
10
20
30
40
50
0
10
20
30
Po (W)
VP = 14.4 V; RL = 4 ; f = 1 kHz.
Fig 26. Power dissipation as a function of output
power with a 2 load; all channels driven
Product short data sheet
50
Po (W)
VP = 14.4 V; RL = 4 ; f = 1 kHz.
TDF8530_SDS
40
Fig 27. Efficiency as a function of output power with a
2 load; all channels driven
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TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
14.6 Typical application schematics
bead
100 μF
35 V
bead
bead
VP
100 μF
35 V
VP1
VP2
VPA
PGND1
1000 μF
35 V
GND
PGND2
LLC
OUT1P
100 nF
1 μF
CLC
10 Ω
VSTAB1
BOOT1P
22 Ω
470 pF
470 pF
470 pF
OUT1P
470 pF
22 Ω
OUT1N
CLC
10 Ω
100 nF
OUT1N
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
GNDD/HW
100 nF
VDDD
39 kΩ
OSCIO
BOOT1N
VP1
LLC
VP1
MASTER MODE
100 nF
OSCSET
15 nF
LLC
OUT2N
100 nF
44
15 nF
PGND1
VP1
1
1 μF
SSM
spread spectrum
mode
SDA
100 nF
CLC
PGND1
10 Ω
PGND1
22 Ω
470 pF
470 pF
VP1
470 pF
470 pF
PGND1
BOOT2N
SCL
non-I2C-bus
mode
ADS
15 nF
OUT2N
6.8 kΩ
MOD
BD modulation setting
22 Ω
CLC
OUT2P
OUT2P
10 Ω
100 nF
LLC
BOOT2P
LLC
BOOT3P
OUT3P
100 nF
DC offset protection
disabled (1)
DCP
15 nF
TDF8530
12
33
13
32
10 kΩ
DIAG
VPull-up
EN
enable
15 nF
CLC
10 Ω
OUT3P
SEL_MUTE
mute/on
22 Ω
470 nF
470 pF
OUT3N
470 pF
PGND2
VP2
470 pF
BOOT3N
470 pF
22 Ω
CLC
OUT3N
PGND2 PGND2
10 Ω
100 nF
100 nF
LLC
BOOT4N
OUT4N
100 nF
CLC
VP2
VP2
LLC
OUT4N
22 Ω
470 pF
PGND2
VP2
470 pF
OUT4P
BOOT4P
22 Ω
10 Ω
100 nF
OUT4P
15
30
SVRR
16
29
17
28
18
27
19
26
VDDA
AGND
ACGND
bead
47 μF
VPA
2.2 μF
CACGND 100 nF
CINN
2.2 μF
IN1P
CIN1P
470 nF
IN2P
CIN2P
470 nF
IN3P
CIN3P
470 nF
IN4P
CIN4P
470 nF
INN
20
25
IN1P
IN2P
15 nF
470 pF
CLC
31
15 nF
10 Ω
470 pF
14
15 nF
1 μF
VSTAB2
21
22
24
23
LLC
IN3P
IN4P
aaa-000459
4 BTL mode in non-I2C-bus mode with DC offset protection disabled, Spread spectrum mode enabled, BD modulation.
(1) See Section 8.3.5 on page 11 for detailed information on DC offset protection.
Fig 28. Example application diagram 4 BTL in non-I2C-bus mode
TDF8530_SDS
Product short data sheet
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32 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
bead
100 μF
35 V
bead
bead
VP
100 μF
35 V
VP1
VP2
VPA
PGND1
1000 μF
35 V
GND
PGND2
LLC
OUT1P
100 nF
1 μF
CLC
10 Ω
VSTAB1
BOOT1P
22 Ω
470 pF
470 pF
470 pF
OUT1P
470 pF
22 Ω
OUT1N
CLC
10 Ω
100 nF
OUT1N
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
GNDD/HW
100 nF
VDDD
39 kΩ
OSCIO
BOOT1N
VP1
LLC
VP1
SSM
fixed frequency
SDA
100 nF
CLC
PGND1
10 Ω
PGND1
22 Ω
470 pF
BOOT2N
470 pF
PGND1
VP1
470 pF
connect to uP
SCL
ADS
RADS
MOD
RMOD
15 nF
OUT2N
470 pF
22 Ω
CLC
OUT2P
10 Ω
100 nF
OUT2P
LLC
BOOT2P
BOOT3P
OUT3P
CLC
10 Ω
OUT3P
TDF8530
12
33
13
32
14
31
15
30
10 kΩ
DIAG
VPull-up
EN
enable
SEL_MUTE
470 nF
470 pF
470 pF
VP2
470 pF
470 pF
OUT3N
PGND2
PGND2 PGND2
10 Ω
100 nF
100 nF
LLC
BOOT4N
OUT4N
CLC
VP2
VP2
LLC
OUT4N
22 Ω
470 pF
OUT4P
PGND2
VP2
470 pF
BOOT4P
22 Ω
10 Ω
100 nF
29
17
28
18
27
19
26
AGND
ACGND
bead
47 μF
VPA
2.2 μF
CACGND 100 nF
CINN
2.2 μF
IN1P
CIN1P
470 nF
IN2P
CIN2P
470 nF
IN3P
CIN3P
470 nF
IN4P
CIN4P
470 nF
INN
20
25
IN1P
IN2P
15 nF
470 pF
CLC
16
VDDA
15 nF
10 Ω
470 pF
SVRR
15 nF
BOOT3N
CLC
OUT4P
DC offset protection
enabled (1)
15 nF
22 Ω
100 nF
I2C address range select
4.7 μF
DCP
22 Ω
OUT3N
I2C address select
15 nF
LLC
100 nF
MASTER MODE
100 nF
OSCSET
15 nF
LLC
OUT2N
100 nF
44
15 nF
PGND1
VP1
1
1 μF
VSTAB2
21
22
24
23
IN3P
IN4P
LLC
aaa-000460
4 BTL mode in I2C-bus mode with DC offset protection enabled, Spread spectrum mode disabled.
(1) See Section 8.3.5 on page 11 for detailed information on DC offset protection.
Fig 29. Example application diagram: 4 BTL in I2C-bus mode
TDF8530_SDS
Product short data sheet
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33 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
15. Package outline
HSOP44: plastic, heatsink small outline package; 44 leads; low stand-off height
SOT1131-1
A
E
x
D
c
y
X
E2
HE
v
A
D1
D2
1
22
pin 1 index
Q
A
A2
E1
(A3)
A4
θ
Lp
detail X
44
23
Z
w
bp
e
0
5
A
A2
3.5
3.5
3.3
3.2
Unit
mm
Z
θ
0.07
1.30
1.13
0.95
8°
4°
0°
scale
Dimensions
max
nom
min
10 mm
y
A3
A4
bp
+0.08 0.38
0.35 +0.02 0.30
−0.04 0.25
c
D(1)
D1
D2
E(1)
E1
E2
0.32
0.25
0.23
16.0
15.9
15.8
13.0
12.8
12.6
1.10
1.00
0.90
11.1
11.0
10.9
6.2
6.0
5.8
2.9
2.7
2.5
e
HE
Lp
Q
v
w
x
0.65
14.5
14.2
13.9
1.10
0.91
0.80
1.7
1.6
1.5
0.25
0.12
0.03
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
sot1131-1_po
European
projection
Issue date
09-03-23
10-08-18
SOT1131-1
Fig 30. Package outline SOT1131-1 (HSOP44)
TDF8530_SDS
Product short data sheet
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34 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
TDF8530_SDS
Product short data sheet
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35 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 18 and 19
Table 18.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 19.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
TDF8530_SDS
Product short data sheet
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36 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Abbreviations
Table 20.
TDF8530_SDS
Product short data sheet
Abbreviations
Abbreviation
Description
BCDMOS
Bipolar Complementary and double Diffused Metal-Oxide Semiconductor
BTL
Bridge-Tied Load
DCP
DC offset Protection
DMOST
double Diffused Metal-Oxide Semiconductor Transistor
EMI
ElectroMagnetic Interference
THD
Total Harmonic Distortion
I2C
Inter-Integrated Circuit
LSB
Least Significant Bit
Mp
Master microprocessor
MSB
Most Significant Bit
NDMOST
N-type double Diffused Metal-Oxide Semiconductor Transistor
OCP
OverCurrent Protection
OTP
OverTemperature Protection
OVP
OverVoltage Protection
PLL
Phase-Locked Loop
POR
Power-On Reset
PWM
Pulse-Width Modulation
SOI
Silicon-On-Insulator
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 October 2011
© NXP B.V. 2011. All rights reserved.
37 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Table 20.
Abbreviations …continued
Abbreviation
Description
TFP
Thermal Foldback Protection
UVP
UnderVoltage Protection
WP
Window Protection
18. Revision history
Table 21.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDF8530_SDS v.3
20111020
Product short data sheet
-
TDF8530_SDS v.2
Modifications:
TDF8530_SDS v.2
Modifications:
TDF8530_SDS v.1
TDF8530_SDS
Product short data sheet
•
Data sheet status changed from Objective short data sheet to Product short data sheet.
20111014
•
Objective short data sheet
-
TDF8530_SDS v.1
Changed Table 15 on page 24: Changes to internal oscillator parameters and output
frequency data.
20111011
Objective short data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 October 2011
-
© NXP B.V. 2011. All rights reserved.
38 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
TDF8530_SDS
Product short data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 October 2011
© NXP B.V. 2011. All rights reserved.
39 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDF8530_SDS
Product short data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 October 2011
© NXP B.V. 2011. All rights reserved.
40 of 41
TDF8530
NXP Semiconductors
I2C-bus controlled quad channel Class-D power amplifier
21. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.4
8.4.1
8.4.2
8.4.2.1
8.4.2.2
8.4.3
8.4.4
9
9.1
9.2
10
11
12
12.1
13
14
14.1
14.2
14.3
14.4
14.5
14.6
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 6
Master and slave mode selection . . . . . . . . . . . 6
Operation mode selection. . . . . . . . . . . . . . . . . 6
Modulation mode . . . . . . . . . . . . . . . . . . . . . . . 7
Phase staggering (Slave mode) . . . . . . . . . . . . 8
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 10
Overtemperature protection . . . . . . . . . . . . . . 10
Overcurrent protection . . . . . . . . . . . . . . . . . . 10
Window protection . . . . . . . . . . . . . . . . . . . . . 10
DC offset protection . . . . . . . . . . . . . . . . . . . . 11
Supply voltage protection . . . . . . . . . . . . . . . . 11
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 11
Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 11
Load identification (I2C-bus mode only) . . . . . 12
DC load detection . . . . . . . . . . . . . . . . . . . . . . 12
AC load detection (tweeter detection) . . . . . . 13
Clip detection . . . . . . . . . . . . . . . . . . . . . . . . . 14
Start-up and shutdown sequence . . . . . . . . . . 14
I2C-bus specification . . . . . . . . . . . . . . . . . . . . 16
Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 18
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal characteristics . . . . . . . . . . . . . . . . . 21
Static characteristics. . . . . . . . . . . . . . . . . . . . 21
Switching characteristics . . . . . . . . . . . . . . . . 24
Dynamic characteristics . . . . . . . . . . . . . . . . . 25
Application information. . . . . . . . . . . . . . . . . . 26
Output power estimation. . . . . . . . . . . . . . . . . 26
Output current limiting . . . . . . . . . . . . . . . . . . 27
Speaker configuration and impedance . . . . . . 27
Heat sink requirements. . . . . . . . . . . . . . . . . . 28
Curves measured in reference design . . . . . . 29
Typical application schematics . . . . . . . . . . . . 32
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 34
Soldering of SMD packages . . . . . . . . . . . . . . 35
16.1
16.2
16.3
16.4
17
18
19
19.1
19.2
19.3
19.4
20
21
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
35
35
36
37
38
39
39
39
39
40
40
41
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 October 2011
Document identifier: TDF8530_SDS
