TDF8544
I2C-bus controlled 4 50 W power amplifier
Rev. 2 — 29 August 2011
Product data sheet
1. General description
The TDF8544 is one of a new generation of complementary quad Bridge-Tied Load (BTL)
audio power amplifiers intended for automotive applications. It has full I2C-bus controlled
diagnostics, including start-up diagnostics. The TDF8544 can operate at a battery voltage
as low as 6 V making this amplifier suitable for stop/start-car operation.
The amplifier uses a complementary DMOS output stage in a Silicon-On-Insulator (SOI)based BCD process. The DMOS output stage ensures a high power output signal with
perfect sound quality. The SOI-based BCD process ensures a robust amplifier, where
latch-up cannot occur, with good separation between the four independent channels, with
every component isolated and without substrate currents.
2. Features and benefits
Stop/start-car prepared: keeps operating without audible disturbance during engine
start at a battery voltage as low as 6 V
Operates in either legacy (non I2C-bus) or I2C-bus modes (3.3 V and 5 V compliant)
Four hardware-programmable I2C-bus addresses
Can drive 2 and 4 loads
Speaker fault detection
Start-up diagnostics with load detection: open, short, present; filtered for door-slam
and chatter relays
AC load (tweeter) detection with low and high current mode
Gain select after start-up without audible disturbance
Independent selectable soft mute of front and rear channels
Programmable gain (26 dB and 16 dB), independently programmable for the front and
rear channels
Line driver mode supports engine start at a battery voltage as low as 6 V (16 dB and
mid-tap voltage 0.25VP)
Programmable clip detect: 2 %, 5 % or 10 %
Programmable thermal pre-warning
Pin STB can be programmed/multiplexed with second-clip detect
Clip information of each channel can be directed separately to pin DIAG or pin STB
Independent enabling of thermal-, clip- or load fault information (short across the load
or to VP or to ground) on pin DIAG
Loss-of-ground and open VP safe (minimum series resistance required)
All amplifier outputs short-circuit proof to ground, supply voltage and across the load
(channel independent)
All pins short-circuit proof to ground
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Temperature controlled gain reduction to prevent audio holes at high junction
temperatures
Programmable low battery voltage detection to enable 7.5 V or 6 V minimum battery
voltage operation
Overvoltage protection (load-dump safe up to VP = 50 V) with overvoltage pre-warning
at 16 V
Offset detection
3. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VP(oper)
operating supply
voltage
RL = 4
6
14.4
18
V
Iq
quiescent current
no load
-
260
350
mA
no load; VP = 7 V
-
190
-
mA
RL = 4 ; VP = 14.4 V; THD = 0.5 %
19
22
-
W
RL = 4 ; VP = 14.4 V; THD = 10 %
26
28
-
W
Po
Po(max)
output power
maximum output
power
RL = 2 ; VP = 14.4 V; THD = 10 %
45
51
-
W
RL = 4 ; VP = 15.2 V; Vi = 2 V RMS square wave
47
50
-
W
RL = 2 ; VP = 14.4 V; Vi = 2 V RMS square wave
70
75
-
W
-
0.01
0.1
%
amplifier mode
-
40
60
V
line driver mode
-
25
33
V
THD
total harmonic
distortion
Po = 1 W to 12 W; fi = 1 kHz; RL = 4
Vn(o)
output noise voltage
filter 20 Hz to 22 kHz (6th order); RS = 50
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDF8544J/N2
DBS27P
plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length
6.8 mm)
SOT827-1
TDF8544SD/N2
RDBS27P
plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads
(row spacing 2.54 mm)
SOT878-1
TDF8544TH/N2
HSOP36
plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-1
TDF8544
Product data sheet
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
5. Block diagram
ADSEL
SDA SCL
1 (10) 26 (8) 23 (7)
TDF8544
VP1
VP2
21 (3)
7 (16)
ENGINE START
PROTECTION
5 (9)
STB
IN3
2 (11)
STANDBY/
FAST MUTE
SELECT
DIAGNOSTIC/
CLIP DETECT
I2C-BUS
16 (29)
18 (2)
MUTE
DIAG
26 dB/
16 dB
20 (1)
OUT3+
OUT3-
PROTECTION/
DIAGNOSTIC
IN1
12 (25)
10 (17)
MUTE
26 dB/
16 dB
8 (18)
OUT1+
OUT1-
PROTECTION/
DIAGNOSTIC
IN4
15 (28)
22 (6)
MUTE
26 dB/
16 dB
24 (4)
OUT4+
OUT4-
PROTECTION/
DIAGNOSTIC
IN2
13 (26)
6 (13)
MUTE
26 dB/
16 dB
VP
4 (15)
OUT2+
OUT2-
PROTECTION/
DIAGNOSTIC
27 (36)
11 (24)
14 (27)
SVR
SGND
17 (30)
ACGND
9 (23)
PGND1
3 (14)
PGND2
19 (32)
PGND3
TAB
25 (5)
PGND4
001aan045
Pin numbers in parenthesis relate to type TDF8544TH (package HSOP36).
Fig 1.
TDF8544
Product data sheet
Block diagram
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
6. Pinning information
6.1 Pinning
ADSEL
1
STB
2
PGND2
3
OUT2-
4
DIAG
5
OUT2+
6
VP2
7
OUT1-
8
PGND1
9
OUT1+ 10
SVR 11
IN1 12
IN2 13
SGND 14
TDF8544J/SD
IN4 15
IN3 16
ACGND 17
OUT3+ 18
PGND3 19
OUT3- 20
VP1 21
OUT4+ 22
SCL 23
OUT4- 24
PGND4 25
SDA 26
TAB 27
001aan046
Fig 2.
TDF8544
Product data sheet
Pin configuration of types TDF8544J/SD (packages DBS27P and RDBS27P)
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
TAB 36
1
OUT3-
n.c. 35
2
OUT3+
n.c. 34
3
VP1
n.c. 33
4
OUT4-
PGND3 32
5
PGND4
n.c. 31
6
OUT4+
ACGND 30
7
SCL
IN3 29
8
SDA
IN4 28
9
DIAG
SGND 27
TDF8544TH
10 ADSEL
IN2 26
11 STB
IN1 25
12 n.c.
SVR 24
13 OUT2+
PGND1 23
14 PGND2
n.c. 22
15 OUT2-
n.c. 21
16 VP2
n.c. 20
17 OUT1+
n.c. 19
18 OUT1001aan047
Fig 3.
TDF8544
Product data sheet
Pin configuration of type TDF8544TH (package HSOP36)
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
6.2 Pin description
TDF8544
Product data sheet
Table 3.
Pin description
Symbol
Pin
Description
TDF8544J/SD
TDF8544TH
ADSEL
1
10
I2C-bus address select
STB
2
11
stand-by (I2C-bus mode) or mode pin (legacy mode)
programmable second clip indicator
PGND2
3
14
channel 2 power ground
OUT2
4
15
channel 2 negative output (right rear)
DIAG
5
9
diagnostic and clip detection output
OUT2+
6
13
channel 2 positive output (right rear)
VP2
7
16
power supply voltage 2
OUT1
8
18
channel 1 negative output (right front)
PGND1
9
23
channel 1 power ground
OUT1+
10
17
channel 1 positive output (right front)
SVR
11
24
half supply voltage filter capacitor
IN1
12
25
channel 1 input
IN2
13
26
channel 2 input
SGND
14
27
signal ground
IN4
15
28
channel 4 input
IN3
16
29
channel 3 input
ACGND
17
30
AC ground
OUT3+
18
2
channel 3 positive output (left front)
PGND3
19
32
channel 3 power ground
OUT3
20
1
channel 3 negative output (left front)
VP1
21
3
power supply voltage 1
OUT4+
22
6
channel 4 positive output (left rear)
SCL
23
7
I2C-bus clock input
OUT4
24
4
channel 4 negative output (left rear)
PGND4
25
5
channel 4 power ground
SDA
26
8
I2C-bus data input and output
TAB
27
36
heatsink connection; must be connected to ground
n.c.
-
12, 19, 20,
21, 22, 31,
33, 34, 35
not connected
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
7. Functional description
The TDF8544 is a complementary quad BTL audio power amplifier made with SOI-based
BCDMOS technology. It contains four independent amplifiers in a BTL configuration; see
Figure 1. The amplifier remains fully operational at a battery voltage as low as 6 V. Below
6 V, a crank detector is activated to shut down the amplifier without audible plops.
The TDF8544 is protected against overvoltage, short-circuit, overtemperature, open
ground and open VP connections.
The diagnostics for temperature and clip levels are programmable via the I2C-bus, and the
information indicated at diagnostic pins DIAG and STB is selectable. The status of each
amplifier can be read separately for output offset, load or no load, short-circuit or speaker
falsely connected.
During amplifier start-up the built-in start-up diagnostics can be used to detect shorted
load, open load, short to ground or short to VP. The TDF8544 is software and hardware
compatible with its predecessors: stand-alone amplifiers TDA8594 and TDA8595.
A resistor can be connected to pin ADSEL and ground to emulate an I2C-bus address that
is determined by the resistor value. Up to four different I2C-bus addresses are possible;
see Table 8. If pin ADSEL is shorted to ground, the TDF8544 operates in legacy mode. In
this mode, the I2C-bus is not needed and the function of pin STB changes from 2-level
(Stand-by mode and On mode) to a 3-level pin (Stand-by mode, On mode and mute).
The output stage of an amplifier channel consists of two PDMOS power transistors and
two NDMOS transistors in BTL configuration and ensures a high power output signal with
perfect sound quality. The BCDMOS process is used with an isolated SOI substrate which
ensures a robust amplifier, where latch-up cannot occur, and low crosstalk between the
channels with every component isolated, without substrate currents.
The input stage is biased (at 0.23 battery voltage + 1.4 V) and can accept an input
voltage of up to 8 V (peak). The DC input bias voltage can be measured on pin SVR. At a
bias voltage of 0.23 battery voltage + 1.4 V (= 4.7 V at a supply of 14.4 V), the input
capacitors can remain biased even with an engine start crank as low as 6 V. If the input
capacitors are allowed to discharge quickly, a small input signal is caused by a different
input time-constant due to a different AC ground and input capacitor. This small input
signal would be amplified to the output resulting in an audible plop noise.
7.1 Start-up and shut-down sequence
The capacitor on pin SVR is used for smooth start-up and shut-down which prevents the
amplifier from producing switch-on or -off plop noise. Increasing the SVR capacitor value
increases start-up and shut-down time.
If the amplifier is switched on in I2C-bus mode (IB1[D0] = 1) or in legacy mode
(VSTB > 2.5 V), the amplifier output voltage rises to 1.4 V below half the supply voltage
and the output is muted. When the output reaches 1.4 V below half the supply voltage, the
start-up mute is released if the I2C-bus was set to unmute (VSTB > 5.9 V in legacy mode),
or stays in mute if the bits are set to mute (2.5 V < VSTB < 4.5 V in legacy mode).
To enable short start-up times, the 70 k input resistor is reduced to 3 k during start-up
until just before the start-up mute release.
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
During start-up, the ampifier cannot distinguish between a short to ground or a speaker
fault. If there is a speaker fault during start-up, the amplifer enters protection mode and
switches off that channel.
If the amplifier starts and a speaker fault occurs (double-fault condition, one side of the
speaker connected to ground and one side connected to one output), the amplifier only
sets the speaker fault detection bits.
If the amplifier is switched off by I2C-bus (IB1[D0] = 0) the soft mute is activated and the
capacitor on pin SVR is discharged. If the amplifier is switched off in legacy mode, pin
STB must be set to mute for 50 ms to ensure a low switch-off plop and then pin STB can
be set to ground which discharges the SVR capacitor.
If the amplifier is switched off by pulling pin STB LOW, the amplifier is muted (fast mute)
and then the capacitor on pin SVR is discharged. This fast mute can be used in I2C-bus
and legacy mode, when for instance an external engine start detection is used.
VP
DIAG
DB2[D7]
POR
IB1[D0]
start enable
twake
STB
SVR
tamp-on
amplifier
output
td(mute-off)
Fig 4.
td(fast-mute)
toff
001aam685
Start-up and shut-down in I2C-bus mode
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
VP
DIAG
STB
POR
on
mute
standby
SVR
tamp-on
soft
mute
fast
mute
toff
amplifier
output
td(mute-off)
Fig 5.
td(soft-mute)
td(mute-on)
td(fast-mute)
001aam686
Start-up and shut-down in legacy mode
7.2 Engine start and low voltage operation
The voltage on pin SVR acts as a reference voltage for the input bias (set to 0.23 battery
voltage + 2 diode voltage Vbe) and as a reference for generating the filtered half supply
voltage at the amplifier output. The capacitor connected to pin SVR improves supply
voltage ripple rejection and channel separation between the four channels.
The DC output voltage relates to the SVR voltage to prevent common mode ripple on the
speaker lines. If the supply voltage drops during an engine start, the output follows slowly
due to the SVR capacitor. To enable sufficient headroom for the output signal below a
battery voltage of 10 V, the DC-output voltage directly follows the half supply voltage. This
ensures that at low supply voltage the undistorted output power is maximized. If the
battery voltage is above 10 V, the DC-output voltage relates to the SVR voltage and is
filtered again for supply ripple; see Figure 6.
The DC input voltage follows the supply voltage slowly, due to the SVR capacitor, to
prevent audible plops, even during engine start.
If the battery voltage drops below 6 V, the low VP mute is activated. During low VP mute,
the amplifier is fast muted (about 400 s). When mute is completed, the capacitors on pin
ACGND and pin SVR are discharged to prevent audible plops.
If the battery rises again above the low VP mute threshold (6 V), and a Power-On Reset
(POR) (DB2[D7] = 1) is not detected, the amplifier starts automatically. The amplifier
restart only occurs if the SVR capacitor has been discharged to 0.7 V to prevent a start-up
plop. If the battery voltage has dropped too much that the internal registers lose their
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
information, a POR occurs and the amplifier will not restart automatically. In I2C-bus
mode, pin DIAG is pulled LOW to indicate a POR has occurred. In legacy mode, the
amplifier restarts if pin STB remains HIGH.
The device prevents amplifier plops during engine start. To prevent plops on the amplifier
output caused by, for instance, a tuner regulator out of regulation, the voltage on pin STB
can be made zero when an engine start is detected. Pin STB activates the fast mute,
suppressing disturbances at the amplifier inputs.
The built-in low battery voltage mute is the default, and in legacy mode is set to 5.5 V, but
can also be set to 7.2 V via the I2C-bus. If the low battery voltage mute is set to 7.2 V, the
amplifier activates fast mute (400 s) and enters the same cycle when the low VP mute
was set to 5.5 V: discharge of the ACGND and SVR capacitors when the mute is
completed and start-up when the supply voltage is above 8 V, when no POR has
occurred.
SVR clamp voltage
VP
14
voltage
(V)
10
DC output voltage
7
UVP
6
3.5
SVR voltage/DC input voltage
DC voltage output
not filtered to ensure
headroom
Fig 6.
amplifier re-start
(depends on
I2C-bus content)
t(start-Vo(off))
t(start-SVRoff)
t (s)
001aam687
Engine start protection
7.3 Power-on reset and supply voltage spikes
If in I2C-bus mode the supply voltage drops below 4.5 V, the content of the I2C-bus latches
cannot be guaranteed and POR is activated at a typical VP level of 3.1 V. All latches are
reset, the amplifier is switched off and pin DIAG is pulled LOW to indicate that a POR has
occurred; see DB2[D7]. If IB1[D0] is set, the power-on flag is reset, pin DIAG is released
and the amplifier starts. In legacy mode a supply voltage drop below 6 V switches off the
amplifier. When the supply voltage is above 6 V the amplifier restarts if pin STB is still
enabled.
7.4 Protection
7.4.1 Output protection and short-circuit protection
If a short-circuit to ground, to VP or across the load occurs on one or more amplifier
outputs, only the channel with the short will be switched off. The channel that has a
short-circuit and the type of short-circuit can be read via the I2C-bus. If pin DIAG is
enabled for load fault information (IB2[D4] = 0) pin DIAG is pulled LOW. The window
protection prevents a restart of the channel with a short to ground or VP. With a short
across the load the channel is switched on again after 15 ms to check if the short across
the load is still present. If the short-circuit conditions are still present, the channel is
TDF8544
Product data sheet
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
switched off. If several channels have a short across the load at the same time, the
channels are switched on one by one to prevent high supply current switching with four
shorts across the load at the same time. The 15 ms cycle reduces power dissipation. To
prevent audible distortion, the channel with the short can be disabled via the I2C-bus.
7.4.2 Loss-of-ground/loss of VP
Loss-of-ground/loss of VP is a double fault condition: the ground (or VP) wire of the set is
not connected and the ground (or VP) wire is connected to one of the loudspeaker
outputs. In this situation the supply capacitor in the set is charged through the body diode
of the output power transistor. This body diode (between the drain and source of the
power transistor) is always present in amplifiers with MOS output stages. The capacitor
charge current depends on the series impedance of the supply lines, the output
impedance of the loss-of-ground tester and the value of the capacitor; see Figure 7. To
simulate a worst-case condition, the loss-of-ground tester is equipped with a buffer
capacitor of 116 mF to simulate a very low output impedance. With an RS of 63 m, peak
currents of more than 70 A have been measured.
(2)
3
5
7
(1)
VP
9
2200 μF
Cbuffer
116 mF
17
19
21
23
Vpulse
NMOS
80N03L
RS
Loss-of-ground tester
DUT in application
001aam695
(1) Capacitor can be 2200 F to 10000 F.
(2) Amplifier output stage.
Fig 7.
TDF8544
Product data sheet
Test circuit for loss-of-ground test
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
PMOS
IRF5305
Vpulse
(1)
3
5
7
2200 μF
9
VP
17
Cbuffer
116 mF
19
RS
21
23
Loss-of-VP tester
DUT in application
001aao146
(1) Amplifier output stage.
Fig 8.
Test circuit for loss-of-VP test
7.4.3 Speaker fault detection
There are two protection features available to prevent damage to the speaker if one side
of the speaker is connected to ground.
• A check for a speaker fault operates during start-up. This is included in the check for a
short to ground; the channel that has the speaker fault is switched off. If the short to
ground bit is set, it can mean either a short to ground or a speaker fault. At start-up it
is difficult to distinguish between a speaker fault and a short to ground. The amplifier
is protected against both, but the speaker fault bit is not always set.
• A check for a speaker fault operates continuously. If a speaker fault is detected, bit D6
in registers DB1 to DB4 are set but the amplifier is not switched off and pin DIAG is
not pulled LOW.
7.4.4 Overvoltage warning and load dump protection
If the battery voltage VP exceeds the maximum value of Vth(ovp), the device switches off
the output stages of the amplifier to protect the output transistors. The overvoltage
pre-warning bit is set when the supply voltage level exceeds the value of VP(ovp)pwarn.
The functionality of the diagnostic output can be chosen in I2C-bus mode. In this mode the
pre-warning information can become visible at the diagnostic output. In legacy mode, pin
DIAG will not be activated under pre-warning conditions.
Although the amplifier switches off the output stages, the device remains operational
during load dump conditions (maximum value of VP at load dump protection; duration
50 ms, rise time > 2.5 ms). The occurrence of the load dump situation can last for a longer
period of time without damaging the device. Provided that the I2C-bus supply is within the
levels specified, communication with the I2C-bus bus during load dump situations remains
possible and the status of the channel outputs can be read.
TDF8544
Product data sheet
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
7.4.5 Thermal pre-warning and thermal protection
If the average junction temperature reaches one of the adjustable levels set via the
I2C-bus, selected with IB3[D4], pre-warning is activated resulting in pin DIAG LOW (if
selected) and can be read via the I2C-bus. The default setting for the thermal pre-warning
is IB3[D4] = 0 setting the warning level at Tj(AV)(pwarn) = 160 C. In legacy mode the
thermal pre-warning is also set at Tj(AV)(pwarn) = 160 C.
If the temperature increases further, the temperature-controlled gain reduction is activated
for all four channels to reduce the output power; see Figure 9. If this does not reduce the
average junction temperature, all four channels are switched off at the absolute maximum
temperature Toff.
001aam696
30
G
(dB)
20
10
0
140
150
160
170
180
190
Tj (°C)
Fig 9.
Temperature controlled amplifier gain
7.5 Diagnostics
Diagnostic information can be read via the I2C-bus, but can also be made available at pin
DIAG or pin STB. Pin DIAG indicates information such as POR occurred, low battery, and
high battery; the output load fault information is selectable via the I2C-bus. This
information is seen at pin DIAG as a logical OR. In case of a failure, pin DIAG remains
LOW and the microcontroller can read the failure information via the I2C-bus; pin DIAG
can be used as a microcontroller interrupt to minimize I2C-bus traffic. When the failure is
removed, pin DIAG is released.
To enable full control over the clipping information, pin STB can be programmed as a
second-clip detection pin. The clip detection level can be selected for all channels at once.
The clip information can be selected to be available separately at pin DIAG or at pin STB
for each channel. It is possible, for example,to distinguish between clipping of the front
and the rear channels.
The diagnostic information available at either of the two diagnostic pins DIAG and STB is
shown in Table 4.
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 4.
Diagnostic information on pins DIAG and STB
Diagnostic
information
I2C-bus mode
Power-On Reset
(POR)
after POR, pin DIAG
no
remains LOW until
amplifier starts (inverse
of start-up bit)
no
Low battery
yes
no
yes
Clip detection
can be enabled per
channel; can be
enabled by IB1[D7] if
below VP = 10 V;
default is ‘blocked’
can be enabled per
channel; can be
enabled by IB1[D7] if
below VP = 10 V;
default is ‘blocked’
yes; fixed level for all
channels at 2 %;
blocked for VP < 10 V
Temperature prewarning
can be enabled;
default: Tj(AV)(pwarn) =
160 C
no
yes, pre-warning level
is Tj(AV)(pwarn) =
160 C
Short
can be enabled; default no
is enabled
DIAG pin
Speaker fault detection no
Legacy mode
STB pin
no
DIAG pin
yes
no
Offset detection
no
no
no
Load detection
no
no
no
no
yes
Overvoltage protection yes
(20 V)
Overvoltage
pre-warning (16 V)
can be enabled; default no
is disabled
no
Maximum temperature yes
protection (active)
no
yes
Start-up diagnostics
indication
no
no
no
7.5.1 Start-up diagnostics with DC load detection
If the start-up diagnostics are enabled, the load condition of all four channels is
determined. At the end of the start-up diagnostics cycle, not only the load condition is
known (shorted load, normal load or open load), but also if a separate amplifier is
connected or if the outputs are shorted to battery or ground. If a separate amplifier
(booster) is detected, the amplifier can start-up in line driver mode (low gain setting).
The load diagnostic is insensitive to door-slam (slowly moving speaker due to slamming of
the car door) and to external interference such as crosstalk of relays switching in the
wiring harness; see Figure 10.
TDF8544
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
COMPARATORS
OFFSET
GENERATOR
out +
SPIKE
FILTER
out −
DOOR-SLAM
PROCESSOR
I2C-BUS BITS
LOAD CONDITION
001aam697
Fig 10. Principle of start-up diagnostics
The load detection values are shown in Figure 11.
SHORTED
NORMAL
LINE DRIVER
OPEN
high gain
0.5 Ω
1.5 Ω
20 Ω
80 Ω
200 Ω
400 Ω
low gain
1.5 Ω
3.2 Ω
20 Ω
80 Ω
200 Ω
400 Ω
001aaam698
Fig 11. Start-up diagnostics load detection levels
If only 4 speakers are connected, the low gain mode can be selected during the start-up
diagnostics. A shorted load is indicated until an impedance of 1.5 is reached. Even ‘soft’
shorts in the wiring harness will be detected.
IB1[D1]
turn on diagnostic
enable
STB
td(sudiag-on)
amplifier
output
(1)
tsudiag
(2)
tamp_on
001aam699
(1) First stage: open load/load/line driver load; short across the load.
(2) Second stage: amplifier start plus short to ground/VP; speaker fault.
Fig 12. Start-up with start-up diagnostics
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I2C-bus controlled 4 50 W power amplifier
In the first stage an offset is generated across the load. To avoid switch-on plop-noise the
offset is increased after 15 ms. The measurement cycle lasts for tsudiag. After 15 ms the
offset across the load is reduced. The offset is generated with resistors instead of the
amplifier to avoid plop-noise during engine start. If the offset is removed quickly, audible
plop can occur during periods without audio.
If the voltage of the outputs is more than 3.5 V during the first stage, the start-up
diagnostic is switched off to avoid damage to the amplifier. This can happen with a door
slam or with a short to VP. If a short to VP is applied, the shorted channel will report not
valid after the first stage. If only 1 or 2 channels report not valid after the first stage, a short
to VP of those channels can be assumed. If all 4 channels report not valid, under- over voltage, a start-up diagnostic cycle can be assumed.
The start-up diagnostics has a built-in spike filter to remove disturbances caused by
switching relays in the wiring harness or EMC. The door-slam processor filters out
disturbances caused when the car door closes: car door-slam can cause the speakers to
move slowly which disturbs the measurement. With these filter techniques, reliable load
detection is performed in a single start-up diagnostics cycle.
The start-up diagnostics can be repeated. Only the first stage, where the speaker load is
determined, is sensitive to disturbance and needs to be repeated. When the start-up
diagnostics start, the not valid bit is set, and “the start-up diag busy bit” (TDF8544 bit
DB5[D5]) indicates that the start-up diagnostics are not completed. When the start-up is
completed, or interrupted by a POR, the “start-up diag busy bit” is reset.
There are two possible situations:
• the start-up diagnostics are enabled (IB1[D1] = 1) and the amplifier start is not
enabled (IB1[D0] = 0), bit “start-up diag busy bit” is reset when the start-up
diagnostics are completed, and the I2C-bus data bits are set. Toggling the start-up
diagnostics bit re-starts the start-up diagnostic. The invalid bits are set and bit
“start-up diag busy bit” indicates that the start-up diagnostics are not completed.
• the start-up diagnostics are enabled (IB1[D1] = 1) and the amplifier start is enabled
(IB1[D0] = 1). After the first start-up diagnostic cycle has finished, the amplifier starts
and when start-up is completed, just before the start-up mute release (DC output
voltage is 1.4 V below midtap voltage), bit “start-up diag busy bit” indicates that the
startup diagnostic is completed. It is not necessary to toggle the start-up diagnostics
and has no purpose.
The first and second stages of the start-up diagnostics can be repeated:
Start-up with the start-up diagnostics (IB1[D1] = 1 and the amplifier start enabled
(IB1[D0] = 1). Wait until DB5[D5] = 0 which indicates that the start-up diagnostics cycle is
completed. Read the start-up diagnostics information. Shut down the amplifier by making
the start-up bit logic 0. When DB5[D0] = 0, the amplifier is completely shut down and a
new start-up cycle can be programmed.
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
Table 5.
Start-up diagnostics I2C-bus bits
DC load bits[1]
Meaning
DBx[D5]
DBx[D4]
0
0
normal load
0
1
line driver mode
1
0
open load
1
1
invalid: overvoltage or
undervoltage (VP < 10 V) has
occurred, or start-up
diagnostics not completed, or
channel has short to VP;
indicated in second stage
[1]
DBx[D3] indicates a shorted load; DBx[D1] indicates a short to VP; DBx[D0] indicates a short to ground.
When set, D4, D5 have no meaning.
If during the start-up diagnostics an engine start occurs, the generated offset to measure
the DC load is reduced and the start-up diagnostics cannot be performed correctly. In this
case the invalid combination DBx[D4:D5] = 11 is set.
The start-up diagnostics information in the I2C-bus bits is combined with the AC load
detection allowing the start-up diagnostics information to be read when IB4[D4] = 0. If
IB4[D4] = 1, the stored start-up diagnostics information bits cannot be read but they will
not lose their value.
Remark: the shorted load, and short to VP or ground information from the start-up
diagnostics is cleared after an I2C-bus read. This indicates the real situation: when the
short is removed, the bits are cleared. The DBx[D5] and DBx[D4] information, generated
at start-up, is refreshed after a new start-up diagnostics cycle.
7.5.2 DC offset detection
The offset detection can be performed with no input signal (for instance when the DSP is
muted after a start-up) or with an input signal. If in I2C-bus mode an I2C-bus read of the
output offset is performed, the I2C-bus DBx[D2] latches are set. If the amplifier BTL output
voltage is within a window with a threshold of 1.3 V (typical), the DBx[D2] latches are reset
and their setting is disabled. If for example, after 1 s another I2C-bus read is performed
and the offset bits are still set, the output did not cross the offset threshold during the last
1 second; see Figure 13. This can mean either a frequency below 1 Hz was applied (1 s
I2C-bus read interval) or an output offset of more than 1.3 V is present.
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
Vo = (OUT+ - OUT-)
offset
threshold
time
reset, setting
disabled
1 second:
read → no offset,
DBx[D2] reset
Vo = (OUT+ - OUT-)
offset
threshold
time
read →
set bit
1 second:
read → offset,
DBx[D2] set
001aam700
Fig 13. Offset detection
7.5.3 AC load detection
The AC load detection, set with IB1[D2] = 1, is used to detect if AC-coupled speakers
such as tweeters are connected correctly. The detection requires a 19 kHz sine wave to
be applied to the inputs of the amplifier. A high current AC-load detection mode can be
selected, for example during car assembly, or a low current AC-load detection mode, for
example during switch on of car radio. The output voltage over the load impedance
generates an amplifier current. If the amplifier peak current triggers 4 times a 580 mA
(peak) threshold (or 320 mA (peak) in low current mode), the AC-load detection bit is set.
The 4 ‘threshold cross’ counter is used to prevent false AC-load detection caused by
switching the input signal on or off.
An AC-coupled speaker reduces the impedance at the output of the amplifier in a certain
frequency band. The presence of an AC-coupled speaker can be determined using a high
current mode (IB4[D1] = 1, see Figure 14) or using a low current detection mode
(IB4[D1] = 0; see Figure 14.
If, for instance, a 19 kHz input signal is generated with a peak output voltage of 2 V the
I2C-bus bits are guaranteed to be set with a total AC + DC load less than 4 and are
guaranteed not set with a load of more than 9 ; see Figure 14.
The interpretation of the line driver and amplifier mode DC load bit for AC load detection is
shown in Table 6.
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I2C-bus controlled 4 50 W power amplifier
Table 6.
AC load detection
IB4[D4] = 1
DB1 to 4 [D4] (AC load bit)
No AC load detected
0
AC load detected
1
If IB1[D2] = 1 the AC-load detection measurement cycle is enabled, the peak counter is
reset and the measuring cycle starts. The AC-load detection is only performed after the
amplifier has completed its start-up cycle. Since the AC-load information in the I2C-bus
bits is combined with the start-up diagnostics, the AC-load information can be read when
IB4[D4] = 1. If IB4[D4] = 0, the stored AC-load bits cannot be read, but their values are
preserved.
001aam701
25
ZL
(Ω)
20
no load detected,
l2C-bus bits not set
15
trip level
10
load detected,
l2C-bus bits set
5
0
0
2
4
6
VoM (V)
Fig 14. AC load impedance as a function of peak output voltage (high current AC-load
detection)
001aam702
50
ZL
(W)
40
no load detected,
l2C-bus bits not set
30
trip level
20
load detected,
l2C-bus bits set
10
0
0
2
4
6
VoM (V)
Fig 15. AC load impedance as a function of peak output voltage (low current AC-load
detection)
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
7.5.4 Distortion clip detection
If the amplifier output starts clipping at the supply voltage or ground, the output signal
becomes distorted. If the distortion per channel exceeds a selectable threshold (2 %, 5 %
or 10 %), either pin DIAG or pin STB is activated. To be able to detect if, for instance, the
front channels (channels 1 and 3) or rear channels (channels 2 and 4) are clipping, the
clip information per channel can be directed to either pin DIAG or pin STB.
It is possible to only have the clip information on the diagnostic pins by disabling the
temperature- and load information on pin DIAG. The temperature and load protection are
still functional but can only be read via the I2C-bus.
The clip detection level can be programmed via the I2C-bus. The clip information is
blocked below a supply voltage of 10 V to avoid false clip detection during engine start, or
can be programmed to operate at the low voltage detection level of 7.5 V or 6 V.
Since it is possible to have different amplifier gain settings between the front and rear
channels and there is only one clip reference current, the clip detect levels are only
accurate for the channels with the highest gain. In line driver mode the DC-output voltage
is 0.23VP and clip detection will still indicate a clip, but the levels will not be accurate.
7.6 Line driver mode and low gain mode
The TDF8544 can be used as a line driver or as a low gain amplifier. In both situations, the
gain needs to be set to 16 dB via the I2C-bus (IB3[D5:D6] and can be independently set
for the front (channels 1 and 3) and rear (channels 2 and 4). The main difference between
line driver mode and low gain mode is the DC output voltage.
In line driver mode the TDF8544 is used to drive a separate amplifier or booster. In this
mode the DC output voltage is set to 0.23 battery voltage and is filtered with the
capacitor connected to pin SVR (same as VSVR). The reason not to set the DC output
voltage to half the battery voltage is to allow engine starts at a battery voltage as low as
6 V. The DC output voltage remains approximately 3 V during engine start. If the DC
output voltage is set to half the battery voltage, with an engine start the common mode
voltage will change quickly from 7 V to 3 V. This drives the input stage of the booster
below the ground level.
If the TDF8544 is used as a low gain amplifier in a booster, the DC output voltage is set to
half of the supply voltage to ensure maximum undistorted output power.
The line driver and low gain modes can be selected with I2C-bus bit IB4[D2].
Table 7.
Channels 1 and 3
gain setting (dB)
Channels 2 and 4
gain setting (dB)
Line driver/low gain
mode IB4[D2][1]
All channels DC
output voltage (V)
26
26
X
0.5VP
16
26
X
0.5VP
26
16
X
0.5VP
16
16
low gain mode
0.5VP
16
16
line driver mode
0.23VP
[1]
TDF8544
Product data sheet
DC output voltage as a function of different gain settings
X = neither mode selected.
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I2C-bus controlled 4 50 W power amplifier
7.7 I2C-bus, legacy mode and address select pin
Pin ADSEL can select either of two amplifier modes: legacy mode or I2C-bus mode.
7.7.1 Address select (pin ADSEL)
The following amplifier functions are selected with pin ADSEL:
• Pin ADSEL shorted: (RADSEL < 470 ) legacy mode, no I2C-bus communication is
needed.
• Resistor connected between pin ADSEL and ground: where different I2C-bus
addresses can be selected with resistors.
• One I2C-bus address can be selected by either forcing a voltage on pin ADSEL or by
connecting a high ohmic resistor between pin ADSEL and VP.
To avoid address changes during low supply voltage, the address selected by the value of
resistor connected to pin ADSEL is latched at voltages below 6 V. The consequence is,
during start-up and after every power-on reset, the supply voltage must be above 6 V
otherwise the address is invalid.
7.7.2 Legacy mode (RADSEL < 470 )
The function of pin STB changes from off/operating to off/mute/operating and the amplifier
starts immediately when pin STB is put into mute or operating mode. Mute operating is
controlled via an internal timer (15 ms) to minimise mute-on plops. When pin STB is
switched directly from operating to off, first the hard mute is activated (switching to mute
within 400 s) and then the amplifier shuts down. To have a plop-free shut-down, first pin
STB should be switched to mute for 50 ms and then switched off.
7.7.3 I2C-bus mode
If pin STB is LOW, the total quiescent current is low, and the I2C-bus lines are not loaded.
When pin STB is switched HIGH, the TDF8544 enters operating mode and performs a
POR which makes pin DIAG LOW. The TDF8544 starts when IB1[D0] = 1. Bit D0 also
resets the ‘power on reset occurred’ bit (DB2[D7]) and releases pin DIAG.
Soft mute and hard mute can be activated via the I2C-bus. Soft mute can be activated
independently for the front (channels 1 and 3) and rear (channels 2 and 4), and mutes the
audio in 15 ms. Hard mute activates the mute for all channels at the same time and mutes
the audio in 400 s. Unmuting after a hard mute will be a soft unmute of approximately
15 ms. When pin STB is switched to Off mode, and the amplifier has started, first the hard
mute is activated and then the amplifier shuts down. It is possible to fully mute the
amplifiers within 400 s by making pin STB LOW, for example during an engine start.
7.7.4 I2C-bus diagnostic bits read-out/cleared after read
The amplifier’s diagnostic information can be read via the I2C-bus. The I2C-bus bits are
set if a failure occurs and are reset by the I2C-bus read command (cleared after read).
When the failure is removed, the microcontroller knows the cause of the failure by reading
the I2C-bus. The consequence of this procedure is that old information is read during the
I2C-bus read. Most real information will be gathered within two consecutive read
commands.
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
Cleared after read means that the I2C-bus bits are cleared after a read command. The
Clear command is done only if all five data bytes are read. If only four data bytes are read,
the I2C-bus latches are not cleared and the old value remains in the latches.
When selected, pin DIAG gives actual diagnostic information. If a failure is removed,
pin DIAG is released instantly, independently of the I2C-bus latches.
7.8 Amplifier in combination with a DC-to-DC converter
The TDF8544 can be used in combination with a DC-DC up-converter as the supply for
the amplifier (connected to VP). If the DC-DC converter output voltage is controlled with
the audio signal, the amplifier’s dissipation can be reduced at lower output powers. To
ensure that the amplifier can follow supply voltage variations, the supply voltage ripple
capacitor connected to pin SVR, to filter the amplifier’s common mode output voltage,
must be disconnected internally. The SVR capacitor is still used to determine the DC input
voltage. If I2C-bus bit IB4[D7] = 1, the common mode output voltage directly follows the
supply voltage variations.
8. I2C-bus specification
Table 8.
TDF8544 hardware address select
Pin ADSEL
A6
A5
A4
A3
A2
A1
A0
R/W
Hex
Remark
Open
1
1
0
1
1
0
0
0 = write to TDF8544;
1 = read from TDF8544
D8
reserved;
instruction and
data bytes
have other
meaning
100 k 1 %
1
0
DC
-
30 k 1 %
1
1
DE
-
10 k 1 %
0
1
0
D4
-
Voltage > 4 V
1
0
1
DA
-
Ground
no
I2C-bus;
legacy mode
-
SDA
SCL
S
START condition
P
SDA changes when SCL is HIGH:
start − or stop condition
STOP condition
001aam703
Fig 16. Definition of START and STOP conditions
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I2C-bus controlled 4 50 W power amplifier
SDA
SCL
change
of data
allowed
data line
stable;
data valid
001aam704
Fig 17. Bit transfer
I2C-bus WRITE
SCL
1
MSB
SDA
2
MSB − 1
S
7
8
LSB + 1
ADDRESS
9
ACK
1
MSB
2
MSB − 1
A
W
7
LSB + 1
8
LSB
WRITE DATA
9
ACK
A
P
to stop the transfer, after the last acknowledge (A)
a stop condition (P) must be generated
I2C-bus READ
SCL
1
MSB
SDA
2
MSB − 1
S
7
8
LSB + 1
ACK
R
ADDRESS
9
1
MSB
2
7
MSB − 1
A
LSB + 1
READ DATA
8
LSB
9
ACK
A
P
to stop the transfer, the last byte must not be acknowledged
and a stop condition (P) must be generated
: generated by master (microcontroller)
: generated by slave
S
: start
P
: stop
A
: acknowledge
R/W
001aam705
: read / write
Fig 18. I2C-bus read and write modes
8.1 I2C-bus instruction bytes
I2C-bus mode:
• If R/W bit = 0, the TDF8544 expects four instruction bytes; IB1, IB2, IB3, IB4
• After a power-on reset, all instruction bits are set to zero
Legacy mode:
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I2C-bus controlled 4 50 W power amplifier
• All bits equal to zero define the setting, with the exception of bit IB1[D0] which is
ignored; see Table 9.
Table 9.
Instruction byte IB1
Bit
Description
D7
enable or disable clip detection below VP = 10 V
0 = disable clip detection below VP = 10 V
1 = enable clip detection below VP = 10 V
D6
channel 3 clip information on pin DIAG or pin STB
0 = clip information on pin DIAG
1 = clip information on pin STB
D5
channel 1 clip information on pin DIAG or pin STB
0 = clip information on pin DIAG
1 = clip information on pin STB
D4
channel 4 clip information on pin DIAG or pin STB
0 = clip information on pin DIAG
1 = clip information on pin STB
D3
channel 2 clip information on pin DIAG or pin STB
0 = clip information on pin DIAG
1 = clip information on pin STB
D2
enable or disable AC load detection
0 = AC load detection disabled
1 = AC load detection enabled
D1
enable or disable start-up diagnostics
0 = start-up diagnostics disabled
1 = start-up diagnostics enabled
D0
enable or disable amplifier start
0 = amplifier start not enabled
1 = amplifier start enabled
Table 10.
Instruction byte IB2
Bit
Description
D7 and D6
clip detection level
00 = clip detection level 2 %
01 = clip detection level 5 %
10 = clip detection level 10 %
11 = clip detection level disabled
D5
temperature information on pin DIAG
0 = temperature information on pin DIAG
1 = no temperature information on pin DIAG
D4
load fault information (shorts) on pin DIAG
0 = load fault information on pin DIAG
1 = no load fault information on pin DIAG
D3
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
Table 10.
Instruction byte IB2 …continued
Bit
Description
D2
soft mute channel 1 and channel 3
0 = soft mute disabled
1 = soft mute enabled (mute delay 15 ms)
D1
soft mute channel 2 and channel 4
0 = soft mute disabled
1 = soft mute enabled (mute delay 15 ms)
D0
fast mute all amplifier channels
0 = fast mute disabled
1 = fast mute enabled
Table 11.
Instruction byte IB3
Bit
Description
D7
-
D6
amplifier channel 1 and channel 3 gain select
0 = 26 dB
1 = 16 dB
D5
amplifier channel 2 and channel 4 gain select
0 = 26 dB
1 = 16 dB
D4
temperature pre-warning level
0 = warning level at Tj(AV)(pwarn) = 160 C
1 = warning level at Tj(AV)(pwarn) = 135 C
D3
enable or disable channel 3
0 = channel 3 enabled
1 = channel 3 disabled
D2
enable or disable channel 1
0 = channel 1 enabled
1 = channel 1 disabled
D1
enable or disable channel 4
0 = channel 4 enabled
1 = channel 4 disabled
D0
enable or disable channel 2
0 = channel 2 enabled
1 = channel 2 disabled
Table 12.
Instruction byte IB4
Bit
Description
D7
common-mode voltage filtered by SVR capacitor
0 = filter common-mode voltage
1 = DC-to-DC converter connected (SVR capacitor not used to filter common-mode
voltage)
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
Table 12.
Instruction byte IB4 …continued
Bit
Description
D6
soft or fast mute select during shut-down via pin STB
0 = activate fast mute during shut-down
1 = activate slow mute during shut-down
D5
16 V overvoltage warning on pin DIAG
0 = 16 V overvoltage warning on pin DIAG disabled
1 = 16 V overvoltage warning on pin DIAG enabled
D4
AC or DC load information on bits DBx[D5:D4]
0 = DC load information on bits DBx[D5:D4]
1 = AC load information on bits DBx[D5:D4]
D3
-
D2
line driver mode or low gain mode selection
0 = line driver mode; common-mode output voltage is 0.23 VP
1 = low gain mode; common-mode output voltage is 0.5 VP; only valid for channels
when gain is set to 16 dB
D1
AC load detection measurement current selection
0 = AC load detection; low measurement current
1 = AC load detection; high measurement current
D0
low VP mute undervoltage level setting
0 = low VP mute undervoltage level set to 5.9 V
1 = low VP mute undervoltage level set to 7.5 V
TDF8544
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TDF8544
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I2C-bus controlled 4 50 W power amplifier
8.2 I2C-bus data bytes
I2C-bus mode:
• If R/W = 1, the TDF8544 sends data bytes to the microprocessor
• All bits are reset after a read operation except DBx[D4] and DBx[D5] in DB1 to DB4.
Bit DBx[D2] in DB1 to DB4 is set after a read operation; see Section 7.5.1 and
Section 7.5.2.
• For explanation of AC and DC load detection bits, see Section 7.5.3
Table 13.
Data byte DB1
Bit
Description
D7
temperature pre-warning
0 = no temperature pre-warning
1 = temperature pre-warning has occurred
D6
speaker fault channel 2
0 = no speaker fault, channel 2
1 = speaker fault, channel 2
D5 and D4
channel 2 DC-load or AC-load detection
if bit IB4[D4] = 1, AC-load detection is enabled, bit D5 does not care, bit D4 has
the following meaning:
0 = no AC-load
1 = AC-load detected
if bit IB4[D4] = 0, AC-load detection is disabled, bits D5 and D4 are available
for DC-load detection
00 = normal load
01 = line driver load
10 = open load
11 = not valid
D3
channel 2 shorted load
0 = no shorted load
1 = shorted load
D2
channel 2 output offset
0 = no output offset
1 = output offset
D1
channel 2 short to VP
0 = no short to VP
1 = short to VP
D0
channel 2 short to ground
0 = no short to ground
1 = short to ground
Remark: Data bits are only reset (cleared after read) after reading 5 data bytes.
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 14.
Data byte DB2
Bit
Description
D7
POR and amplifier status
0 = POR disabled; amplifier enabled
1 = POR has occurred; amplifier disabled
D6
speaker fault channel 4
0 = no speaker fault
1 = speaker fault, channel 4
D5 and D4
channel 4 DC-load or AC-load detection
if bit IB4[D4] = 1, AC-load detection is enabled, bit D5 does not care, bit D4 has
the following meaning:
0 = no AC-load
1 = AC-load detected
if bit IB4[D4] = 0, AC-load detection is disabled, bits D5 and D4 are available for
DC-load detection
00 = normal load
01 = line driver load
10 = open load
11 = not valid
D3
channel 4 shorted load
0 = no shorted load
1 = shorted load
D2
channel 4 output offset
0 = no output offset
1 = output offset
D1
channel 4 short to VP
0 = no short to VP
1 = short to VP
D0
channel 4 short to ground
0 = no short to ground
1 = short to ground
Remark: Data bits are only reset (cleared after read) after reading 5 data bytes.
Table 15.
Data byte DB3
Bit
Description
D7
maximum temperature protection
0 = no protection
1 = maximum temperature protection
D6
speaker fault channel 1
0 = no speaker fault, channel 1
1 = speaker fault, channel 1
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 15.
Data byte DB3 …continued
Bit
Description
D5 and D4
channel 1 DC-load or AC-load detection
if bit IB4[D4] = 1, AC-load detection is enabled, bit D5 does not care, bit
D4 has the following meaning:
0 = no AC-load
1 = AC-load detected
if bit IB4[D4] = 0, AC-load detection is disabled, bits D5 and D4 are
available for DC-load detection:
00 = normal load
01 = line driver load
10 = open load
11 = not valid
D3
channel 1 shorted load
0 = no shorted load
1 = shorted load
D2
channel 1 output offset
0 = no output offset
1 = output offset
D1
channel 1 short to VP
0 = no short to VP
1 = short to VP
D0
channel 1 short to ground
0 = no short to ground
1 = short to ground
Remark: Data bits are only reset (cleared after read) after reading 5 data bytes.
Table 16.
Data byte DB4
Bit
Description
D7
power supply 16 V overvoltage warning
0 = no overvoltage warning
1 = overvoltage warning occurred
D6
speaker fault channel 3
0 = no speaker fault
1 = speaker fault
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 16.
Data byte DB4 …continued
Bit
Description
D5 and D4
channel 3 DC-load or AC-load detection
if bit IB4[D4] = 1, AC-load detection is enabled, bit D5 does not care, bit D4 has
the following meaning:
0 = no AC-load
1 = AC-load detected
if bit IB4[D4] = 0, AC-load detection is disabled, bits D5 and D4 are available for
DC-load detection:
00 = normal load
01 = line driver load
10 = open load
11 = not valid
D3
channel 3 shorted load
0 = no shorted load
1 = shorted load
D2
channel 3 output offset
0 = no output offset
1 = output offset
D1
channel 3 short to VP
0 = no short to VP
1 = short to VP
D0
channel 3 short to ground
0 = no short to ground
1 = short to ground
Remark: Data bits are only reset (cleared after read) after reading all 5 data bytes.
Table 17.
Data byte DB5
Bit
Description
D7
power supply undervoltage
0 = no undervoltage
1 = undervoltage occurred
D6
power supply overvoltage
0 = no overvoltage
1 = overvoltage has occurred
D5
system status with start-up diagnostics or amplifier start-up[1]
0 = system not busy
1 = system busy
D4
VP below/above 7.5 V
0 = VP above 7.5 V
1 = VP has dropped below 7.5 V
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 17.
Data byte DB5 …continued
Bit
Description
D3
VP below above 10 V
0 = VP above 10 V
1 = VP has dropped below 10 V
D2
undervoltage protection
0 = no undervoltage protection occurred
1 = undervoltage protection occurred (engine start)
D1
-
D0
amplifier and output stage status[1]
0 = amplifier switched off, output stage high impedance
1 = amplifier switched on, output stage active
[1]
Bits DB5[D0] and [D5] are not latched/cleared after being read. They indicate the actual value.
Remark: Data bits are only reset (cleared after read) after reading all 5 data bytes.
9. Limiting values
Table 18. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
TDF8544
Product data sheet
Symbol
Parameter
Conditions
Min
Max
Unit
VP
supply voltage
operating
6
18
V
non-operating
1
+50
V
load dump protection;
duration 50 ms, rise
time > 2.5 ms
-
50
V
10 minutes maximum
VP(r)
reverse supply voltage
-
2
V
IOSM
non-repetitive peak
output current
-
13
A
IORM
repetitive peak output
current
-
8
A
Tj(max)
maximum junction
temperature
-
150
C
Tstg
storage temperature
55
+150
C
Tamb
ambient temperature
heatsink of sufficient size
to ensure Tj does not
exceed 150 C
40
+105
C
V(prot)
protection voltage
AC and DC short-circuit
voltage of output pins and
across the load
-
VP
V
Vi(max)
maximum input voltage
RMS value; before
capacitor; RS = 100
-
5
V
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 18. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Vx
voltage on pin x
Conditions
Min
Max
Unit
SCL and SDA
0
6.5
V
SVR, ACGND and
DIAG
0
10
V
0
24
V
-
80
W
-
2000
V
corner pins
-
750
V
non-corner pins; except
pin 24 (SVR) version
TH only
-
500
V
pin 24 (SVR) version
TH only
-
400
V
[1]
STB
total power dissipation
Ptot
VESD
electrostatic discharge
voltage
Tcase = 70 C
HBM; C = 100 pF;
Rs = 1.5 k
[2]
CDM
[3]
[1]
10 k series resistance if connected to VP.
[2]
Human Body Model (HBM): all pins have passed all tests to 2500 V to guarantee 2000 V, according to
class II.
[3]
Charged-Device Model (CDM).
10. Thermal characteristics
Table 19.
Symbol
Thermal characteristics
Parameter
Conditions
Typ
Unit
DBS27/RDBS27
Rth(j-c)
thermal resistance from junction to case
1.15
K/W
Rth(j-a)
thermal resistance from junction to ambient
40
K/W
Rth(j-c)
thermal resistance from junction to case
1.15
K/W
Rth(j-a)
thermal resistance from junction to ambient
35
K/W
HSOP36
11. Characteristics
Table 20. Characteristics
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RL = 4
6
14.4
18
V
RL = 2
6
14.4
16
V
no load
-
260
350
mA
no load; VP = 7 V
-
190
-
mA
Supply voltage behavior
VP(oper)
Iq
operating supply voltage
quiescent current
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 20. Characteristics …continued
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ioff
off-state current
VSTB = 0.4 V
-
4
10
A
VO
output voltage
DC; amplifier on; high gain/low
gain mode
6.6
7.1
7.6
V
line driver mode; IB4[D2] = 0;
IB3[D5] = [D6] = 1
3.0
3.4
3.8
V
IB4[D0] = 1
7.0
7.7
8.1
V
IB4[D0] = 0
5.4
5.7
6.2
V
IB4[D0] = 1
6.5
7.2
7.7
V
IB4[D0] = 0
5.2
5.5
5.9
V
VP(low)(mute)
low supply voltage mute
rising supply voltage
falling supply voltage
VP(low)(mute)
VP(ovp)pwarn
low supply voltage mute
hysteresis
IB4[D0] = 1
0.1
0.5
0.8
V
IB4[D0] = 0
0.1
0.3
0.7
V
pre-warning overvoltage
protection supply voltage
rising supply voltage
15.2
16
16.9
V
falling supply voltage
14.4
15.2
16.2
V
hysteresis
-
0.8
-
V
Vth(ovp)
overvoltage protection
threshold voltage
rising supply voltage
18
20
22
V
VPOR
power-on reset voltage
falling supply voltage
-
3.1
4.5
V
VO(offset)
output offset voltage
amplifier on
75
0
+75
mV
amplifier mute
25
0
+25
mV
line driver mode
45
0
+45
mV
-
-
0.8
V
-
-
0.8
V
2.5
-
4.5
V
2.5
-
VP
V
5.9
-
VP
V
5.6
5.9
6.5
V
6.1
-
7.4
V
-
5
30
A
Mode select and second clip detection: pin STB
VSTB
voltage on pin STB
off mode selected
I2C-bus mode
legacy mode
off)
(I2C-bus
mode
mute selected
legacy mode (I2C-bus mode
off)
operating mode selected
I2C-bus mode
legacy mode
off)
(I2C-bus
mode
low voltage on pin STB when
pulled LOW during clipping
[1]
ISTB = 150 A
ISTB = 500 A
ISTB
current on pin STB
TDF8544
Product data sheet
0 V < VSTB < 8.5 V; clip detection
not active
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 20. Characteristics …continued
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
time after wake-up via pin STB
before first I2C-bus transmission
is recognized; see Figure 4
-
300
500
s
-
-
5
A
I2C-bus mode;
with ILO = 5 A +15 ms;
no DC-load (IB1[D1] = 0); see
Figure 4
-
430
650
ms
legacy mode;
with ILO = 5 A +20 ms;
VSTB = 7 V; RADSEL = 0 ;
see Figure 5
-
430
650
ms
I2C-bus mode;
with ILO = 5 A +30 ms;
no DC-load (IB1[D1] = 0); see
Figure 4
-
550
800
ms
legacy mode;
with ILO = 5 A +20 ms;
VSTB = 7 V; RADSEL = 0 ;
see Figure 5
-
550
800
ms
I2C-bus mode;
with ILO = 5 A +0 ms;
see Figure 4
250
500
750
ms
via pin STB; (IB4[D6] = 0);
with ILO = 5 A +0 ms;
see Figure 5
250
500
750
ms
Start-up/shut-down/mute timing
twake
wake-up time
ILO(SVR)
output leakage current on
pin SVR
td(mute_off)
mute off delay time
tamp_on
toff
amplifier on time
amplifier switch-off time
time from amplifier start to 10 %
of output signal; ILO = 0 A
time from amplifier start to
amplifier on; 90 % of output
signal; ILO = 0 A
time to DC output voltage < 0.1 V;
ILO = 0 A
[2]
[2]
[2]
td(mute-on)
delay time from mute to on from 10 % to 90 % of output
signal; Vi = 50 mV; I2C-bus mode
(IB2[D1] = 1 to 0, or legacy mode
(VSTB = 2 V to 7 V); see Figure 5
5
15
40
ms
td(soft_mute)
soft mute delay time
from 90 % to 10 % of output
signal; Vi = 50 mV; I2C-bus mode
(IB2[D1] = 0 to 1) or legacy mode
(VSTB = 7 V to 2 V); see Figure 5
5
15
40
ms
td(fast_mute)
fast mute delay time
from 90 % to 10 % of output
signal; Vi = 50 mV; I2C-bus mode
(IB2[D0] = 0 to 1, or VSTB from
> 5.9 V to < 0.8 V in 1 s; see
Figure 5
-
0.4
1
ms
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 20. Characteristics …continued
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t(start-Vo(off))
engine start to output off
time
VP from 14.4 V to 5 V in 1.5 ms;
Vo < 0.5 V; see Figure 6
-
0.1
1
ms
t(start-SVRoff)
engine start to SVR off time VP from 14.4 V to 5 V in 1.5 ms;
VSVR < 0.7 V; see Figure 6
-
40
75
ms
-
I2C-bus interface[3]
VIL
LOW-level input voltage
pins SCL and SDA
-
VIH
HIGH-level input voltage
pins SCL and SDA
2.3
VOL
LOW-level output voltage
pin SDA; IL = 5 mA
-
fSCL
SCL clock frequency
VADSEL
voltage on pin ADSEL
1.5
V
5.5
V
-
0.4
V
-
400
-
kHz
RADSEL = 0
4
5
11
V
RADSEL = 100 k
-
-
VP
V
-
2
10
A
I2C-bus address
A[6:0] = 1101 110
99
100
101
k
I2C-bus address
A[6:0] = 1101 111
29.7
30
30.3
k
I2C-bus address
A[6:0] = 1101 010
9.9
10
10.1
k
legacy mode
-
-
0.47
k
6
V
I2C-bus
address
A[6:0] = 1101 101
II(ADSEL)
input current on pin ADSEL VSTB = 5 V; VADSEL = 5 V
RADSEL
resistance on pin ADSEL
VP(latch)
latch supply voltage
RADSEL connected between pin
ADSEL and ground pin
will not react to address selection
changes
Start-up diagnostics
tsudiag
start-up diagnostic time
from start-up diagnostic
command via I2C-bus until
completion of start-up diagnostic;
VO + < 0.1 V; VO < 0.1 V (no
load) IB1[D1] = 1; see Figure 12
50
130
250
ms
td(sudiag-on)
start-up diagnostic to on
delay time
at 90 % of output signal;
IB1[D0:D1] = 11; see Figure 12
-
680
-
ms
Voffset
offset voltage
startup diagnostic offset voltage
under no load condition
1.3
2
2.5
V
RLdet(sudiag)
start-up diagnostic load
detection resistance
shorted load
high gain; IB3[D6:D5] = 00
-
-
0.5
low gain; IB3[D6:D5] = 11
-
-
1.5
normal load:
TDF8544
Product data sheet
high gain (IB3[D6:D5] = 00)
1.5
-
20
low gain (IB3[D6:D5] = 11)
3.2
-
20
line driver load
80
-
200
open load
400
-
-
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35 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 20. Characteristics …continued
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL(DIAG)
LOW-level output voltage
on pin DIAG
fault condition; IDIAG = 1 mA
-
-
0.3
V
VO(offset_det)
output voltage at offset
detection
1.0
1.3
2.0
V
THDclip
total harmonic distortion
clip detection level
Diagnostic
IB2[D7:D6] = 10; VP > 10 V
-
10
-
%
IB2[D7:D6] = 01; VP > 10 V
-
5
-
%
IB2[D7:D6] = 00; VP > 10 V
-
2
-
%
IB3[D4] = 0 or legacy mode
150
160
170
C
IB3[D4] = 1
Tj(AV)(pwarn)
pre-warning average
junction temperature
125
135
145
C
Tj(AV)(G(0.5dB))
average junction
Vi = 0.05 V
temperature for 0.5 dB gain
reduction
-
175
-
C
G(th_fold)
gain reduction of thermal
foldback
all channels will switch off
-
20
-
dB
Io
output current
I2C-bus mode; AC load bit set;
peak current
IB4[D1] = 1
580
-
-
mA
IB4[D1] = 0
320
-
-
mA
IB4[D1] = 1
-
-
250
mA
IB4[D1] = 0
-
-
125
mA
RL = 4 ; VP = 14.4 V;
THD = 0.5 %
19
22
-
W
RL = 4 ; VP = 14.4 V;
THD = 10 %
26
28
-
W
RL = 2 ; VP = 14.4 V;
THD = 0.5 %
34
37
-
W
RL = 2 ; VP = 14.4 V;
THD = 10 %
45
51
-
W
RL = 4 ; VP = 14.4 V;
Vi = 2 V RMS square wave
40
44
-
W
RL = 4 ; VP = 15.2 V;
Vi = 2 V RMS square wave
47
50
-
W
RL = 2 ; VP = 14.4 V;
Vi = 2 V RMS square wave
70
75
-
W
I2C-bus
mode; AC load bit not
set; peak current
Amplifier
Po
Po(max)
output power
maximum output power
TDF8544
Product data sheet
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36 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 20. Characteristics …continued
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
THD
total harmonic distortion
Po = 1 W to 12 W; fi = 1 kHz;
RL = 4
-
0.01
0.1
%
Po = 1 W to 12 W; fi = 10 kHz
-
0.2
0.4
%
line driver mode; Vo = 1 V RMS
and 4 V RMS
-
0.02
0.05
%
low gain mode; Po = 1 W to 12 W;
fi = 1 kHz; RL = 4
-
0.01
0.1
%
65
80
-
dB
55
65
-
dB
55
70
-
dB
common mode input to
differential output (VO(dif) / VI(cm)
+ 26 dB)
55
65
-
dB
common mode input to
common mode output
(VO(cm) / VI(cm) + 26 dB)
50
58
-
dB
from off to mute and mute to off
-
-
7.5
mV
from mute to on and on to mute
(soft mute)
-
-
7.5
mV
from off to on and on to off
(start-up diagnostic enabled)
-
-
7.5
mV
mute mode
-
15
23
V
line driver mode
-
25
33
V
cs
channel separation
RS = 1 k; RACGND = 250
[4]
fi = 1 kHz
fi = 10 kHz
SVRR
supply voltage ripple
rejection
100 Hz to 10 kHz; RS = 1 k;
RACGND = 250 ; tested at VP =
10.5 V
[4]
CMRR
common mode rejection
ratio
amplifier mode; Vcm = 0.3 V (p-p);
fi = 1 kHz to 3 kHz, RS = 1 k;
RACGND = 250
[4]
Vo
Vn(o)
output voltage variation
output noise voltage
plop during switch-on and
switch-off
[5]
filter 20 Hz to 22 kHz (6th order);
RS = 1 k
line driver mode; RS = 50
-
25
33
V
amplifier mode
-
43
65
V
amplifier mode; RS = 50
-
40
60
V
Gv(amp)
voltage gain amplifier
mode
single-ended in to differential out
25.5
26
26.5
dB
Gv(ld)
voltage gain line driver
mode
single-ended in to differential out
15.5
16
16.5
dB
Zi
input impedance
Tamb = 40 C to +105 C
38
62
99
k
Tamb = 0 C to 105 C
55
62
99
k
mute
mute attenuation
Vo / Vo(mute); Vi = 50 mV
80
92
-
dB
TDF8544
Product data sheet
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Rev. 2 — 29 August 2011
© NXP B.V. 2011. All rights reserved.
37 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Table 20. Characteristics …continued
Refer to test circuit (see Figure 30) at Tamb = 25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb = 25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vo(mute)(RMS)
RMS mute output voltage
Vi = 1 V RMS;
filter 20 Hz to 22 kHz
-
16
29
V
Bp
power bandwidth
1 dB
-
20 to
20000
-
Hz
CL(crit)
critical load capacitance
no oscillation; open load and 2
load; all outputs to GND or across
the load
33
-
-
nF
[1]
VSTB depends on the current into pin STB: minimum = (1429 ISTB) + 5.4 V, maximum = (3143 ISTB) + 5.6 V.
[2]
The times are specified without leakage current. For a leakage current of 5 A on pin SVR, the delta time is specified. If the capacitor
value on pin SVR changes 30 %, the specified time will also change 30 %. The specified times include an ESR of 15 for the
capacitor on pin SVR.
[3]
Standard I2C-bus specification: maximum LOW-level = 0.3VDD, minimum HIGH-level = 0.7VDD. To comply with 5 V and 3.3 V logic the
maximum LOW-level is defined by VDD = 5 V and the minimum HIGH-level by VDD = 3.3 V.
[4]
For optimum channel separation (cs), supply voltage ripple rejection (SVRR) and common mode rejection ratio (CMRR), a resistor
RS
R ACGND = ------ must be in series with the ACGND capacitor.
4
[5]
The plop-noise during amplifier switch-on and switch-off is measured using an ITU-R 2 k filter; see Figure 20.
input
DIFFERENTIAL
TO
SINGLE −
ENDED
5th ORDER
20 kHz
BUTTERWORTH
LOW-PASS
FILTER
ITU-R 2K
FILTER
RECTIFIER
PEAK
DETECTOR
OUTPUT
BUFFER
+ 40 dB GAIN
output
001aam706
Fig 19. Location of ITU-R 2K filter
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aam707
10
(4)
output
(dB)
−10
(1)
maximum
6 dB at 6 kHz
−30
0 dB at 2 kHz
(2)
−50
(3)
−70
10
102
103
104
105
f (Hz)
(1) 20 Hz.
(2) A-weighting.
(3) ITU-R average response meter.
(4) 20 kHz bandwidth limit.
Fig 20. TDF8544; plop noise test using ITU-R 2k filter
12. Performance diagrams
001aan036
10
THD + N
(%)
1
10−1
(1)
(2)
10−2
10−3
10
102
103
104
105
fi (Hz)
(1) Po = 1 W.
(2) Po = 10 W.
Fig 21. Total harmonic distortion as a function of input frequency; 4 load
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aan038
10
THD + N
(%)
1
10−1
(1)
(2)
10−2
10−3
10
102
103
104
105
fi (Hz)
(1) Po = 1 W.
(2) Po = 10 W.
Fig 22. Total harmonic distortion as a function of input frequency; 2 load
001aan039
10
THD + N
(%)
1
(3)
10−1
(2)
10−2
(1)
10−3
10−2
10−1
1
102
10
Po (Hz)
(1) fi = 1 kHz.
(2) fi = 100 Hz.
(3) fi = 10 kHz.
Fig 23. Total harmonic distortion as a function of output power; 4 load
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aan040
10
THD + N
(%)
1
(3)
10−1
(2)
10−2
(1)
10−3
10−1
1
102
10
Po (W)
(1) fi = 1 kHz.
(2) fi = 100 Hz.
(3) fi = 10 kHz.
Fig 24. Total harmonic distortion as a function of output power; 2 load
001aan041
80
Po
(W)
60
(3)
40
(1)
20
(2)
0
6
10
14
18
Vp (V)
(1) THD = 10 %.
(2) THD = 0.5 %.
(3) EIAJ.
Fig 25. Output power as a function of supply voltage; 4 load
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aan042
120
Po
(W)
(3)
80
(1)
40
(2)
0
6
10
14
18
Vp (V)
(1) THD = 10 %.
(2) THD = 0.5 %.
(3) EIAJ.
Fig 26. Output power as a function of supply voltage; 2 load
001aan092
0
αcs
(dB)
-20
-40
-60
-80
-100
10
102
103
104
105
fi (Hz)
Fig 27. Channel separation as a function of input frequency; 4 load
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aan093
0
αcs
(dB)
−20
−40
−60
−80
−100
10
102
103
104
105
fi (Hz)
Fig 28. Channel separation as a function of input frequency; 2 load
001aan044
0
SVRR
(dB)
−20
−40
−60
−80
−100
10
102
103
104
105
fi (Hz)
Fig 29. Supply voltage ripple rejection as a function of input frequency
TDF8544
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
13. Application information
RADSEL(1)
ADSEL
SDA SCL
1 (10) 26 (8) 23 (7)
VP1
VP2
21 (3)
7 (16)
+5 V
TDF8544
ENGINE START
PROTECTION
10 kΩ
10 kΩ
5 (9) DIAG
STB 2 (11)
Rs
470 nF
STANDBY/
FAST MUTE
IN3 16 (29)
SELECT
DIAGNOSTIC/
CLIP DETECT
I2C-BUS
MUTE
18 (2) OUT3+
26 dB/
16 dB
(2)
20 (1) OUT3-
PROTECTION/
DIAGNOSTIC
Rs
470 nF
IN1 12 (25)
MUTE
10 (17) OUT1+
26 dB/
16 dB
(2)
8 (18) OUT1-
PROTECTION/
DIAGNOSTIC
Rs
470 nF
IN4 15 (28)
MUTE
22 (6) OUT4+
26 dB/
16 dB
(2)
24 (4) OUT4-
PROTECTION/
DIAGNOSTIC
Rs
470 nF
IN2 13 (26)
MUTE
VP
6 (13) OUT2+
26 dB/
16 dB
(2)
4 (15) OUT2-
PROTECTION/
DIAGNOSTIC
27 (36) TAB
11 (24)
14 (27)
17 (30)
9 (23)
3 (14)
19 (32)
25 (5)
SVR
SGND
ACGND
PGND1
PGND2
PGND3
PGND4
10 μF(1)
2.2 μF(1)
001aan048
(1) The SVR and ACGND capacitors and the RADSEL resistor must be connected to pin SGND before they are connected to pin
PGNDn; the ACGND capacitor value must be close to 4 the input capacitor value. 4 470 nF capacitors can be used as an
alternative to the 2.2 F capacitor shown.
(2) For EMC reasons, a 10 nF capacitor can be connected between each amplifier output and ground.
Fig 30. Test and application diagram
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
13.1 Application PCB layout
001aan737
Fig 31. TDF8544J PCB top view
001aan738
Fig 32. TDF8544J PCB bottom view
Remark: Please use the TDF8544J board to evaluate the TDF8544SD. The TDF8544SD
does not fit on this board but is equal in behavior and performance.
TDF8544
Product data sheet
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45 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
001aao326
Fig 33. TDF8544TH PCB top view
001aao327
Fig 34. TDF8544TH PCB bottom view
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
13.2 Beep input
Circuit to amplify the beep signal from the microcontroller to all four amplifiers with gain
set to 0 dB.
ACGND
TDF8544
2.2 μF
1.7 kW
0.22 mF
from microcontroller
47 pF
100 W
001aan049
Fig 35. Beep input circuit
13.3 Clip detection on pin STB
8.5 V
10 kΩ
4.7 kΩ
TDF8544
18 kΩ
STB
MICROCONTROLLER
3.3 V
switch
10 kΩ
001aan050
Fig 36. Circuit for testing clip detection on pin STB
14. Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
15. Package outline
DBS27P: plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm)
SOT827-1
non-concave
Dh
x
D
Eh
view B: mounting base side
A2
d
B
j
E
A
L4
L3
L
1
L2
27
e1
Z
w M
bp
e
c
Q
v M
e2
m
0
10
20 mm
scale
DIMENSIONS (mm are the original dimensions)
bp
UNIT
A
A2
mm
19
4.65 0.60
4.35 0.45
c
0.5
0.3
D(1)
d
29.2 25.8
28.8 25.4
Dh
E(1)
e
e1
e2
Eh
j
L
L2
12
15.9
15.5
2
1
4
8
3.4
3.1
6.8
3.9
3.1
L3
L4
1.15 22.9
0.85 22.1
m
Q
v
4
2.1
1.8
0.6
w
x
0.25 0.03
Z(1)
1.8
1.2
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT827-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
03-07-29
Fig 37. Package outline SOT827-1 (DBS27P)
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
RDBS27P: plastic rectangular-DIL-bent-SIL (reverse bent) power package; 27 leads (row spacing 2.54 mm)
SOT878-1
non-concave
Dh
x
D
Eh
view B: mounting base side
d
A2
B
j
E
A
L
1
27
c
e1
Z
e2
Q
e
w
bp
v
L1
M
0
10
M
20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A2
bp
c
D (1)
d
Dh
E (1)
e
e1
e2
Eh
j
L
L1
Q
v
w
x
Z (1)
mm
13.5
4.65
4.35
0.60
0.45
0.5
0.3
29.2
28.8
25.8
25.4
12
15.9
15.5
2
1
2.54
8
3.4
3.1
3.75
3.15
3.75
3.15
2.1
1.8
0.6
0.25
0.03
1.8
1.2
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-01-11
05-01-26
SOT878-1
Fig 38. Package outline SOT878-1 (RDBS27P)
TDF8544
Product data sheet
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49 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-1
D
E
A
x
c
y
X
E2
v
HE
A
D1
D2
1
18
pin 1 index
Q
A
A2
E1
(A 3)
A4
θ
Lp
detail X
36
19
z
w
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max. A2
mm
3.5
A3
A4(1)
+0.08
3.4
0.35
−0.04
3.3
D1
D2
E (2)
E1
E2
e
HE
Lp
Q
0.38 0.32 16.0 13.0
0.25 0.23 15.8 12.6
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
0.65
14.5
13.9
1.1
0.8
1.7
1.5
bp
c
D (2)
v
w
x
y
0.25 0.12 0.03 0.07
Z
θ
2.55
2.20
8°
0°
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-03-09
04-05-25
SOT851-1
Fig 39. Package outline SOT851-1 (HSOP36)
TDF8544
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
16. Abbreviations
Table 21.
Abbreviations
Acronym
Description
BCDMOS
Bipolar Complementary Double-diffused Metal-Oxide Semiconductor
BTL
Bridge Tied Load
CMOS
Complementary Metal-Oxide Semiconductor
DMOS
Diffusion Metal Oxide Semiconductor
DSP
Digital Signal Processor
EMC
ElectroMagnetic Compatibility
ESR
Equivalent Series Resistance
NMOS
Negative Metal Oxide Semiconductor
PMOS
Positive Metal Oxide Semiconductor
POR
Power-On Reset
SOAR
Safe Operating ARea
SOI
Silicon On Insulator
17. Revision history
Table 22.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDF8544 v.2
20110829
Product data sheet
-
TDF8544 v.1
TDF8544 v.1
20110810
Objective data sheet
-
-
TDF8544
Product data sheet
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TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
TDF8544
Product data sheet
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52 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TDF8544
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53 of 54
TDF8544
NXP Semiconductors
I2C-bus controlled 4 50 W power amplifier
20. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.8
8
8.1
8.2
9
10
11
12
13
13.1
13.2
13.3
14
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 7
Start-up and shut-down sequence . . . . . . . . . . 7
Engine start and low voltage operation. . . . . . . 9
Power-on reset and supply voltage spikes . . . 10
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output protection and short-circuit protection. 10
Loss-of-ground/loss of VP . . . . . . . . . . . . . . . . 11
Speaker fault detection . . . . . . . . . . . . . . . . . . 12
Overvoltage warning and load dump
protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal pre-warning and thermal protection . 13
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Start-up diagnostics with DC load detection . . 14
DC offset detection . . . . . . . . . . . . . . . . . . . . . 17
AC load detection . . . . . . . . . . . . . . . . . . . . . . 18
Distortion clip detection . . . . . . . . . . . . . . . . . 20
Line driver mode and low gain mode . . . . . . . 20
I2C-bus, legacy mode and address select pin 21
Address select (pin ADSEL) . . . . . . . . . . . . . . 21
Legacy mode (RADSEL < 470 W). . . . . . . . . . . 21
I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C-bus diagnostic bits read-out/cleared after
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Amplifier in combination with a DC-to-DC
converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C-bus specification . . . . . . . . . . . . . . . . . . . . 22
I2C-bus instruction bytes. . . . . . . . . . . . . . . . . 23
I2C-bus data bytes . . . . . . . . . . . . . . . . . . . . . 27
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal characteristics . . . . . . . . . . . . . . . . . 32
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 32
Performance diagrams . . . . . . . . . . . . . . . . . . 39
Application information. . . . . . . . . . . . . . . . . . 44
Application PCB layout . . . . . . . . . . . . . . . . . . 45
Beep input . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Clip detection on pin STB . . . . . . . . . . . . . . . . 47
Test information . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1
15
16
17
18
18.1
18.2
18.3
18.4
19
20
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
48
51
51
52
52
52
52
53
53
54
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 August 2011
Document identifier: TDF8544
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
NXP:
TDF8544TH/N3,118