TEA19051BAPTK/1J

TEA19051BTK USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Rev. 3 — 21 January 2019 1 Product data sheet General description The TEA19051BTK is a highly configurable secondary side SMPS controller that is available in many factory configured versions. Section 15 gives an overview of the offthe-shelf available versions of the TEA19051BTK. To inquire about the possibilities of customer-specific versions, contact your local sales representative. The TEA19051BTK supports the following protocols: • • • • USB Type-C v.1.3 USB power delivery (USB-PD) including programmable power supply (PPS) Battery Charging 1.2 (BC1.2) Qualcomm® QuickCharge™ QC2.0, QC3.0, and QC4+ A complete smart-charging switch mode power supply (SMPS) can be built in combination with the TEA193x primary controller and the TEA199x secondary side synchronous rectifier (SR) controller. The TEA19051BTK can be provided in several small packages with low pin count. Due to its small number of external components, a small form factor SMPS can be built that meets efficiency requirements like CoC Tier-2, EuP Iot6, and DOE v6 with an extremely no-load power (< 30 mW). The TEA19051BTK has a high level of digital integration. It incorporates all required circuits, including a charge pump to drive an external NMOS load switch directly, a USBPD physical interface (PHY), and an integrated driver for fast output discharge. The output voltage and output current are continuously measured and are used to control the SMPS. Two GPIO pins measure the adapter temperature and the temperature in the cable/connector. Optionally, the GPIO pins can be used for other features, like supply (see Table 4). The die temperature of the TEA19051BTK is monitored via an internal temperature sensor. Multiple protections ensure the best-in-class charging safety for the TEA19051BTK. To ensure correct operation under all conditions, all protections except UVP are implemented in hardware. The response of these protections can be programmed as latched or safe restart. Although not recommended, these protections can also be disabled individually via the settings in the non-volatile multi-time programmable (MTP) memory. If an output short circuit occurs, the power dissipation in the adapter can be below 50 mW. For output voltage regulation, current regulation, and protection, only a single optocoupler is required in the application. The TEA19051BTK operates in CV mode with a better than 2 % voltage accuracy. In CC mode, it operates with a better than 2 % full-load current accuracy. TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 2 Features and benefits 2.1 General • Best-in-class fail-safe application for high-power adapters; gives complete protection against overload conditions in the load (e.g. phone) • Wide output voltage operating range (2.9 V to 21 V) • Ultra-high efficiency together with TEA193x QR/DCM controller and TEA199x SR controller • Very low no-load power (< 30 mW for the complete system solution) • High power density • Dedicated SW pin to drive external NMOS directly • Constant voltage (CV) and constant current (CC) control (programmable level) • Precise voltage and current control with low minimum step size (voltage 12-bit DAC, current 10-bit DAC) • Continuous measurement of output voltage and output current with a better than 2 % accuracy • Low-cost HVSON16 package (suitable for reflow soldering) • Low-cost bill of materials (BOM; ≈15 external components) • Embedded MCU (with ROM, RAM, and MTP memory) • Discharge pin for fast output voltage ramp down • Built-in series regulator and programmable cable compensation • Non-volatile MTP memory for storage of system configuration parameters 2.2 Protocol support • USB Type-C v.1.3 • USB power delivery (USB-PD) 2.0 and 3.0 including programmable power supply (PPS) • Qualcomm® QuickCharge™ QC2.0, QC3.0, and QC4+ protocols • Battery Charging 1.2 (BC 1.2) • Unstructured vendor defined messages (VDMs), which can be used for MTP programming, e.g. to get Vendor IDs TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 2 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 2.3 Protections • • • • • • • • • • • Overtemperature protection (OTP): one internal and two external Adaptive overvoltage protection (OVP) Adaptive undervoltage protection (UVP) Overcurrent protection (OCP) Undervoltage lockout (UVLO) protection Output short protection (OSP) Open-supply protection (OSUP) Open-ground protection (OGP) Overvoltage protection DP, DM, CC1, and CC2 pins Soft short protection at the CC1 and CC2 pins Soft short protection at the output To ensure safe operation, the TEA19051BTK switches off the load during fault conditions. 3 Applications • USB chargers for smart phones and tablets supporting the Qualcomm® QuickCharge™ QC2.0, QC3.0, and QC4+ protocols • USB-PD 3.0, type C 1.3 chargers with optional VDM support for smartphones and tablets TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 3 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 4 Ordering information Table 1. Ordering information Type number TEA19051BAATK/1 TEA19051BABTK/1 Package Name Description Version HVSON16 plastic small enhanced very thin small outline package; no leads; 16 terminals; body: 3.5 × 5.5 × 0.85 mm SOT1308-1 TEA19051BACTK/1 TEA19051BAFTK/1 TEA19051BAGTK/1 TEA19051BAHTK/1 TEA19051BAKTK/1 TEA19051BAMTK/1 TEA19051BAPTK/1 TEA19051BARTK/1 5 Marking Table 2. Marking TEA19051BTK Product data sheet Type number Marking code TEA19051BAATK A19051BAA TEA19051BABTK A19051BAB TEA19051BACTK A19051BAC TEA19051BAFTK A19051BAF TEA19051BAGTK A19051BAG TEA19051BAHTK A19051BAH TEA19051BAKTK A19051BAK TEA19051BAMTK A19051BAM TEA19051BAPTK A19051BAP TEA19051BARTK A19051BAR All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 4 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 6 Block diagram OPTO VCC BG_det 30 µA BG_OK SW_OFF REF VCC_ below_xxx 4 bits OVP BG_OK SUPPLY BLOCK UVLO 20 mA Vout_below_vcc VSNS OCP DISCH CCmode amp 0.8 V ADC DAC DAC DAC DAC DAC VOUT_below_0p8 ADC 3 levels + off ADC ISNS CHARGE PUMP GPIO1 3.3 V OTP ana_ctrl PARAMETER MTP 3.3 V SW USB-PD PROTO UVLO USB-PD PHY SW_OFF OR 3.3 V GPIO2 ana_ctrl 3 levels + off TYPEC CONDET 3.3 V USB BLOCK RAM SGND I2C (M/S) µC ROM OSC GND OVP CC1 OVP CC2 OVP DP OVP DM DIGITAL EDP SCL SDA aaa-025896 Figure 1. TEA19051BTK block diagram TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 5 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 7 Pinning information 7.1 Pinning VCC 1 16 SW OPTO 2 15 GND SGND 3 14 DISCH GPIO1 4 ISNS 5 GPIO2 6 VSNS 7 SCL 8 13 CC1 IC 12 CC2 11 DP 10 DM 17 EDP 9 SDA aaa-025739 Figure 2. TEA19051BTK pinning diagram (SOT1308-1) 7.2 Pin description Table 3. Pin description TEA19051BTK Product data sheet Symbol Pin Description VCC 1 supply voltage OPTO 2 OPTO driver SGND 3 sense ground GPIO1 4 general-purpose input/output ISNS 5 current sense input GPIO2 6 general-purpose input/output VSNS 7 voltage sense input SCL 8 I C clock line SDA 9 I C data line DM 10 negative terminal of the data communication line DP 11 positive terminal of the data communication line CC2 12 type C CC2 line detection and USB-PD communication CC1 13 type C CC1 line detection and USB-PD communication DISCH 14 fast discharge sink GND 15 ground SW 16 NMOS gate drive output EDP 17 exposed die pad 2 2 All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 6 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8 Functional description The TEA19051BTK can be considered as a versatile programmable replacement for the well-known TL431 shunt regulator series, where: • The VSNS pin takes the role of the REF input of the TL431 • The OPTO pin takes the role of the cathode • The GND pin takes the role of the anode In addition to the constant voltage (CV) mode, which is regulated via the VSNS pin, the system supports constant current (CC) mode. The current control loop is regulated and the cable compensation is added via the ISNS pin. Alternatively, the ISNS input can be used for overcurrent protection (OCP; see Table 4). Several other protections are available. Many of these protections are programmable as latched or safe restart. For guaranteed safety, all protections are implemented in hardware. So, even when the microcontroller stops, the protections are still functional. The output voltage and the output current can be controlled via USB-PD using the CC pins. They can also be controlled via QC using the DP and DM pins. The output current and the output voltage are continuously measured via an integrated AD-converter. The values can be made available continuously via the USB-PD protocol. The applied time constant of the digital filter is initialized via the firmware. A dedicated signal that indicates a stable output voltage/output current for a reliable measurement is available. It can be used, for example, to determine and monitor the cable resistance in the portable device. The external temperatures, measured via the GPIO1 and GPIO2 pins, are continuously monitored. From the GPIO voltages and applied currents, the controller calculates the corresponding temperatures. These temperatures can be communicated to the portable device. Optionally, an OTP function is added to this external temperature measurement, which is programmable via MTP (see Table 4). The available protections are implemented in hardware. They are independent of processor actions. These protections in combination with the NMOS load switch ensure a fully safe operation with only one optocoupler. When the optocoupler fails, the OVP of the primary side controller (TEA1936x) limits the maximum output voltage. The TEA19051BTK fully supports the type-C connector standard. When a Type C receptacle is used, the CC1/CC2 pair is used for plug attach/detach detection. It is also meant to support the USB-PD communication standard. The DP/DM pair is meant to support: • Battery Charging 1.2 • Qualcomm® QuickCharge™ QC2.0 and QC3.0 The USB-PD specification requires the use of a load switch and certain discharge behavior of the output voltage at the connector Vbus. So, to drive the gate of an external NMOS switch, the TEA19051BTK is equipped with an SW pin. To be able to discharge Vbus using an external resistor in series with an internal switch, the TEA19051BTK is equipped with a DISCH pin. User-defined parameters can be stored in the non-volatile multi-time programmable (MTP) memory. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 7 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.1 Start-up and supply The TEA19051BTK is supplied via the VCC pin connected to the secondary DC voltage of an AC-to-DC SMPS converter (see Figure 7). To control the primary side controller, this VCC voltage is regulated via an integrated voltage/current control loop with external loop compensation and an external optocoupler. This optocoupler is part of the gain loop of the primary side SMPS controller. At each start-up and after power-on reset, the optocoupler current is initially zero. So, the AC-to-DC converter starts up with full output power, resulting in a rapid increase of the VCC voltage. Due to the low VCC(start) level (≈3 V), the TEA19051BTK ensures that it is fully operating before the VCC reaches the default initial regulation level. The default values of the initial regulation level are 5 V and 3 A and they are programmed in the nonvolatile memory (MTP). At power-on reset, the safe default values, which are read from MTP, are set. When the VCC voltage is below the UVLO level, the external NMOS load switch is off. When the output is shorted while the load switch is closed, the UVLO is also triggered. The load switch is then immediately opened and the system restarts after the safe restart timer. When the VCC exceeds the UVLO level, all circuits, the initial DAC value, and the resistive divider ratio are initialized. The system regulates the output to 5 V with a limited output current of 3 A. All these values can be set via the MTP. To minimize the output voltage overshoot after start-up, an internal 20 mA current sink is applied to VCC when the VCC voltage exceeds 1.05 × Vo(default). The sink current remains active until the VCC voltage has dropped to below 1.05 × Vo(default) again. After the output voltage has stabilized, the load switch becomes conducting and the system waits for an attach. Before the attach, only the essential circuits are working which reduces the no-load power to its minimum. When the voltage on one of the CC pins drops to below the VIH(Rd) level, an attach is detected and all circuits are enabled. If a protocol is detected, it is allowed to change the voltage and current. 1.05 x Vo(default) UVLO 20 mA discharge VCC reading EEPROM 5 V regulation initialization aaa-023848 Figure 3. Start-up sequence The TEA19051BTK operates on supply voltages up to 21 V. The voltage on the VCC pin is used to detect an OVP and UVP. The OVP and UVP level are set as a percentage of the requested output voltage level. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 8 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS If the supply voltage drops to below the UVLO level, the system returns to the no-supply state and opens the load switch. Analog circuits are reset below UVLO. The internal digital circuits are reset below the band gap voltage reference level. 8.2 Voltage loop The analog constant voltage (CV) loop regulates VCC such that the voltage on the VSNS pin equals the internal reference voltage. An external resistor divider is connected between VCC, the VSNS pin, and ground. The value of this divider must match the value that is programmed in MTP exactly. It depends on the maximum voltage in the application. The divider values are: • • • • 1/ 2.5; maximum PDO voltage ≤ 6 V 1/5.476; maximum PDO voltage ≤ 13 V 1/8.325; maximum PDO voltage ≤ 20 V 1/8.828; maximum PDO voltage ≤ 21 V The CV loop is regulated by varying the current through an optocoupler diode similar to a TL431 driven control loop commonly used in switch mode power supplies. The RC combination between the OPTO and VSNS pin determines the dynamic behavior of the integrating part of the control loop. The resistor in series with the optocoupler diode determines the dynamic behavior of the proportional part of the control loop. To prevent saturation of the control loop during switching, a diode is placed in parallel to this resistor. See Section 13.3 for more information about the control loop. When the voltage loop reference is set to a higher value using the USB-PD or the QC protocol, the internal reference voltage is updated to the new setting within 20 μs. The output voltage is regulated to the requested voltage with a speed determined by the control loop. If there is a transition down, a predefined ramp down sequence is followed to prevent a high undershoot. Depending on the step size, the ramp down either follows a linear or a parabolic slope. For a transition up, no special measures are required to prevent an overshoot. The reason is that the charging current of the loop capacitor lifts the voltage on the VSNS pin when the VCC voltage in the application increases. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 9 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS VCC OPTO aaa-021703 a. Circuit VCC Vopto loop saturated discharge aaa-021704 b. Curve Figure 4. Linear transition down (no load) A linear ramp-down (see Figure 4) can yield a perfect linear ramp of the output voltage without any undershoot. However, depending on the loop bandwidth, the voltage loop can end up in saturation. Saturation hampers a fast response to a load step immediately following the end of the ramp (most protocols do not allow any load to be drawn during a transition). Making the ramp down slower can prevent saturation of the loop. However, a slower ramp down can contradict with the maximum discharge time most protocols specify. A parabolic discharge curve (see Figure 5; patent pending) initially causes the voltage loop to saturate, due to the initial rapid ramp down. However, it allows the loop to recover and to resume regulation toward the end of the curve. The total parabolic sequence time must be chosen such that no undershoot under the final end value occurs. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 10 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS VCC OPTO aaa-021703 a. Circuit VCC Vopto loop reference parabola depth loop saturated f(parabola factor) discharge aaa-021705 b. Curve Figure 5. Parabolic transition down (no-load) 8.3 Current loop The voltage drop across a small external series resistor between the output return terminal and the converter ground is supplied to the ISNS pin. An internal amplifier multiplies the voltage on the ISNS pin by a factor of 50. The output voltage of the amplifier must remain below 2.5 V. The external resistor value can be chosen from 2 mΩ up to 22.5 mΩ in steps of 0.02 mΩ. The external resistor value must correspond to the programmed value in MTP. Any deviation from this MTP value, e.g. due to PCB-layout imperfections, causes a current error and must be corrected (see Section 13.2). The ground connection of the external sense resistor must be connected to the SGND pin via an independent sense wire. The combination of the maximum current in the application, the sense resistor, and the gain of the internal amplifier must be chosen such that the output voltage of the internal amplifier remains below 2.5 V. When the application is used in CC-mode, an RC-combination must be connected between the OPTO pin and the ISNS pin (see Section 13.4). TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 11 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.4 Cable compensation With cable compensation enabled, the output voltage is increased when the output current increases to compensate for the voltage drop over the cable. The value of the cable compensation is the same for all PDOs. It is set in MTP between the minimum and maximum values (see Table 4). Setting the cable compensation above 200 mV/A is not recommendable. The cable compensation can be enabled/disabled for each individual PDO. 8.5 Load switch A low-cost NMOS transistor is used as load switch between VCC and Vbus (see Figure 7). A dedicated switch-drive output pin (SW pin) controls this NMOS transistor. The output (high) level of the switch drive output is VCC + 6 V using an internal charge pump. As long as VCC is below the UVLO level or if the VCC connection is open, the SW pin is held low, ensuring that the load switch is off. To ensure that the NMOS is also kept off when the SW pin is disconnected, an external (high-ohmic) resistor is required between the gate of the NMOS and Vbus. To avoid charging VCC via the back-gate diode of the load switch, it is possible to apply two NMOS switches in series, with their sources connected together. 8.6 Discharge function The DISCH pin, which has an internal low-ohmic switch, provides the means to discharge the output Vbus quickly. An external series resistor limits the maximum current and the IC dissipation. To check if the output voltage has dropped to below 0.8 V, a comparator is implemented. This voltage drop is a requirement of the USB-PD specification (vSafe0V) if there is a hard reset. When the internal DISCH switch is activated, the voltage at the DISCH pin is always low, because of the external current limiting resistor. A mechanism has been implemented to check the real output voltage. During a hard reset discharge sequence, when VCC is below vSafe5V, the switch is opened every millisecond for 20 μs to check the output voltage at the end of the 20 μs period. The check of the output voltage is done until the voltage remains below 0.7 V and the hard reset discharge sequence is terminated. For this check to work properly, the capacitance on the DISCH pin and the external current limiting resistor must have a time constant that is short enough. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 12 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS To ensure that the output remains low, a 1 mA sink current is present on the DISCH pin when both the load switch and discharge switch are off. The period that the DISCH pin is active in unattached state (td(act)) is typically 100 ms. The reason for this limitation is to prevent that excessive power dissipation occurs if an external Vbus voltage is applied. 8.7 Detach detection When the voltage on one of the CC pins is greater than 1.2 V, a detach is detected. If the type C cable is disconnected, the output voltage is regulated to its default value (5 V) after 200 µs. 8.8 Internal temperature measurement The internal die temperature is monitored continuously. Its value can be requested with the appropriate vendor defined message (VDM). When the internal OTP (see Table 5) is enabled, the internal OTP is triggered when the die temperature exceeds the value that is programmed in MTP. 8.9 GPIO pins The internal hardware of the GPIO1 and GPIO2 pins is identical. In the MTP, the following functions can be selected for each GPIO pin: • • • • Off NTC NTC + OTP Supply In the sections below, the functions are further explained. 8.9.1 Off The GPIO pin is disabled and can be connected to ground. 8.9.2 NTC With the NTC function enabled, the GPIO pins can be used to measure the adapter and cable connector temperature via NTC resistors. The NTC connected to GPIO1 is meant for measuring the (cable) connector temperature. The NTC connected to GPIO2 for measuring the adapter temperature. The temperature values can be requested with the appropriate VDM command. To ensure an accurate temperature measurement over the complete temperature range, both external NTCs are supplied via an adaptive current source (see Figure 6). TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 13 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS I1 = 15 µA I2 = 60 µA I3 = 240 µA disable MTP OTP level DIGITAL CONTROL FIRMWARE ADC GPIO CC1 CC2 USB-PD aaa-028134 a. Circuit VGPIO I1 = 15 µA 3 I2 = 60 µA I3 = 240 µA 2.5 2 1.5 1 0.5 0.4 0 -50 0 50 100 Temperature 150 aaa-028135 b. Curves Figure 6. External NTC is supplied via adaptive current sources The voltage at a GPIO pin is measured via an internal A-to-D converter. If the voltage on the GPIO pin drops to below 400 mV, the source current is increased. If the voltage on the GPIO pin exceeds 2.4 V, the source current is decreased. When a 47 kΩ NTC resistor with a Beta of 4108 is used, the temperature is accurately measured with a better than < 5 °C accuracy within a range of 0 °C to > 120 °C. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 14 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.9.3 NTC + OTP With this function enabled, an OTP function is added to the NTC function. The OTP function is integrated in hardware. The OTP level is set in MTP. When the NTC (+ OTP) function is enabled for a GPIO pin, but this GPIO pin is not used in the application, it must be connected to ground via a fixed 47 kΩ resistor. Do not leave the unused pin floating or connect it to ground. 8.9.4 Supply When the supply functionality is chosen for the GPIO pin in MTP, the output of the GPIO can be used to supply, e.g., an EEPROM. The following modes can be chosen via MTP: • The supply signal is high continuously 2 • Dynamic switching of the I C slave supply on the GPIO pin. 2 When the master activates I C communication, the supply is turned on first. After a 2 2 delay, the I C communications start. When I C communications stops for 1 s, the supply is turned off. • The signal on the GPIO can have inverted behavior 8.10 Communication If a type-C receptacle is used, attach/detach detection and USB-PD communication is provided on the CC pins. DP and DM provide the communication interface for QC2.0 and QC3.0. If a type-A receptacle is used, attach/detach detection can be disabled (via MTP). The load switch is closed (when no protection is triggered). 8.10.1 USB Type-C The TEA19051BTK complies with the USB Type-C 1.3 specification (see Ref. 2) in the sense that the distinct pull-up current values support attach/detach and current capability advertising. The attach/detach detection is done in the hardware. So, if there is a detach, a return of Vbus to vSafe5V is always ensured. The hardware implementation of the return of Vbus to vSafe5V eliminates the risk of software implementations where Vbus may stay at an unsafe level if the program execution stalls. To support currents higher than 3 A, use a captive cable. Vconn is not supported. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 15 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.10.2 USB-PD The TEA19051BTK supports the USB-PD, release 3.0 specification (see Ref. 4) as far as it is required for a DFP. The TEA19051BTK supports the programmable power supply (PPS) part of the USB-PD 3.0 specification. The TEA19051BTK can be programmed such that it only complies with the USB-PD 2.0 specification. With these MTP settings, power-brick USB-PD-2.0 testing can be done and USB-PD 2.0 qualification is possible. Maximum seven different power data objects (PDO) can be defined in the nonvolatile memory (MTP). Released types have a predefined set of PDOs programmed (see Table 4). For each PDO, current limit type (OCP/CC) and cable compensation on/ off can be set. However, any other voltage or current within the range can be defined in a PDO. Four of the seven PDOs can be set as programmable power supply (PPS) instead of a Fixed Power Supply via MTP. The TEA19051BTK supports the QC4+ VDMs. To make USB-PD certification possible, QC2.0 and QC3.0 must be disabled. Disabling QC2.0 and QC3.0 can be done in MTP or by not connecting the TEA19051BTK DP and DM pins. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. 8.10.3 Discover identification The TEA19051BTK supports the discover identification protocol in USB-PD. It is possible to program VID, PID, and BCD values in MTP. These values can be requested via VDM messages. The maximum power, which is used to determine the power profile, can be set in MTP. 8.10.4 Battery charging The standard battery charging protocol is supported according to the BC1.2 specification (see Ref. 1). 8.10.5 Quick charge The Qualcomm® QuickCharge™ QC2.0, QC3.0, and QC4+ protocols are fully supported (see Ref. 5, Ref. 6, and Ref. 7). The required fixed and PPS PDOs can be configured in MTP. The fixed PDO settings that are used for QC2.0 can be set via MTP. When QC 3.0 is used, the voltage can be set via this protocol from 3.6 V to 12 V in steps of 200 mV. The maximum voltage can be limited if wanted via MTP settings. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 16 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.10.6 MTP configuration The TEA19051BTK is configurable via MTP. The different types are defined in Section 15. Table 4 gives an overview of the programmability with their minimum/ maximum values. Table 4. MTP configuration options Function default output voltage default maximum output current maximum level step size - 3V 10 V 50 mV - 0.3 A 5A 20 mA - - - - 62 °C 111 °C variable but < 5 °C disable; NTC; [1] NTC with OTP ; Supply - - - GPIO2 protection level - 62 °C 111 °C variable but < 5 °C OTP internal - 27 °C 135 °C 4.3 °C external sense resistor(Rsns) - 2 mΩ 22 mΩ 0.02 mΩ external resistor divider VCC/ [2] VSNS (=DIV) 8.325; 2.5; 5.476; 8.828 - - - - 0 mV/A Rsns * DIV * 8 V/A variable OCP-mode/CC-mode - - - 5V 3A - - - - 3V 0.3 A 20 V 10 A 0.05 V 0.01 A [4] 120 %; 125 %; 130 % - - - [4] off; 60 %; 70 %; 80 % - - - off; 70 %; 80 %; 90 % - - - GPIO1 protection level GPIO2 [3] cable compensation CC mode or OCP mode PDO1 PDO2; PDO3; PDO4; PDO5; PDO6; PDO7 OVP level (PDO) UVP level (PDO) UVP level (APDO) [4] [4] PDO QC enable TRUE/FALSE - - - PDO PPS enable TRUE/FALSE - - - QC3.0 cable compensation enable TRUE/FALSE - - - - 0W 102.3 W 0.1 W USB3.0 enable TRUE/FALSE - - - power limit PPS TRUE/FALSE - - - - 3.3 V 20 V - [5] QC3.0 maximum power minimum voltage APDO [1] [2] [3] [4] [5] Product data sheet minimum level disable; NTC; [1] NTC with OTP ; Supply GPIO1 TEA19051BTK Options The NTC readout and OTP levels are defined with an NTC of 47 kΩ and a B-constant of 4108. Maximum output voltage for 5.476 is 13 V. Maximum output voltage for 2.5 V is 6 V. Cable compensation above 200 mV/A is not recommended. Can be selected for each PDO individually. Maximum 4 PDOs can be an APDO. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 17 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.11 Protections Table 5 gives an overview of the available protections. All protections except the OGP operate in safe restart mode. All protections except UVP are implemented in hardware. When a fault condition occurs, the load switch is immediately opened. When the fault condition is removed, the load switch is closed again. The VCC is set to default and the minimum delay defined in MTP is passed. 8.11.1 Protections overview Table 5. Overview of protections 8.11.2 Protection Description Implementation Default filter UVLO undervoltage lockout hardware - OVP overvoltage protection hardware 30 μs OCP overcurrent protection hardware 20 ms OTP (internal) overtemperature protection hardware - 2 times OTP (external) overtemperature protection hardware - OGP open-ground protection hardware - UVP undervoltage protection software - OSUP open-supply (VCC) protection hardware - OV_DP_DM overvoltage protection DP and DM pins hardware 127 μs OV_CC1_CC2 overvoltage protection CC1 and CC2 pins hardware 127 μs Secondary side safe restart protection When a safe restart protection is triggered, the load switch is immediately turned off. The voltage loop is kept on and is regulated to the initial value (5 V typical). As the load switch is immediately turned off before the regulation reduces the output power, the VCC voltage may increase. To ensure that the VCC voltage has dropped to a safe value, before the load switch is turned on again, VCC is discharged via an internal current source of 20 mA if it exceeds the level of 1.05 × Vdefault. When the protection is triggered, the safe restart timer is started. After 1 s (default value), a restart sequence is performed, which reinitializes all circuits. Optionally, most protections can be changed to latched protections in MTP. 8.11.3 Undervoltage lockout (UVLO) The level at which the UVLO protection is triggered is fixed. When VCC drops to below the UVLO level, the load switch is immediately turned off. All settings are reset to their initial values. Internal circuitries are disabled. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 18 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.11.4 Overvoltage protection (OVP) The OVP level is set as a percentage of the requested output voltage level. The OVP level is set to default 125 % (V < 9 V) or 120 % (V ≥ 9 V) of the programmed output voltage. When VCC continuously exceeds this level for longer than the minimum OVP time (default 30 μs), the OVP protection is triggered. 8.11.5 Overcurrent protection (OCP) The default TEA19051BTK setting is CC mode. In CC mode, the current loop defines the maximum current. Instead, the OCP mode can be selected via MTP. The OCP level can be programmed individually for each PDO. OCP is only triggered if the OCP mode is set for the corresponding PDO and the output current is continuously higher than the programmed current level for more than the programmed OCP blanking time. 8.11.6 Overtemperature protection (OTP) 8.11.6.1 Internal OTP When the internally measured temperature exceeds the programmed OTP setting, OTP is triggered, unless the protection is disabled in MTP. The temperature level can be defined in MTP. The default value is 113 °C. Furthermore, the internal temperature sensor can be used to measure the temperature. The measured temperature can be sent via USB-PD. 8.11.6.2 External OTP When the mode "NTC+OTP" is selected for GPIO1 (cable connector temperature) or GPIO2 (adapter temperature) in the MTP and the externally measured temperature exceeds the programmed OTP setting, OTP is triggered. The temperature level can be defined in MTP. The default value is 90 °C (see Section 15 and Table 4). 8.11.7 Open-ground protection (OGP) An open-ground event is detected by monitoring the difference in voltage between the GND and SGND pins. When the difference is greater than the specified maximum voltage difference, OGP is triggered, unless the protection is disabled. This feature protects the application from supplying high currents to the load when the ground pins of the sense resistor are not properly connected. 8.11.8 Open-supply protection (OSUP) When the IC is not supplied via the VCC pin any more, the voltage on the OPTO pin is used to open the external load switch. Opening the external load switch prevents that the load is damaged if the VCC pin is disconnected. 8.11.9 Undervoltage protection (UVP) The UVP level is set to 60 % PDO level. The reaction to a triggering of UVP is programmed in the firmware. The protection is a safe restart protection by default. The level can never be lower than the UVLO level. The level can be adjusted via MTP. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 19 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 8.11.10 Output short protection (OSP) At a shorted output, the VCC voltage drops to below the UVLO level. The load switch is turned off. After the programmed safe restart time, the output is enabled again. To meet the average input power requirement at a shorted output, a proper safe restart time must be chosen. When the VCC voltage exceeds the UVLO level, the primary controller initially limits the maximum output power. Because the safe restart time is set to 1 s, the dissipation is limited to < 50 mW. This limitation prevents that the application heats up when the output is shorted. 8.11.11 OVP DP and DM pins (OV_DP_DM) The overvoltage protection of the DP and DM pins can be enabled in MTP. However, it is switched off by default. OV_DP_DM is a safe restart protection. When the DP or DM pin is shorted to Vbus, this protection is triggered. The trigger level of the OV_DP_DM is at 4.5 V. To prevent unwanted triggering, it has a 127 µs (default) blanking time. 8.11.12 OVP CC1 and CC2 pins (OV_CC1_CC2) The overvoltage protection of the CC1 and CC2 pins can be enabled in MTP. However, it is switched off by default. OV_CC1_CC2 is a safe restart protection. When the CC1 or CC2 pin is shorted to Vbus, this protection is triggered. The trigger level of the OV_CC1_CC2 is at 4.5 V. To prevent unwanted triggering, it has a 127 µs (default) blanking time. 8.11.13 Soft short protection CC pins (SHORT_CC1_CC2) The CC pins are protected with a soft-short protection that measures the impedance of the CC lines. When the measured impedance is not according to the USB-PD specification, the load switch is opened. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 20 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 9 Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Voltages VVCC voltage on pin VCC −0.5 +26 V VOPTO voltage on pin OPTO −0.5 +26 V VCC1 voltage on pin CC1 −0.5 +26 V VCC2 voltage on pin CC2 −0.5 +26 V VDP voltage on pin DP −0.5 +6 V VDM voltage on pin DM −0.5 +6 V VSW voltage on pin SW −0.5 VCC + 9 V VDISCH voltage on pin DISCH −0.5 +26 V VVSNS voltage on pin VSNS −0.5 +3.6 V VISNS voltage on pin ISNS −0.5 +3.6 V VGPIO1 voltage on pin GPIO1 −0.5 +3.6 V VGPIO2 voltage on pin GPIO2 −0.5 +3.6 V VSDA voltage on pin SDA −0.5 +3.6 V VSCL voltage on pin SCL −0.5 +3.6 V Tstg storage temperature −65 +150 °C Tj junction temperature −40 +150 °C human body model (HBM) −2000 +2000 V charged device model (CDM) −500 +500 V machine model (MM) −200 +200 V General Electrosatic discharge (ESD) VESD TEA19051BTK Product data sheet electrostatic discharge voltage All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 21 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 10 Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Max Unit Voltages VVCC voltage on pin VCC 0 21 V VOPTO voltage on pin OPTO 0 21 V VCC1 voltage on pin CC1 0 5 V VCC2 voltage on pin CC2 0 5 V VDP voltage on pin DP 0 5 V VDM voltage on pin DM 0 5 V VSW voltage on pin SW 0 VCC + 6 V VDISCH voltage on pin DISCH 0 21 V VVSNS voltage on pin VSNS 0 2.5 V VISNS voltage on pin ISNS 0 3.3 V VGPIO1 voltage on pin GPIO1 0 3.3 V VGPIO2 voltage on pin GPIO2 0 3.3 V VSDA voltage on pin SDA 0 3.3 V VSCL voltage on pin SCL 0 3.3 V junction temperature −20 +105 °C General Tj 11 Thermal characteristics Table 8. Thermal characteristics TEA19051BTK Product data sheet Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient JEDEC test board 60 K/W Rth(j-c) thermal resistance from junction to case JEDEC test board 30 K/W All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 22 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 12 Characteristics Table 9. Characteristics Tamb = 25 °C; VCC = 5.0 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply (VCC pin) Vth(UVLO) undervoltage lockout threshold falling - 2.85 2.9 V ICC supply current unattached; VCC = 5 V - 1.8 - mA nominal; VCC = 5 V - 3 - mA extra discharge current; VCC = 1.05 × Vo(default) - 20 - mA discharge current of VCC during safe restart protection; depends on load conditions - 20 - mA protection level voltage - 1.05 × Vo(default) - V ICC(dch) Vos discharge supply current overshoot voltage CC1/CC2 section (CC1 and CC2 pins) Type C Ipu VIH VIL Vovp pull-up current HIGH-level input voltage current source for DFP pull-up indication default current −96 −80 −64 μA 1.5 A mode −194 −180 −166 μA 3 A mode −356 −330 −304 μA with standard 5.1 kΩ pull-down resistance default current 1.5 1.6 1.7 V 1.5 A mode 1.5 1.6 1.7 V 3 A mode 2.45 2.60 2.75 V LOW-level input voltage with standard 5.1 kΩ pull-down resistance overvoltage protection voltage default current 0.15 0.2 0.25 V 1.5 A mode 0.35 0.40 0.45 V 3 A mode 0.75 0.80 0.85 V CC1 and CC2 pins - 4.5 - V BMC bit rate 270 300 330 Kbps USB-PD normative specification fbit bit rate TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 23 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Symbol Parameter Conditions Min Typ Max Unit USB-PD transmitter normative specification tfall fall time 10 % and 90 % amplitude points; minimum is underloaded condition 300 - 650 ns trise rise time 10 % and 90 % amplitude points; minimum is underloaded condition 300 - 650 ns Vo output voltage signal voltage swing 1.05 1.125 1.2 V Zo output impedance transmitter - 45 - Ω USB-PD receiver normative specification Cin input capacitance receiver - 250 - pF |tfltr(lim) time constant limiting filter receiver bandwidth 100 - - ns zi input impedance receiver 10 - - MΩ Vi input voltage receiver comparator low level - 0.55 - V high level - 0.8 - V hysteresis - 250 - mV DM and DP pins - 4.5 - V - - 20 Ω high level 1.8 2.0 2.2 V low level 0.250 0.325 0.400 V pin DP 300 900 1500 kΩ pin DM 14.25 19.53 24.80 kΩ attach debounce time (BC1.2) 1 - 1.5 s DM low debounce time after BC1.2 is completed 1 - - ms signal detection debounce time 20 40 60 ms DP and DM pins Vovp overvoltage protection voltage Qualcomm® QuickCharge™ QC2.0 and QC3.0 Rsw switch resistance when DP and DM pins are shorted Vi input voltage DM and DP comparator pins Rpd td pull-down resistance delay time TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 24 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Symbol Parameter Conditions Min Typ Max Unit Voltage control (VSNS pin) Vref reference voltage input voltage range on the VSNS pin to control the voltage loop 0.3 - 2.4 V Vacc voltage accuracy voltage loop accuracy; VCC = 5 V −2 - +2 % measurement voltage accuracy −2 - +2 % gm transconductance VCC in; OPTO out 4 - - mA/mV Gmax maximum gain cable compensation - 8 - mV/mV 0 - 40 mV Current control (ISNS pin) Iref reference current parameter can be programmed in MTP 10 bits Iout output current current loop accuracy; Rsense = 5 mΩ 0.5 A < Iout < 5 A −100 - +100 mA Iout > 5 A −2 - +2 % measurement current accuracy; Rsense = 5 mΩ 0.5 A < Iout < 5 A −100 - +100 mA −3 - +3 % gain current; amplifier = 50 200 - gain current; amplifier = 25 100 - - mA/mV Iout > 5 A gm transconductance [1] mA/mV GPIO1 and GPIO2 pins IO(GPIOX) output current on pin GPIOX GPIO function = NTC (+OTP) low temperatures (see Figure 6) −15.75 −15.00 −14.25 μA medium temperatures (see Figure 6) −63 −60 −57 μA high temperatures (see Figure 6) −252 −240 −228 μA Tacc temperature accuracy 47 kΩ NTC (Beta = 4108) −5 - +5 °C Tres temperature resolution temperature measurement −1 - +1 °C VI input voltage high level 1.5 - - V low level - - 0.9 V high level; no load 2.7 3.0 3.3 V low level; no load - - 0.3 V VO output voltage TEA19051BTK Product data sheet GPIO function = supply All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 25 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Symbol Parameter Conditions Min Typ Max Unit IO output current GPIO function = supply source; VO = 2.3 V - - −1 mA sink; VO = 0.4 V 1 - - mA high level 2.1 - - V low level - - 0.9 V Vo(SCL/SDA) = 0.6 V 6 - - mA - 3 - V SDA and SCL pins VI input voltage IO output current Vpu pull-up voltage Rpu pull-up resistance for SDA and SCL - 1 - kΩ Vovp overvoltage protection voltage with control loop in voltage control mode 3 - 25 V Vovp(acc) overvoltage protection voltage accuracy VCC pin; Vovp = 6 V −3 - +3 % Vocp overcurrent protection voltage 6 - 40 mV Vocp(acc) overcurrent protection voltage accuracy −3 - +3 % Vuvp undervoltage protection voltage 3 - 21 V Vuvp(acc) undervoltage protection voltage accuracy −3 - +3 % ICC(dch) discharge supply current during safe restart protection - 20 - mA output resistance switch-on - 80 - kΩ switch-off - 600 - Ω - 3 - Ω Protections SW driver RO DISCH part (DISCH pin) Rdch discharge resistance Vdet(rst) reset detection voltage hard reset 0.65 0.70 0.75 V tact active time maximum on-time during attached state - 100 - ms OPTO pin IO(min) minimum output current - 30 - μA IO(max) maximum output current 3.75 5 6.25 mA - 10 - MHz Internal oscillator fosc internal oscillator frequency TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 26 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Symbol Parameter Conditions Min Typ Max Unit −10 - +10 °C Internal temperature protection Totp(acc) [1] overtemperature temperature protection trip accuracy regarding the trip level programmed in MTP The current sense pin can be used up to 40 mV. The result is a current range that depends on the programmed Rsense resistor. (e.g. with 10 mΩ, the value can be up to 4 A). TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 27 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 13 Application information VCC Vbus XV R2 DRAIN HV DRIVER n.c. ISENSE CTRL TEA193x S1 GATE TEA199x CAP R3 SOURCE AUX GND VCCH PROTECT VCCL GND R1 R7 R5 VCC R6 R4 C2 GND SGND DISCH GPIO1 CC1 ISNS TEA19051B CC2 C1 NTC1 (near connector) SW OPTO NTC2 (adapter) GPIO2 DP VSNS DM SCL SDA EDP aaa-025897 Figure 7. Typical application diagram, including TEA1938, TEA1999 (low-side SR), and TEA19051BTK 13.1 Resistor divider The resistor divider (R3 / (R2 + R3) connected from the VCC pin to the VSNS pin must reduce the output voltage to < 2.5 V for the maximum output voltage. See Section 8.2 for more information about the divider ratios. To minimize the voltage drop at the connector, the resistor divider must be connected as close as possible to the load switch. It is important that the external resistive divider exactly matches the internal value (MTP), because internal measurements depend on it. In the resistive divider, use resistors with a 1 % or better accuracy. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 28 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 13.2 Sense resistor The accuracy of the sense resistor R1 is very important. Any deviation from the value in MTP gives an offset in the current measurement. Because the sense resistor is very lowohmic, the layout of the connections in the PCB can give major deviations from its initial value. To overcome these deviations, several options are available: • Change the sense resistor value such that the complete value is matching the typical MTP value (5 mΩ or 10 mΩ). • Trim the value with a resistor divider so that the (R7 / (R5 + R7)) × (R1 + RPCB) matches the MTP default value. RPCB is the resistance of copper wires and the resistance change of the sense resistor due to its soldering profile. To maximize accuracy and temperature stability, keep Rpcb as low as possible. The sense resistor must have a temperature coefficient that is as low as possible. To prevent magnetic coupling, keep the length and the area of the connections between the sense resistor and the SGND and ISNS pins as small as possible. Connect the exposed die pad to the GND pin. Ensure that high currents flowing through the plane below the IC is prevented. 13.3 Voltage loop In the application diagram, an integrator network is connected between the VSNS pin and the optocoupler. The recommended values of these components are: • R2 = 160 kΩ to 180 kΩ • R4 = 1 kΩ • C1 = 10 nF; for the integral part To prevent magnetic coupling to these parts, which results in pollution in output voltage, the length and the area of the connection must be kept as small as possible. 13.4 Current loop For applications using the CC loop in the application, an integrator network is connected between the ISNS pin and the optocoupler. The recommended values for these components are: • R5 = 330 Ω when R1 = 10 mΩ; R5 = 160 Ω when R1 = 5 mΩ; connected between sense resistor and the ISNS pin for the proportional part. • R6 = 5 kΩ • C2 = 100 nF; for the integral part To prevent magnetic coupling to these parts, which results in pollution in output currents, the length and the area of the connection must be kept as small as possible. Resistor R6 and capacitor C2 can be removed in applications that use OCP mode. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 29 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 14 Package outline HVSON16: plastic thermal enhanced very thin small outline package; no leads; 16 terminals; body 3.5 x 5.5 x 0.85 mm SOT1308-1 X D B A A E A1 A3 detail X terminal 1 index area terminal 1 index area e1 e v w b 1 8 C C A B C y1 C y L E1 K 16 9 D1 0 3 Dimensions Unit A A1 max 1.00 0.05 nom 0.85 min 0.80 0.00 mm 6 mm scale A3 b D D1 E E1 0.2 0.35 0.32 0.29 5.6 5.5 5.4 3.75 3.70 3.65 3.6 3.5 3.4 e e1 1.85 1.80 0.65 4.55 1.75 k L v 0.2 0.55 0.50 0.45 0.1 w y 0.05 0.05 y1 0.1 sot1308-1_po Outline version SOT1308-1 References IEC JEDEC JEITA European projection Issue date 11-07-04 11-11-25 MO-229 Figure 8. Package outline SOT1308-1 (HVSON16) TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 30 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15 Appendix: Internal parameter settings per type In this section, the internal parameter settings per type are given. 15.1 TEA19051BAATK Table 10 gives an overview of the function settings in the TEA19051BAATK. Table 10. Internal parameter settings Function TEA19051BAATK power rating 27 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5V default maximum output current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function NTC with OTP GPIO2 protection level 90 °C chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 5.476 cable compensation 117 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level off QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 31 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAATK PDO3 PPS enable FALSE voltage 12 V current 2.25 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable TRUE maximum voltage 5.9 V minimum voltage 3.3 V maximum current 3A power limit enabled FALSE OVP level 125 % UVP level 90 % QC enable FALSE cable compensation enable FALSE PDO5 PPS enable [1] TEA19051BTK Product data sheet TRUE maximum voltage 11 V minimum voltage 3.3 V maximum current 3A power limit enabled TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 32 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.2 TEA19051BABTK Table 11 gives an overview of the function settings in the TEA19051BABTK. Table 11. Internal parameter settings Function TEA19051BABTK power rating 45 W [1] supported standards USB-PD3 ; QC2.0; QC3.0 default output voltage 5V default maximum output current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function NTC with OTP GPIO2 protection level 90 °C chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 8.325 cable compensation 100 mV/A CC mode or OCP OCP OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level off QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 33 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BABTK PDO3 PPS enable FALSE voltage 12 V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 3A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable [1] TEA19051BTK Product data sheet FALSE voltage 20 V current 2.25 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 34 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.3 TEA19051BACTK Table 12 gives an overview of the function settings in the TEA19051BACTK. Table 12. Internal parameter settings Function TEA19051BACTK power rating 65 W [1] supported standards USB-PD3 ; QC2.0; QC3.0 default output voltage 5V default maximum output current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function NTC with OTP GPIO2 protection level 90 °C chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 8.325 cable compensation 100 mV/A CC mode or OCP OCP OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level off QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 35 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BACTK PDO3 PPS enable FALSE voltage 12 V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 3A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable [1] TEA19051BTK Product data sheet FALSE voltage 20 V current 3.25 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 36 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.4 TEA19051BAFTK Table 13 gives an overview of the function settings in the TEA19051BAFTK. Table 13. Internal parameter settings Function TEA19051BAFTK power rating 18 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5.10 V default maximum output current GPIO1 function 3A NTC with OTP GPIO1 protection level 90 °C GPIO2 function disabled GPIO2 protection level - chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 5.476 cable compensation 88 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5.10 V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 2A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 37 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAFTK PDO3 PPS enable FALSE voltage 12 V current 1.50 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable TRUE maximum voltage 5.90 V minimum voltage 3.3 V maximum current 3A power limit enabled FALSE OVP level 125 % UVP level 90 % QC enable FALSE cable compensation enable FALSE PDO5 PPS enable TRUE maximum voltage 11 V minimum voltage 3.3 V maximum current 2A power limit enabled [1] TEA19051BTK Product data sheet TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 38 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.5 TEA19051BAGTK Table 14 gives an overview of the function settings in the TEA19051BAGTK. Table 14. Internal parameter settings Function TEA19051BAGTK power rating 27 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5V default maximum current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function disabled GPIO2 protection level - chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 8.325 cable compensation 111 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 39 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAGTK PDO3 PPS enable FALSE voltage 12 V current 2.25 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 1.80 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable FALSE voltage 20 V current 1.35 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO6 PPS enable [1] TEA19051BTK Product data sheet TRUE maximum voltage 11 V minimum voltage 3.3 V maximum current 3A power limit enabled TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 40 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.6 TEA19051BAHTK Table 15 gives an overview of the function settings in the TEA19051BAHTK. Table 15. Internal parameter settings Function TEA19051BAHTK power rating 30 W [1] supported standards QC2; QC3 default output voltage 5V default maximum current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function disabled GPIO2 protection level - chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 5.476 cable compensation 117 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 6V current 3A OVP level 125 % UVP level 60 % QC enable FALSE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 41 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAHTK PDO3 PPS enable FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 12 V maximum current 2.5 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO5 PPS enable TRUE maximum voltage 5.9 V minimum voltage 3.3 V maximum current 3A power limit enabled FALSE OVP level 125 % UVP level 90 % QC enable FALSE cable compensation enable FALSE PDO6 PPS enable [1] TEA19051BTK Product data sheet TRUE maximum voltage 11 V minimum voltage 3.3 V maximum current 3A power limit enabled TRUE OVP level 125 % UVP level 90 % QC enable FALSE cable compensation enable FALSE The TEA19051BAH is USB-PD3/QC4 compliant, but USB-PD3/QC4 certification is not possible. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 42 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.7 TEA19051BAKTK Table 16 gives an overview of the function settings in the TEA19051BAKTK. Table 16. Internal parameter settings Function TEA19051BAKTK power rating 30 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5V default maximum current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function disabled GPIO2 protection level - chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 8.325 cable compensation 111 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 43 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAKTK PDO3 PPS enable FALSE voltage 12 V current 2.50 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 2.00 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable FALSE voltage 20 V current 1.50 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO6 PPS enable TEA19051BTK Product data sheet TRUE maximum voltage 11 V minimum voltage 3.3 V maximum current 3A power limit enabled TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 44 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAKTK PDO7 PPS enable [1] TEA19051BTK Product data sheet TRUE maximum voltage 16 V minimum voltage 3.3 V maximum current 2A power limit enabled TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 45 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.8 TEA19051BAMTK Table 17 gives an overview of the function settings in the TEA19051BAMTK. Table 17. Internal parameter settings Function TEA19051BAMTK power rating 60 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5V default maximum output current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function NTC with OTP GPIO2 protection level 90 °C chip OTP trigger level 131 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 8.828 cable compensation 118 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 46 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAMTK PDO3 PPS enable FALSE voltage 12 V current 3.00 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 3.00 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable FALSE voltage 20 V current 3.00 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO6 PPS enable TEA19051BTK Product data sheet TRUE maximum voltage 16 V minimum voltage 3.3 V maximum current 3A power limit enabled FALSE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 47 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAMTK PDO7 PPS enable [1] TEA19051BTK Product data sheet TRUE maximum voltage 21 V minimum voltage 3.3 V maximum current 3A power limit enabled TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 48 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.9 TEA19051BAPTK Table 18 gives an overview of the function settings in the TEA19051BAPTK. Table 18. Internal parameter settings Function TEA19051BAPTK power rating 27 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5V default maximum output current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function disabled GPIO2 protection level - chip OTP trigger level 113 °C external sense resistor (Rsense) 10 mΩ external resistor divider VCC/VSNS (= DIV) 8.325 cable compensation 111 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 49 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BAPTK PDO3 PPS enable FALSE voltage 12 V current 2.25 A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 1.80 A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable TRUE maximum voltage 5.90 V minimum voltage 3.30 V maximum current 3.00 A power limit enabled FALSE OVP level 125 % UVP level 90 % QC enable FALSE cable compensation enable FALSE PDO6 PPS enable TEA19051BTK Product data sheet TRUE maximum voltage 11 V minimum voltage 3.3 V maximum current 3A power limit enabled TRUE OVP level 120 % UVP level 90 % All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 50 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function [1] TEA19051BTK Product data sheet TEA19051BAPTK QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 51 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 15.10 TEA19051BARTK Table 19 gives an overview of the function settings in the TEA19051BARTK. Table 19. Internal parameter settings Function TEA19051BARTK power rating 100 W [1] supported standards USB-PD3 ; QC4+ default output voltage 5V default maximum output current 3A GPIO1 function NTC with OTP GPIO1 protection level 90 °C GPIO2 function NTC with OTP GPIO2 protection level 90 °C chip OTP trigger level 113 °C external sense resistor (Rsense) 5 mΩ external resistor divider VCC/VSNS (= DIV) 8.828 cable compensation 106 mV/A CC mode or OCP CC mode OCP level/CC mode margin 5% PDO1 PPS enable FALSE voltage 5V current 3A OVP level 125 % UVP level OFF QC enable TRUE cable compensation enable TRUE PDO2 PPS enable TEA19051BTK Product data sheet FALSE voltage 9V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 52 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BARTK PDO3 PPS enable FALSE voltage 12 V current 3A OVP level 120 % UVP level 60 % QC enable TRUE cable compensation enable TRUE PDO4 PPS enable FALSE voltage 15 V current 3A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO5 PPS enable FALSE voltage 20 V current 5A OVP level 120 % UVP level 60 % QC enable FALSE cable compensation enable TRUE PDO6 PPS enable TEA19051BTK Product data sheet TRUE maximum voltage 16 V minimum voltage 3.3 V maximum current 3A power limit enabled FALSE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 53 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Function TEA19051BARTK PDO 7 PPS enable [1] TEA19051BTK Product data sheet TRUE maximum voltage 21 V minimum voltage 3.3 V maximum current 5A power limit enabled TRUE OVP level 120 % UVP level 90 % QC enable FALSE cable compensation enable FALSE To make USB-PD3 certification possible, the DP and DM pins of the IC must not be connected. To pass BC1.2, the DP and DM pins of the connector must be connected to each other. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 54 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 16 Abbreviations Table 20. Abbreviations TEA19051BTK Product data sheet Acronym Description AC alternating current APDO augmented PDO BMC bi-phase mark coding BOM bill of materials CC constant current CV constant voltage DC direct current DCM discontinuous conduction mode DFP downstream facing port DM data minus DP data plus EEPROM electrically erasable programmable read-only memory MTP multi-time programmable OCP overcurrent protection OGP open-ground protection OSP output short protection OSUP output supply protection OTP overtemperature protection OVP overvoltage protection PDO power data object PPS programmable power supply QR quasi-resonant RAM random-access memory ROM read-only memory RPDO regular PDO SCL serial clock line SDA serial data line SMPS switched-mode power supply UFP upstream facing port USB universal serial bus UVLO undervoltage lockout UVP undervoltage protection VDM vendor defined messages All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 55 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 17 References [1] Battery Charging Specification — Revision 1.2; including errata and ECNs through March 15, 2012; March 15, 2012 [2] USB Type-C Cable and Connector Specification — Revision 1.3; and ECNs; July 14, 2017 [3] USB Power Delivery Specification — Revision 2.0, version 1.3; January 12, 2017 [4] USB Power Delivery Specification — Revision 3.0, version 1.1; ECNs as of June 12, 2017; June 12, 2017 [5] Qualcomm® QuickCharge™ 2.0 Interface Specification — 80-NH008-1, revision AG; Qualcomm®, March 27, 2014 [6] Qualcomm® QuickCharge™ 3.0 Interface Specification — 80-NH008-2, revision K; Qualcomm®, August 1, 2017 [7] Qualcomm® QuickCharge™ 4 Interface Specification — 80-NH008-3, revision D; Qualcomm®, August 1, 2017 TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 56 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 18 Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA19051BTK v.3 20190121 Product data sheet - TEA19051BTK v.2 Modifications: • • • • TEA19051BTK v.2 20180827 Product data sheet - TEA19051BTK v.1 TEA19051BTK v.1 20180206 Product data sheet - - TEA19051BTK Product data sheet Section 4 "Ordering information" has been updated. Section 5 "Marking" has been updated. Section 15.9 "TEA19051BAPTK" has been added. Section 15.10 "TEA19051BARTK" has been added. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 57 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS 19 Legal information 19.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without TEA19051BTK Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 58 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities. Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP B.V. TEA19051BTK Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 21 January 2019 © NXP B.V. 2019. All rights reserved. 59 / 60 TEA19051BTK NXP Semiconductors USB-PD 2.0/USB-PD 3.0/QC 2.0/QC 3.0/QC 4 (+) controller for SMPS Contents 1 General description ............................................ 1 2 Features and benefits .........................................2 2.1 General .............................................................. 2 2.2 Protocol support ................................................ 2 2.3 Protections ......................................................... 3 3 Applications .........................................................3 4 Ordering information .......................................... 4 5 Marking .................................................................4 6 Block diagram ..................................................... 5 7 Pinning information ............................................ 6 7.1 Pinning ............................................................... 6 7.2 Pin description ................................................... 6 8 Functional description ........................................7 8.1 Start-up and supply ........................................... 8 8.2 Voltage loop .......................................................9 8.3 Current loop .....................................................11 8.4 Cable compensation ........................................ 12 8.5 Load switch ......................................................12 8.6 Discharge function ........................................... 12 8.7 Detach detection ..............................................13 8.8 Internal temperature measurement ..................13 8.9 GPIO pins ........................................................ 13 8.9.1 Off .................................................................... 13 8.9.2 NTC ..................................................................13 8.9.3 NTC + OTP ..................................................... 15 8.9.4 Supply .............................................................. 15 8.10 Communication ................................................ 15 8.10.1 USB Type-C .................................................... 15 8.10.2 USB-PD ........................................................... 16 8.10.3 Discover identification ......................................16 8.10.4 Battery charging .............................................. 16 8.10.5 Quick charge ................................................... 16 8.10.6 MTP configuration ............................................17 8.11 Protections ....................................................... 18 8.11.1 Protections overview ........................................18 8.11.2 Secondary side safe restart protection ............ 18 8.11.3 Undervoltage lockout (UVLO) ..........................18 8.11.4 Overvoltage protection (OVP) ..........................19 8.11.5 Overcurrent protection (OCP) ..........................19 8.11.6 Overtemperature protection (OTP) .................. 19 8.11.6.1 Internal OTP .................................................... 19 8.11.6.2 External OTP ................................................... 19 8.11.7 Open-ground protection (OGP) ....................... 19 8.11.8 Open-supply protection (OSUP) ...................... 19 8.11.9 Undervoltage protection (UVP) ........................19 8.11.10 Output short protection (OSP) ......................... 20 8.11.11 OVP DP and DM pins (OV_DP_DM) ...............20 8.11.12 OVP CC1 and CC2 pins (OV_CC1_CC2) ....... 20 8.11.13 Soft short protection CC pins (SHORT_ CC1_CC2) ....................................................... 20 9 Limiting values .................................................. 21 10 Recommended operating conditions .............. 22 11 Thermal characteristics ....................................22 12 13 13.1 13.2 13.3 13.4 14 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 16 17 18 19 Characteristics .................................................. 23 Application information .................................... 28 Resistor divider ................................................ 28 Sense resistor ..................................................29 Voltage loop .....................................................29 Current loop .....................................................29 Package outline .................................................30 Appendix: Internal parameter settings per type ..................................................................... 31 TEA19051BAATK ............................................ 31 TEA19051BABTK ............................................ 33 TEA19051BACTK ............................................ 35 TEA19051BAFTK ............................................ 37 TEA19051BAGTK ............................................39 TEA19051BAHTK ............................................ 41 TEA19051BAKTK ............................................ 43 TEA19051BAMTK ............................................46 TEA19051BAPTK ............................................ 49 TEA19051BARTK ............................................ 52 Abbreviations .................................................... 55 References ......................................................... 56 Revision history ................................................ 57 Legal information .............................................. 58 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2019. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 January 2019 Document identifier: TEA19051BTK