TEA1998TS/1X

TEA1998TS GreenChip synchronous rectifier controller Rev. 1 — 16 February 2017 1 Product data sheet COMPANY PUBLIC General description The TEA1998TS is a member of a new generation of Synchronous Rectifier (SR) controller ICs for switched mode power supplies with adaptive gate drive for maximum efficiency at any load. The TEA1998TS is a dedicated controller IC for synchronous rectification on the secondary side of flyback converters. It incorporates the sensing stage and driver stage for driving the SR MOSFET, which is rectifying the output of the secondary transformer winding. The TEA1998TS can generate its own supply voltage for battery charging applications with low output voltage or for applications with high-side rectification. The TEA1998TS is fabricated in a Silicon-On-Insulator (SOI) process. 2 Features and benefits 2.1 Efficiency features • Adaptive gate drive for maximum efficiency at any load • Typical supply current in no-load operation below 250 μA 2.2 Application features • • • • • • • Operates in an output voltage range between 10 V and 0 V Drain sense pin capable of handling input voltages up to 60 V Self-supplying for operation with low output voltage Self-supplying for high-side rectification without the use of an auxiliary winding Operates with standard and logic level SR MOSFETs Supports USB BC, QuickCharge and smart charging applications TSOP6 package 2.3 Control features • Adaptive gate drive for fast turn-off at the end of conduction • UnderVoltage LockOut (UVLO) with active gate pull-down TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 3 Applications The TEA1998TS is intended for flyback power supplies. In such applications, it can drive the external synchronous rectifier MOSFET, which replaces the diode for the rectification of the voltage on the secondary winding of the transformer. It can be used in all power supplies that require a high efficiency, like: • Chargers • Adapters • Flyback power supplies with very low and/or variable output voltage 4 Ordering information Table 1. Ordering information Type number TEA1998TS 5 Package Name Description Version TSOP6 plastic surface-mounted package; 6 leads SOT457 Marking Table 2. Marking codes TEA1998TS Product data sheet COMPANY PUBLIC Type number Marking code TEA1998TS/1 TEA1998 All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 2 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 6 Block diagram CAP XV V AND I REFERENCE Ich(CAP) UNDER VOLTAGE LOCKOUT ENERGY SAVE CONTROL TEA1998 LOGIC enable BLANKING turn-on TURN-ON on regulation off regulation SWITCH-OFF DRAIN -400 mV SOURCE GATE - -25 mV - -20 mV - +250 mV - GND aaa-022802 Figure 1. TEA1998TS block diagram TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 3 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 7 Pinning information 7.1 Pinning CAP 1 GND 2 XV 3 IC 6 DRAIN 5 SOURCE 4 GATE aaa-021171 Figure 2. TEA1998TS pin configuration (SOT457) 7.2 Pin description Table 3. Pin description TEA1998TS Product data sheet COMPANY PUBLIC Symbol Pin Description CAP 1 capacitor input for internal supply voltage GND 2 ground XV 3 external supply input GATE 4 gate driver output for SR MOSFET SOURCE 5 source sense input of SR MOSFET DRAIN 6 drain sense input of SR MOSFET All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 4 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 8 Functional description 8.1 Introduction The TEA1998TS is a controller IC for Synchronous Rectification (SR) in flyback applications. It can drive the external synchronous rectifier MOSFET for the rectification of the voltage on the secondary winding of the transformer. Figure 3 shows a typical configuration. SR low side VCC HV GND CTRL PROTECT 8 3 2 4 6 7 PRIMARY CONTROLLER 5 1 DRIVER S1 SECONDARY OPTO CONTROLLER ISENSE AUX XV VCC GND DRAIN GATE TEA1998 CAP SOURCE GATE aaa-022803 Figure 3. TEA1998TS configuration with low-side rectification 8.2 Start-up and UnderVoltage LockOut (UVLO; CAP and XV pins) The capacitor on the CAP pin supplies the TEA1998TS. When the XV voltage < 4.7 V, the capacitor is charged via the DRAIN pin. When the XV voltage ≥ 4.7 V, the capacitor is charged via the XV pin and an internal regulator. The regulator reduces the voltage difference between the XV and CAP pins to a level below 100 mV. When the voltage on the CAP pin exceeds Vstart(CAP) (3.7 V typical), the IC leaves the UVLO state and activates the synchronous rectifier circuitry. When the voltage drops below 3.6 V (typical), the UVLO state is reentered and the SR MOSFET gate driver output is actively kept low. 8.3 Drain sense (DRAIN pin) The drain sense pin is an input pin capable of handling input voltages up to 60 V. At positive drain sense voltages, the gate driver is in off-mode with the gate driver pulled down (pin GATE). At negative drain sense voltages, the IC enables the Synchronous Rectification (SR) by sensing the drain source differential voltage. TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 5 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 8.4 Synchronous rectification (DRAIN and SOURCE pins) The IC senses the voltage difference between the drain sense (DRAIN pin) and the source sense (SOURCE pin) connections. This drain source differential voltage of the SR MOSFET is used to drive the gate of the SR MOSFET. When this absolute voltage difference is higher than Vact(drv), the corresponding gate driver output turns on the external SR MOSFET. When the external SR MOSFET is switched on, the absolute voltage difference between the drain and the source sense connections drops to below Vact(drv). The regulation phase follows the turn-on phase. In the regulation phase, the IC regulates the difference between the drain and the source sense inputs to an absolute level of 25 mV. When the absolute difference exceeds 25 mV (Vreg(drv)), the gate driver output increases the gate voltage of the external SR MOSFET until the 25 mV level is reached. The SR MOSFET does not switch off at low current. To avoid that the device switches off because of ringing, a minimum on-time of 1.4 μs (ttact(sr) (min)) is integrated. When the absolute difference < 20 mV, the gate driver output decreases the gate voltage of the external SR MOSFET. The voltage waveform on the gate of the SR MOSFET follows the waveform of the current through the SR MOSFET. When the current through the SR MOSFET reaches zero, the SR MOSFET is switched off quickly. After SR MOSFET switch-off, the drain voltage increases. When the drain voltage exceeds 250 mV, a low ohmic gate pull-down of 3 Ω keeps the gate of the SR MOSFET switched off. 8.5 Gate driver (GATE pin) The gate driver circuit charges the gate of the external SR MOSFET during the rising part of the current. The driver circuit discharges the gate during the falling part of the current. The gate driver has a source capability of typically 0.70 A. It has a sink capability of typically 0.50 A. The source and sink capabilities allow fast turn-on and fast turn-off of the external SR MOSFET. The maximum output voltage of the driver is limited to the voltage on the CAP pin. The maximum output voltage ranges between 4.7 V and 10 V, depending on the voltage on the CAP pin. The high output gate voltage drives all MOSFET brands to the minimum onstate resistance. In applications where the IC is supplied with 5 V, the maximum output voltage of the driver is 4.90 V and logic level SR MOSFETs can be used. The IC is self-supplying in applications with high-side rectification or in battery charging applications with an output voltage < 4.7 V. When the XV pin is connected to ground for driving standard SR MOSFETs, the driver is regulated to 10 V. When the XV pin is connected to the converter output for driving logic-level SR MOSFETs, the driver is regulated to the voltage on the XV pin with a minimum of 4.7 V. TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 6 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller VCAP VG(MAX) 10 V 9V 4.7 V 0 1V 5V 10 V XV aaa-022804 Figure 4. Maximum gate voltage (VG(max)) During start-up conditions (VCAP < Vstart(CAP)) and UVLO, the driver output voltage is actively pulled low. 8.6 Source sense (SOURCE pin) The IC is equipped with an additional source sense pin (SOURCE). This pin is used for measuring the drain-to-source voltage of the external SR MOSFET. Voltage differences on PCB tracks because of parasitic inductance in combination with large dI/dt values, can cause errors. To minimize these errors, the source sense input must be connected as close as possible to the SOURCE pin of the external SR MOSFET. TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 7 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 9 Limiting values Table 4. Limiting values Symbol Parameter Conditions Min Max Unit Voltages VXV voltage on pin XV −0.4 +10.5 V Vsense(DRAIN) sense voltage on pin DRAIN −0.8 +60 V Vsense(SOURCE) sense voltage on pin SOURCE −0.4 +0.4 V - 300 mW General Ptot total power dissipation Tamb = 90 °C Tstg storage temperature −55 +150 °C Tj junction temperature −40 +150 °C - 2000 V - 500 V ElectroStatic Discharge (ESD) VESD electrostatic discharge voltage class 2 human body model charged device model [1] [1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. 10 Thermal characteristics Table 5. Thermal characteristics TEA1998TS Product data sheet COMPANY PUBLIC Symbol Parameter Rth(j-a) Rth(j-c) Conditions Typ Unit thermal resistance from junction to JEDEC test board ambient 200 K/W thermal resistance from junction to JEDEC test board case 115 K/W All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 8 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 11 Characteristics Table 6. Characteristics −25 °C < Tj < +125 °C; Vxv = 5 V; CCAP = 1 μF; CGATE = 10 nF (capacitor between the GATE and the GND pins); all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply voltage management (XV and CAP pins) Vstart(CAP) start voltage on pin CAP VXV = 0 V 3.5 3.7 3.9 V Vstop(CAP) stop voltage on pin CAP VXV = 0 V 3.4 3.6 3.8 V Ich(CAP) charge current on pin CAP power save operation VXV = 0 V; VCAP = 8 V; VDRAIN = 12 V; Tj = 25 °C −95 −80 −70 mA VXV = 2 V; VCAP = 4 V; VDRAIN = 12 V; Tj = 25 °C −150 −125 −100 mA VXV = 0 V; VDRAIN = 12 V 9.0 9.8 10.5 V VXV = 2 V; VDRAIN = 12 V 4.45 4.60 4.75 V VXV = 5 V 4.8 4.9 5.0 V VXV = 10 V 9.8 9.9 10.0 V power save operation; VXV = 5 V 190 210 240 μA normal operation; without gate charge; VXV = 5 V; Tj = 25 °C 1.0 1.2 1.4 mA 70 100 130 μs VI(CAP) II(XV) input voltage on pin CAP input current on pin XV tact(pwrsave) power-save activation time Synchronous rectification sense input (DRAIN and SOURCE pins) Vact(drv) driver activation voltage VSOURCE = 0 V - −400 - mV Vreg(drv) driver regulation voltage VSOURCE = 0 V; Tj = 25 °C −30 −25 −20 mV Vswoff switch-off voltage VSOURCE = 0 V 180 250 320 mV td(act)(drv) driver activation delay time VSOURCE = 0 V; normal operation; time for step-on VDRAIN (2 V to −0.5 V) to rising of VGATE at 10 % of end value - 40 - ns VSOURCE = 0 V; normal operation; time for step-on VDRAIN (−50 mV to 2 V) to falling of VGATE at 90 % of begin value - 40 - ns td(deact)(drv) driver deactivation delay time TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 9 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller Symbol Parameter Conditions tact(sr)(min) minimum synchronous rectification active time Min Typ Max Unit 1.2 1.4 1.7 ηs Gate driver (GATE pin) Isource source current peak.current; VXV = 5 V; Vds = −0.5 V; VG = 0 V - −0.70 - A Isink sink current regulation current; VXV = 5 V; Vds = 0 V; VG = 3 V - 100 - mA peak current; VXV = 5 V; Vds = 0.5 V; VG = 4 V - 0.50 - A Rpd(G) gate pull-down resistance VDRAIN = 0.5 V; IGATE = 100 mA; VXV = 5 V; Tj = 25 °C 2.6 3.2 4.0 Ω VG(max) maximum gate voltage VXV = 0 V 9.0 9.8 10.5 V VXV = 2 V 4.45 4.60 4.75 V VXV = 5 V 4.8 4.9 5.0 V VXV = 10 V 9.8 9.9 10.0 V 11.1 Temperature curves 11.1.1 Charge current (CAP pin) aaa-024173 0 Ich(CAP) (mA) -25 -50 -75 (1) -100 (2) -125 -150 -50 -25 0 25 50 75 100 125 T (°C) 150 Ich(CAP) at VCAP = 8 V; VXV = 0 V Ich(CAP) at VCAP = 4 V; VXV = 2 V Figure 5. Ich(CAP) as a function of temperature TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 10 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 11.1.2 Operating current (XV pin) aaa-024174 1600 II(XV) (µA) (1) 1200 800 400 (2) 0 -50 -25 0 25 50 75 100 125 T (°C) 150 II(XV) - normal operation II(XV) - power save operation Figure 6. II(XV) as a function of temperature 11.1.3 Driver regulation voltage aaa-024175 0 Vreg(drv) (mV) -10 -20 -30 -40 -50 -25 0 25 50 75 100 125 T (°C) 150 Figure 7. Vreg(drv) as a function of temperature TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 11 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 11.1.4 Gate pull-down resistance Rpd(G) (O) aaa-024176 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 T (°C) 150 Figure 8. Rpd(G) as a function of temperature TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 12 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 12 Application information A flyback switched mode power supply with the TEA1998TS consists of a primary side controller with a primary switch, a transformer, and an output stage. To obtain low conduction loss rectification, an SR MOSFET is used in the output stage. The SR MOSFET can be placed low-side (see Figure 3) or can be placed high-side (see Figure 9). In the high-side application, the TEA1998TS is self-supplying. The capacitor on the CAP pin supplies the TEA1998TS. When the drain voltage is positive, it is charged via the DRAIN pin. The gate drive voltage for the synchronous rectifier switch is derived from the voltage difference between the corresponding drain sense and source sense pins. Special attention must be paid to the connection of the drain sense and source sense pins. The voltages measured on these pins are used for the gate drive voltage. Wrong measurement results in a less efficient gate drive because a gate voltage that is either too low or too high. The connections to these pins must not interfere with the power wiring. The power wiring conducts currents with high dI/dt values. It can easily cause measurement errors resulting from induced voltages due to parasitic inductances. The separate source sense pins make it possible to sense the source voltage of the external MOSFETs directly, without having to use the current carrying power ground tracks. SR high side XV DRAIN GATE TEA1998 CAP SOURCE GND XV SECONDARY OPTO CONTROLLER HV GND CTRL PROTECT 8 2 6 7 3 PRIMARY CONTROLLER 4 5 1 DRIVER S1 GND ISENSE AUX VCC aaa-022805 Figure 9. TEA1998TS configuration with high-side rectification TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 13 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 13 Package outline Plastic surface-mounted package (TSOP6); 6 leads D SOT457 B E y A HE 6 5 X v M A 4 Q pin 1 index A A1 1 2 c 3 Lp e bp w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Figure 10. Package outline SOT457 (TSOP6) TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 14 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 14 Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes TEA1998TS 20170216 Product data sheet - - TEA1998TS Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 15 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller 15 Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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This document supersedes and replaces all information supplied prior to the publication hereof. TEA1998TS Product data sheet COMPANY PUBLIC Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 16 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own TEA1998TS Product data sheet COMPANY PUBLIC risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP Semiconductors N.V. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 February 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 17 / 18 TEA1998TS NXP Semiconductors GreenChip synchronous rectifier controller Contents 1 2 2.1 2.2 2.3 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 9 10 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 12 13 14 15 General description ............................................ 1 Features and benefits .........................................1 Efficiency features ............................................. 1 Application features ........................................... 1 Control features ................................................. 1 Applications .........................................................2 Ordering information .......................................... 2 Marking .................................................................2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 Introduction ........................................................ 5 Start-up and UnderVoltage LockOut (UVLO; CAP and XV pins) ............................................. 5 Drain sense (DRAIN pin) ...................................5 Synchronous rectification (DRAIN and SOURCE pins) .................................................. 6 Gate driver (GATE pin) ......................................6 Source sense (SOURCE pin) ............................ 7 Limiting values .................................................... 8 Thermal characteristics ......................................8 Characteristics .................................................... 9 Temperature curves .........................................10 Charge current (CAP pin) ................................10 Operating current (XV pin) .............................. 11 Driver regulation voltage ..................................11 Gate pull-down resistance ............................... 12 Application information .................................... 13 Package outline .................................................14 Revision history ................................................ 15 Legal information .............................................. 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP Semiconductors N.V. 2017. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 February 2017 Document identifier: TEA1998TS