TFA9879
Mono BTL class-D audio amplifier for portable applications
with digital input
Rev. 02 — 15 October 2010
Product data sheet
1. Introduction
The TFA9879 is a high-efficiency filter-free mono class-D audio amplifier with two
separate digital inputs for mobile applications.
2. General description
The TFA9879 contains a processor that supports a range of sound processing features
including a 5-band parametric equalizer, separate bass and treble control, a dynamic
range compressor, soft clip control and volume control. Excellent audio performance
combined with high Power Supply Rejection Ratio (PSRR) is achieved through the use of
a closed loop configuration.
Two independent digital audio inputs (I2S-bus / PCM / IOM2) are available for connecting
both a baseband and a multimedia processor.
The TFA9879 is available in a HVQFN24 package.
3. Features and benefits
3.1 General features
Closed loop amplifier for:
High power supply rejection ratio
Excellent audio performance
Digital input for high RF immunity
High efficiency for maximizing battery life
Wide supply voltage range (fully operational from 2.5 V to 5.5 V)
Delivers high output power into 4 Ω and 8 Ω load impedances
Phase-Locked Loop (PLL); no system clock required
Protection including diagnostics via I2C-bus:
OverCurrent Protection (OCP) to protect against short circuits across the speaker,
to the supply line or to ground
OverTemperature Protection (OTP)
Digital inputs protected with UnderFrequency Protection (UFP), OverFrequency
Protection (OFP) and Invalid Bit-clock Protection (IBP)
‘Pop noise’ free at power-up/power down, during sample rate switching and when
switching between digital inputs
Four separate I2C-bus addresses for multi-channel applications
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
1.8 V / 3.3 V tolerant digital inputs
Only three external components required
3.2 Programmable Digital Sound Processor (DSP)
Digital volume control (−70 dB to +24 dB)
Digital parametric 5-band equalizer
Bass and treble control (−18 dB to +18 dB)
Dynamic range compressor:
Programmable attack and release levels
Programmable attack and release rates
Soft and hard mute control
Programmable DC blocking via high-pass filter
Power limiter (0 dB to −124 dB in 0.5 dB steps)
Zero crossing volume control
Stereo-to-mono down-mix function
3.3 Interface format support for digital audio inputs
I2S formats (fs = 8 kHz to 96 kHz):
Philips standard I2S-bus
Japanese I2S-bus MSB-justified
Sony I2S-bus LSB-justified
PCM / IOM2 formats (fs = 8 kHz or fs = 16 kHz):
Long frame sync
Short frame sync
4. Applications
TFA9879
Product data sheet
Mobile phones
Portable Navigation Devices (PND)
PDAs
Notebooks
Portable gaming devices
MP3 and MP4 players
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
2 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
5. Quick reference data
Table 1.
Quick reference data
All parameters are guaranteed for VDDD = 1.8 V; VDDP = 3.7 V; RL = 8 Ω; LL = 44 μH; fi = 1 kHz; fs = 48 kHz; clip control off;
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
VDDP
power supply voltage
on pin VDDP
2.5
-
5.5
V
VDDD
digital supply voltage
on pin VDDD
1.65
1.8
1.95
V
IP
supply current
on pin VDDP; Amplifier mode with load; soft
mute on
-
5.7
-
mA
on pin VDDP; Power-down mode
-
-
20
μA
IDDD
digital supply current
on pin VDDD; Amplifier mode
-
1.2
-
mA
-
5
15
μA
THD + N = 1 %
0.65
0.7
-
W
THD + N = 10 %
-
0.85
-
W
THD + N = 1 %
-
1.2
-
W
THD + N = 10 %
-
1.5
-
W
THD + N = 1 %
-
0.9
-
W
THD + N = 10 %
-
1.1
-
W
THD + N = 1 %
-
1.6
-
W
THD + N = 10 %
-
1.95
-
W
on pin VDDD; Power-down mode
Po(RMS)
[1]
Typ
Max
Unit
RL = 8 Ω
RMS output power
RL = 4 Ω
RL = 8 Ω; VDDP = 4.2 V
RL = 4 Ω; VDDP = 4.2 V
RL = 8 Ω; VDDP = 5.0 V
THD + N = 1 %
-
1.35
-
W
THD + N = 10 %
-
1.6
-
W
-
2.35
-
W
RL = 4 Ω; VDDP = 5.0 V
THD + N = 1 %
ηpo
[1]
output power efficiency
THD + N = 10 %
-
2.75
-
W
Po(RMS) = 850 mW
-
92
-
%
After switching from Off/Amplifier mode to Power-down mode.
6. Ordering information
Table 2.
Ordering information
Type number
TFA9879HN
TFA9879
Product data sheet
Package
Name
Description
Version
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616_3
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
3 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
7. Block diagram
SDA
1
SCL
2
I2C
CONTROL
VDDD
n.c.
STABA
TEST1
TEST2
TEST3
23
6, 14
13
3
15
5
PROTECTION
CIRCUITS:
OCP
OTP
OFP
UFP
IBP
TFA9879
SDI1 20
SCK1 21
LRCK1 22
MUX
SDI2 17
DIGITAL
AUDIO
RECEIVER
SCK2 18
PLL
7, 8 VDDP
LRCK2 19
2nd
ORDER
LOOP
HIGH
PASS
FILTER
VOLUME
CONTROL
5
BAND
EQUALIZER
BASS
TREBLE
BOOST
POWER
LIMITER
PWM
10 OUTA
H-BRIDGE
DRC
DSP
2nd
ORDER
LOOP
9 OUTB
ADSEL1 16
11, 12 GNDP
ADSEL2 4
24
GNDD
Fig 1.
DAP
010aaa542
Block diagram
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
4 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
8. Pinning information
19 LRCK2
20 SDI1
21 SCK1
22 LRCK1
terminal 1
index area
23 VDDD
24 GNDD
8.1 Pinning
SDA
1
18 SCK2
SCL
2
17 SDI2
TEST1
3
ADSEL2
4
TEST3
5
n.c.
6
16 ADSEL1
TFA9879
15 TEST2
14 n.c.
GNDP 12
9
OUTB
GNDP 11
8
VDDP
13 STABA
OUTA 10
7
VDDP
DAP(1)
010aaa582
Transparent top view
(1) Exposed Die Attach Paddle (DAP)
Fig 2.
Pin configuration
8.2 Pin description
TFA9879
Product data sheet
Table 3.
Pin description
Symbol
Pin
Pin Type Description
SDA
1
IO
I2C-bus data input/output
SCL
2
I
I2C-bus bit clock input
TEST1
3
I
test signal input 1; for test purposes only; connect to PCB ground
ADSEL2
4
I
address selection input 2
TEST3
5
I
test signal input 3; for test purposes only; connect to PCB ground
n.c.
6
-
not connected; connect to PCB ground
VDDP
7, 8
P
analog supply voltage (2.5 V to 5.5 V)
OUTB
9
O
output B (negative)
OUTA
10
O
output A (positive)
GNDP
11, 12
P
analog ground, PCB ground reference
STABA
13
O
1.8 V analog stabilizer output
n.c
14
-
not connected; connect to PCB ground
TEST2
15
I
test signal input 2; for test purposes only; connect to PCB ground
ADSEL1
16
I
address selection input 1
SDI2
17
I
digital audio data input 2
SCK2
18
I
digital audio bit clock input 2
LRCK2
19
I
digital audio word select input 2
SDI1
20
I
digital audio data input 1
SCK1
21
I
digital audio bit clock input 1
LRCK1
22
I
digital audio word select input 1
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
5 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
Table 3.
Pin description …continued
Symbol
Pin
Pin Type Description
VDDD
23
P
digital supply voltage (1.8 V)
GNDD
24
P
digital ground, PCB ground reference
DAP
-
P
exposed Die Attached Paddle (DAP); connect to PCB ground
9. Functional description
The TFA9879 is a high-efficiency mono Bridge Tied Load (BTL) class-D amplifier with
digital audio inputs. It supports all commonly used formats.
The key functional blocks of the TFA9879 are shown in Figure 1. In the digital domain, the
audio signal is processed and converted into a Pulse Width Modulated (PWM) signal
using a 3-level modulation. In the analog domain, the PWM signal is amplified using a
second order feedback loop.
The audio signal-processing path is described below:
1. The MUX selects the serial interface input to be used.
2. The digital audio receiver translates the serial input signal into a standard internal
mono audio stream.
3. The programmable high-pass filter blocks DC signals and low frequency signals.
4. The volume control provides both gain and attenuation functionality and can be
adjusted by the user or dynamically via the Dynamic Range Compressor (DRC). The
volume control can be used to adjust the signal level between −70 dB and +24 dB.
5. The 5-band parametric equalizer can be used to equalize the mono audio stream. It
can be used for speaker transfer curve compensation to optimize the audio
performance of the speakers.
6. The bass and treble boost function provides another way to adjust the sound.
7. The power limiter limits the maximum output signal of the TFA9879. The power limiter
settings are 0 dB to −124 dB in steps of 0.5 dB. This function can be used to limit the
maximum output power delivered to the speakers at a fixed supply voltage and
speaker impedance.
8. The PWM controller block converts the audio signal into a 3-level modulated PWM
signal. The 3-level modulation provides a high signal-to-noise performance and
eliminates clock jitter noise.
9. The second order feedback loop ensures excellent audio performance and high
power supply rejection ratio.
10. The H-BRIDGE allows the TFA9879 to deliver the required output power between
terminals OUTA and OUTB.
The internal clocks of the TFA9879 are derived from the digital audio interface (SCK1 and
SCK2) using a PLL. The reference input for the PLL is selected via the digital input MUX.
The audio signal path can be selected via the I2C-bus interface.
The PLL block generates the system clock.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
6 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
The following protection circuits are built into the TFA9879:
•
•
•
•
•
•
OverTemperature Protection (OTP)
OverCurrent Protection (OCP)
UnderFrequency Protection (UFP)
OverFrequency Protection (OFP)
Invalid Bit-clock Protection (IBP)
DC-blocking
9.1 Operating modes
The TFA9879 supports the following operating modes, which are controlled via the
I2C-bus interface:
• Power-down mode, used to switch off the device; current consumption is reduced to
a minimum; the I2C-bus remains operational; the PWM outputs are disabled.
• Off mode, in which the class-D amplifier is switched off; the TFA9879 is completely
biased and the PWM outputs are disabled.
• Amplifier mode, in which the digital inputs are used to generate a signal between
OUTA and OUTB.
The TFA9879 device control settings are detailed in Table 21.
9.1.1 Power-up/power-down
The power-up and power-down timing of the TFA9879 is illustrated in Figure 3. The
external power supply levels, VDDP and VDDD, should be within the specified operating
ranges before the operating mode is selected. Bit POWERUP in the Device control
register (Table 21) must be set to 1 before the operating mode can be selected via bits
OPMODE. After the turn-on delay (td(on)), the device automatically generates a soft
un-mute function. A soft mute function is generated when OPMODE is set to 0. The
TFA9879 should be set to Power-down mode before the power supplies are disconnected
or turned off.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
7 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
VDDP, VDDD
I2C POWERUP
(00h, bit 0)
I2C OPMODE
(00h, bit 3)
serial interface
input signals
OUTA, OUTB
filtered BTL
output signal
td(on)
operating
td(mute_off)
td(soft_mute)
010aaa653
Fig 3.
Power-up/power-down timing
9.1.2 Supported Digital audio data formats
The TFA9879 supports a commonly used range of I2S, PCM and IOM2 digital audio data
formats. The I2S formats, selected via bits I2S_SET in the Serial interface control register
(Table 22), are listed in Table 4. The PCM/IOM2 formats are listed in Table 5. The
TFA9879 automatically detects the number of slots by measuring the ratio between the
sync frequency (8 kHz) and the data clock. Table 24 details the I2C settings for the
PCM/IOM2 formats.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
8 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
I2S-supported digital audio data formats
Table 4.
SCK frequency
Interface format (MSB first)
Supported data format
32 fs
I2S
up to 16-bit data
32 fs
MSB-justified
up to 16-bit data
32 fs
LSB-justified - 16 bits
16-bit data
64 fs
I2S (Philips) standard
up to 24-bit data
64 fs
MSB-justified
up to 24-bit data
64 fs
LSB-justified - 16 bits
16-bit data
64 fs
LSB-justified - 18 bits
18-bit data
64 fs
LSB-justified - 20 bits
20-bit data
64 fs
LSB-justified - 24 bits
24-bit data
RIGHT
LEFT
WS
1
2
(Philips) standard
3
2
3
MSB
B2
1
BCK
MSB
DATA
B2
MSB
I2S-BUS FORMAT
LEFT
WS
1
2
RIGHT
3
1
2
3
BCK
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT
RIGHT
16
15
2
1
16
B15 LSB
MSB
15
2
1
BCK
DATA
MSB
B2
B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
WS
LEFT
RIGHT
18
17
16
15
2
1
18
B17 LSB
MSB
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B2
B3
B4
B17 LSB
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
20
RIGHT
19
18
17
16
15
2
1
20
B19 LSB
MSB
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B2
B3
B4
B5
B6
B19 LSB
LSB-JUSTIFIED FORMAT 20 BITS
WS
LEFT
24
23
22
21
20
RIGHT
19
18
17
16
15
2
1
24
B23 LSB
MSB
23
22
21
20
19
18
17
16
15
2
1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
010aaa458
LSB-JUSTIFIED FORMAT 24 BITS
Fig 4.
I2S-supported digital audio data formats
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
9 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
Table 5.
PCM/IOM2-supported audio data formats
Number of slots
fs (kHz)
Sync frequency
(kHz) on LRCK
pin
Supported data
formats
Data clock (kHz)
on SCK pin
2
8 or 16
8
8-bit data
128
2
8 or 16
8
8-bit data
128
4
8 or 16
8
8-bit data
256
4
8 or 16
8
8-bit data
256
6
8 or 16
8
8-bit data
384
8
8 or 16
8
8-bit data
512
12
8 or 16
8
8-bit data
768
16
8 or 16
8
8-bit data
1024
2
8 or 16
8
16-bit data
256
3
8 or 16
8
16-bit data
384
4
8 or 16
8
16-bit data
512
6
8 or 16
8
16-bit data
768
8
8 or 16
8
16-bit data
1024
12
8 or 16
8
16-bit data
1536
12
8 or 16
8
16-bit data
1536
reserved
LRCK
SCK
SDI
MSB
B2
LSB
MSB
B2
Slot 0
LSB
MSB
B2
Slot 1
LSB
Slot 2
MSB
B2
Slot N − 1
LSB
Slot N
SHORT SYNC PCM/IOM2 FORMAT
LRCK
SCK
SDI
MSB
B2
LSB
Slot 0
MSB
B2
LSB
Slot 1
MSB
B2
LSB
Slot 2
Slot N − 1
LONG SYNC PCM/IOM2 FORMAT
Fig 5.
MSB
B2
LSB
Slot N
010aaa652
PCM/IOM2-supported digital audio data formats
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
10 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
9.2 Digital Signal Processor (DSP) features
9.2.1 Serial interface selection
The TFA9879 contains two serial interfaces. The active interface is selected via bit
INPUT_SEL in the Device control register (see Table 21). When this bit is toggled, the
following sequence is initiated:
• Soft mute is activated for 128/fs seconds
• The TFA9879 switches to Off mode and the serial interface input is toggled
• The TFA9879 switches back to Operating mode and soft mute is released
9.2.2 Mono selection
Mono selection is used to select the digital audio input channel to be amplified. The
options are:
• Left channel
• Right channel
• Left + right channels (sum divided by two)
Separate Mono selection is provided for the two serial interfaces via bits MONO_SEL in
the Serial interface control registers (addresses 01h and 03h; see Table 22).
9.2.3 Programmable high-pass filter
The TFA9879 features a first-order high-pass filter on the digital audio input to block DC
and low frequency signals. DC values at the output can damage the speaker.
The high-pass filter cut-off frequency is determined by:
• The high-pass filter control setting (bits HP_CTRL, see Table 30)
• The sample frequency, fs
The relationship between these parameters and the cut-off frequency is defined in
Equation 1:
f high ( –3dB )
4096 – HP_CTRL
– f s × ln ⎛⎝ ---------------------------------------------⎞⎠
4096
= ---------------------------------------------------------------------2π
(1)
HP_CTRL can be programmed to any integer value between 0 and 511 (see Table 30).
The high-pass filter is bypassed if HP_CTRL = 0 or bit HPF_BP in the Bypass control
register is set to 1 (see Table 27).
9.2.4 De-emphasis
Digital de-emphasis is sometimes needed, especially with older recordings. Emphasis
and de-emphasis originate in the FM transmission, in which the Signal-to-Noise Ratio
(SNR) is not flat over the signal band (in fact the SNR gets worse as the signal frequency
increases). To achieve good SNR over the complete audio band, the high frequency
components of the audio signal were amplified prior to transmission (this is called
Emphasis).
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
11 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
The de-emphasis filter is a simple first order filter. The cut-off frequency of the
de-emphasis low-pass filter is approximately 3.5 kHz. The TFA9879 de-emphasis filter is
supported for four sample frequencies, as detailed in Table 6.
Table 6.
De-emphasis control
[1:0] Control value[1]
fs (kHz)
00[2]
de-emphasis inactive
01
32
10
44.1
11
48
[1]
Value selected via bits DE_PHAS in the De-emphasis, soft/hard mute and power limiter control register
(see Table 32).
[2]
Default value.
9.2.5 Equalizer
The equalizer can be used for speaker curve compensation or for customer equalizer
settings, such as jazz, pop, rock or classical music. The equalizer function can be
bypassed or configured as 5-band.
9.2.5.1
Equalizer band function
The shape of each parametric equalizer band is determined by the following three filter
parameters:
• (Relative) center frequency ω = 2π ( fc ⁄ f s )
• Quality factor Q
• Gain factor G
In the above equation, fc is the center frequency and fs is the sample frequency.
The definition of the quality factor is the center frequency divided by the 3 dB bandwidth
(see Equation 2). In parametric equalizers this is only valid when the gain is set very low
(−30 dB).
f1 :
⎛ Af ⎞
20 log ⎜ -------1⎟
⎝ A f c⎠
10
= 3dB f c > f 1
f2 :
⎛ Af ⎞
20 log ⎜ -------2⎟
⎝ A f c⎠
10
= 3dB ,f 2 > f c
fc
Q = -------------- ;
f2 – f1
(2)
Each band filter can be programmed to perform a band-suppression (G < 1) or a
band-amplification (G > 1) function around the center frequency.
Each band of the TFA9879 equalizer has a second order Regalia-Mitra all-pass filter
structure. The structure is shown in Figure 6.
TFA9879
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 15 October 2010
© NXP B.V. 2010. All rights reserved.
12 of 60
TFA9879
NXP Semiconductors
Mono BTL class-D audio amplifier with digital input
+
½
+
Y(z)
+
X(z)
s
−
K0/2
A(z)
010aaa406
Fig 6.
Regalia-Mitra filter flow diagram
The transfer function of this all-pass filter is given in Equation 3:
H ( z ) = 1 ⁄ 2 ⋅ ( 1 + A ( z ) ) + K0 ⁄ 2 ⋅ ( 1 – A ( z ) )
(3)
A(z) is the second order filter structure. The transfer function of A(z) is given in
Equation 4:
–1
–2
K1 + K2 ⋅ ( 1 + K1 ) ⋅ Z + Z
A ( z ) = -----------------------------------------------------------------------------–1
–2
1 + K2 ⋅ ( 1 + K1 ) ⋅ Z + K1 ⋅ Z
(4)
Z−1 equals one fs delay period. The relationship between the programmable parameters
K0, K1 and K2 and the filter parameters G, ω and Q is shown in Equation 5 and Equation 6.
Equation 5 can be used to calculate band suppression (G < 1) functions.
K0 = G
K 1 = – cos ω
(5)
K 2 = ( 2Q ⋅ G – sin ω ) ⁄ ( 2Q ⋅ G + sin ω )
G 0
⎛0
t 1 = ⎜1
⎝
⎛0
t 2 = ⎜1
⎝
(7)
K2 ≥ 0
K2 < 0
A maximum of 12 dB amplification, with respect to the input signal, can be achieved per
equalizer stage. The equalizer band signals are processed in sequence, from the highest
(Band A) to the lowest (Band E). Each band can attenuate the signal by 6 dB so, in order
to prevent numerical clipping at filter settings of over 6 dB amplification, band filters can
be scaled by 0 dB or −6 dB. For optimum numerical noise performance, steps of −6 dB
amplification should be applied to the bands in sequence, starting with B and A, as long as
they are able to amplify the signal without clipping.
A filter scale factor, s, is associated with each of the equalizer bands and is set via the
relevant EQx_s control bit (see Table 25).
Table 7.
9.2.5.2
Equalizer filter scale factor settings
s
scale factor (dB)
0
0
1
−6
Equalizer band control
For compact representation with positive signed parameters, parameters k1’ and k2’ are
introduced in Equation 8.
k0 ′ = K0
⎛ 1 – K1
k1 ′ = ⎜
⎝ 1 + K1
t1 = 0
⎛ 1 – K2
k2′ = ⎜
⎝ 1 + K2
t2 = 0
t1 = 1
(8)
t2 = 1
Parameters K0, k1', k2', t1, t2 and s must be combined in two 16-bit control words, word1
and word2 (see Table 24 and Table 25), using the format shown in Table 8. Parameters k1'
and k2' are unsigned floating-point representations in Equation 8.
kx′ = M ⋅ 2
–E
(9)
M
