TJA1028
LIN transceiver with integrated voltage regulator
Rev. 5 — 30 January 2023
1
Product data sheet
General description
The TJA1028 is a LIN 2.0/2.1/SAE J2602 and ISO 17987-4:2016 (12 V) compliant
transceiver with an integrated low-drop voltage regulator. The voltage regulator can
deliver up to 70 mA and is available in 3.3 V and 5.0 V variants. TJA1028 facilitates
the development of compact nodes in Local Interconnect Network (LIN) bus systems.
To support robust designs, the TJA1028 offers strong ElectroStatic Discharge (ESD)
performance and can withstand high voltages on the LIN bus. In order to minimize
current consumption, the TJA1028 supports a Sleep mode in which the LIN transceiver
and the voltage regulator are powered down while still having wake-up capability via the
LIN bus.
The TJA1028 comes in an SO8 package, and also in a 3 mm × 3 mm HVSON8 package
that reduces the required board space by over 70 %. This feature can prove extremely
valuable when board space is limited.
2
Features and benefits
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LIN 2.0/2.1/2.2 compliant
SAE J2602 compliant
ISO 17987-4:2016 (12 V) compliant (TJA1028A/B/C/D)
Downward compatible with LIN 1.3
Internal LIN responder termination resistor
Voltage regulator offering 5 V or 3.3 V, 70 mA capability
2 % voltage regulator accuracy over specified temperature and supply ranges
Voltage regulator output undervoltage detection with reset output
Voltage regulator is short-circuit proof to ground
Voltage regulator stable with ceramic, tantalum and aluminum electrolyte capacitors
Robust ESD performance; ±8 kV according to IEC61000-4-2 for pins LIN and VBAT
Pins LIN and VBAT protected against transients in the automotive environment (ISO
7637)
Very low LIN bus leakage current of < 2 μA when battery not connected
LIN pin short-circuit proof to battery and ground
Transmit data (TXD) dominant time-out function
Thermally protected
Very low ElectroMagnetic Emission (EME)
High ElectroMagnetic Immunity (EMI)
Typical Standby mode current of 45 μA
Typical Sleep mode current of 12 μA
LIN bus wake-up function
K-line compatible
Available in SO8 and HVSON8 packages
TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
• Leadless HVSON8 package (3.0 mm × 3.0 mm) with improved Automated Optical
Inspection (AOI) capability
• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
3
Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VBAT
battery supply voltage
limiting value with respect to GND
-0.3
-
+40
V
IBAT
battery supply current
Standby mode; VLIN = VBAT
-
45
59
μA
Sleep mode; VLIN = VBAT
-
12
18
μA
Normal mode; bus recessive;
-
850
1800
μA
Normal mode; bus dominant;
-
2.0
4.5
mA
VLIN
voltage on pin LIN
limiting value with respect to GND
-40
-
+40
V
Tvj
virtual junction temperature
limiting value
-40
-
+150
°C
4
Ordering information
Table 2. Ordering information
Type number
Regulator Baud rate Package
TJA1028T/3V3/10
3.3 V
10.4 kBd
TJA1028T/3V3/20
3.3 V
20 kBd
TJA1028T/5V0/10
5V
10.4 kBd
TJA1028T/5V0/20
5V
20 kBd
TJA1028AT
3.3 V
10.4 kBd
TJA1028BT
3.3 V
20 kBd
TJA1028CT
5V
10.4 kBd
TJA1028DT
5V
20 kBd
TJA1028TK/3V3/10
3.3 V
10.4 kBd
TJA1028TK/3V3/20
3.3 V
20 kBd
TJA1028TK/5V0/10
5V
10.4 kBd
TJA1028TK/5V0/20
5V
20 kBd
TJA1028ATK
3.3 V
10.4 kBd
TJA1028BTK
3.3 V
20 kBd
TJA1028CTK
5V
10.4 kBd
TJA1028DTK
5V
20 kBd
TJA1028
Product data sheet
Name
Description
Version
SO8
small plastic outline package; 8 leads; body width
3.9 mm
SOT96-1
HVSON8 plastic thermal enhanced very thin small outline
SOT782-1
package; no leads; 8 terminals; body 3 × 3 × 0.85 mm
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
5
Block diagram
VBAT
VBAT
UV
DET
VOLTAGE
REFERENCE
VCC
VCC
UV
DET
VREG
OVERTEMP
DETECTION
EN
VCC
CONTROL
VBAT
RSTN
Rx
LIN
LIN
Tx
RXD
TXD
TIMEOUT
TIMER
VCC
TXD
TJA1028
GND
015aaa085
Figure 1. Block diagram
TJA1028
Product data sheet
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
6
Pinning information
6.1 Pinning
terminal 1
index area
VBAT
1
8
VCC
EN
2
7
RSTN
GND
3
6
TXD
LIN
4
5
RXD
VBAT 1
EN 2
7 RSTN
GND 3
6 TXD
LIN 4
5 RXD
Transparent top view
aaa-048706
aaa-048707
a. TJA1028xT: SO8
8 VCC
b. TJA1028xTK: HVSON8
Figure 2. Pin configuration diagrams
6.2 Pin description
Table 3. Pin description
Pin
Type
VBAT
1
P
battery supply for the TJA1028
EN
2
I
enable input
GND
3
G
ground
LIN
4
AIO
LIN bus line
RXD
5
O
LIN receive data output
TXD
6
I
LIN transmit data input
RSTN
7
I
reset output (active LOW)
VCC
8
P
voltage regulator output
[1]
[2]
7
[1]
Symbol
[2]
Description
I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.
HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must
be soldered to board ground. For enhanced thermal and electrical performance, it is recommended that the exposed
center pad also be soldered to board ground.
Functional description
The TJA1028 combines the functionality of a LIN transceiver and a voltage regulator in a
single chip and offers wake-up by bus activity. The voltage regulator is designed to power
the Electronic Control Unit (ECU) in the microcontroller and its peripherals.
The LIN transceiver is the interface between a LIN commander/responder protocol
controller and the physical bus in a LIN network. According to the Open System
Interconnect (OSI) model, these modules make up the LIN physical layer.
The TJA1028Tx/20, TJA1028Bx and TJA1028Dx variants are optimized for a
transmission speed of 20 kBd. The TJA1028Tx/10, TJA1028Ax and TJA1028Cx variants
are optimized for a transmission speed of 10.4 kBd. All variants achieve optimum
ElectroMagnetic Compatibility (EMC) performance by wave shaping the LIN output.
TJA1028
Product data sheet
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4 / 25
TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
7.1 LIN 2.x/SAE J2602 and ISO 17987-4:2016 (12 V) compliant
The TJA1028 is fully LIN 2.0, LIN 2.1, LIN 2.2, SAE J2602 and ISO 17987-4:2016 (12 V)
compliant. Since the LIN physical layer is independent of higher OSI model layers (e.g.
the LIN protocol), nodes containing an SO17987-4:2016 (12 V) compliant physical layer
can be combined, without restriction, with LIN physical layer nodes that comply with
earlier revisions (i.e. LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0, LIN 2.1, LIN 2.2 and LIN
2.2A).
7.2 Operating modes
The TJA1028 supports four operating modes: Normal, Standby, Sleep and Off. The
operating modes, and the transitions between modes, are illustrated in Figure 3.
AII states
VBAT < Vth(det)poff OR
Tvj > Tth(act)otp
remote
wake-up
OFF
LIN = off
RXD = VCC(2)
RSTN = LOW
VBAT > Vth(det)pon AND
Tvj < Tth(rel)otp
EN = 1 AND
RSTN = 1
STANDBY
LIN = off
(RXD signals
wake source)
EN = 1 0 AND
TXD = 1 AND
RSTN = 1
NORMAL(1)
LIN = on
EN = 1
0 AND(3)
EN = 1 TXD = 0 AND
RSTN = 1
wake-up(3)
event
SLEEP
LIN = off
RXD = VCC(2)
RSTN = LOW
Voltage regulator - on
Voltage regulator - off
015aaa086
1. In Normal mode, the LIN transmitter is enabled - but if EN and/or RSTN go LOW, the LIN
transmitter will be disabled. Remote wake-up signalling will be activated.
2. Until VCC drops below 2 V, else floating.
3. If a wake-up event and a go-to-sleep event occur simultaneously, the device will switch
directly to Standby mode without initiating a reset.
Figure 3. State diagram
7.2.1 Off mode
The TJA1028 switches to Off mode from all other modes if the battery supply voltage
drops below the power-off detection threshold (Vth(det)poff) or the junction temperature
exceeds the overtemperature protection activation threshold (Tth(act)otp).
The voltage regulator and the LIN physical layer are disabled in Off mode, and pin RSTN
is forced LOW.
TJA1028
Product data sheet
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
7.2.2 Standby mode
Standby mode is a low-power mode that guarantees very low current consumption.
The TJA1028 switches from Off mode to Standby mode as soon as the battery supply
voltage rises above the power-on detection threshold (VBAT > Vth(det)pon), provided the
junction temperature is below the overtemperature protection release threshold (Tvj <
Tth(rel)otp).
The TJA1028 switches to Standby mode from Normal mode during the mode select
window if TXD is HIGH and EN is LOW (see Section 7.2.5), provided RSTN = 1.
A remote wake-up event will trigger a transition to Standby mode from Sleep mode. The
remote wake-up event will be signalled by a continuous LOW level on pin RXD.
In Standby mode, the voltage regulator is on, the LIN physical layer is disabled and
remote wake-up detection is active. The wake-up source is indicated by the level on RXD
(LOW indicates a remote wake-up).
7.2.3 Normal mode
If the EN pin is pulled HIGH while the TJA1028 is in Standby mode (with RSTN = 1) or
Sleep mode, the device will enter Normal mode. The LIN physical layer and the voltage
regulator are enabled in Normal mode.
7.2.3.1 The LIN transceiver in Normal mode
The LIN transceiver is activated when the TJA1028 enters Normal mode.
In Normal mode, the transceiver can transmit and receive data via the LIN bus. The
receiver detects data streams on the LIN pin and transfers them to the microcontroller via
pin RXD. LIN recessive is represented by a HIGH level on RXD, LIN dominant by a LOW
level.
The transmit data streams of the protocol controller at the TXD input are converted by the
transmitter into bus signals with optimized slew rate and wave shaping to minimize EME.
A LOW level at the TXD input is converted to a LIN dominant level while a HIGH level is
converted to a LIN recessive level.
7.2.4 Sleep mode
Sleep mode features extremely low power consumption.
The TJA1028 switches to Sleep mode from Normal mode during the mode select window
if TXD and EN are both LOW (see Section 7.2.5), provided RSTN = 1.
The voltage regulator and the LIN physical layer are disabled in Sleep mode. Pin RSTN
is forced LOW. Remote wake-up detection is active.
7.2.5 Transition from Normal to Sleep or Standby mode
When EN is driven LOW in Normal mode, the TJA1028 disables the transmit path. The
mode select window opens tmsel(min) after EN goes LOW, and remains open until tmsel(max)
after EN goes LOW (see Figure 4).
The TXD pin is sampled in the mode select window. A transition to Standby mode is
triggered if TXD is HIGH, or to Sleep mode if TXD is LOW.
TJA1028
Product data sheet
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
To avoid complicated timing in the application, EN and TXD can be pulled LOW at the
same time without having any effect on the LIN bus. In order to ensure that the remote
wake-up time (twake(dom)LIN) is not reset on a transition to Sleep mode, TXD should be
pulled LOW at least td(EN-TXD) after EN goes LOW. This is guaranteed by design.
The user must ensure the appropriate level is present on pin TXD while the mode select
window is open.
EN
TXD
operating
mode
mode select window
Normal
Normal with TXD
path blocked
Sleep or Standby depending on
TXD level in mode select window
tmsel(min)
tmsel(max)
015aaa087
TXD is sampled during the mode select window. The TJA1028 switches to Standby (TXD HIGH)
or Sleep (TXD LOW) mode after sampling.
Figure 4. Transition from Normal to Sleep/Standby mode
7.3 Power supplies
7.3.1 Battery (pin VBAT)
The TJA1028 contains a single supply pin, VBAT. An external diode is needed in series to
protect the device against negative voltages. The operating range is from 4.5 V to 28 V.
The TJA1028 can handle voltages up to 40 V (max). If the voltage on pin VBAT falls below
Vth(det)poff, the TJA1028 switches to Off mode, shutting down the internal logic and the
voltage regulator and disabling the LIN transmitter. The TJA1028 exits Off mode as soon
as the voltage rises above Vth(det)pon, provided the junction temperature is below Tth(rel)otp.
7.3.2 Voltage regulator (pin VCC)
The TJA1028 contains a voltage regulator supplied via pin VBAT, which delivers up to 70
mA. It is designed to supply the microcontroller and its periphery via pin VCC.
7.3.3 Reset (pin RSTN)
The output voltage on pin VCC is monitored continuously and a system reset signal
is generated (pin RSTN goes LOW) if an undervoltage event is detected (VCC < Vuvd
for tdet(uv)(VCC)). Pin RSTN will go HIGH again once the voltage on VCC exceeds the
undervoltage recovery threshold (Vuvr) for trst.
TJA1028
Product data sheet
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
7.4 LIN transceiver
The transceiver is the interface between a LIN commander/responder protocol controller
and the physical bus in a LIN network. It is primarily intended for in-vehicle sub-networks
using baud rates from 2.4 kBd up to 20 kBd and is LIN 2.0/LIN 2.1/SAE J2602 compliant.
7.5 Remote wake-up
A remote wake-up is triggered by a falling edge on pin LIN, followed by LIN remaining
LOW for at least twake(dom)LIN, followed by a rising edge on pin LIN (see Figure 5).
LIN recessive
VBAT
VBUSrec
VLIN
VBUSdom
twake(dom)LIN
LIN dominant
Standby/Sleep mode
Sleep: VCC/Standby: HIGH
RXD
ground
Standby mode
LOW
015aaa088
Figure 5. Remote wake-up behavior
The remote wake-up request is communicated to the microcontroller in Standby mode by
a continuous LOW level on pin RXD.
Note that twake(dom)LIN is measured in Sleep and Standby modes, and in Normal mode if
TXD is HIGH.
7.6 Fail-safe features
7.6.1 General fail-safe features
The following general fail-safe features have been implemented:
• An internal pull-up towards VCC on pin TXD guarantees a recessive bus level if the pin
is left floating by a bad solder joint or floating microcontroller port pin.
• The current in the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin VBAT.
• A loss of power (pins VBAT and GND) has no impact on the bus line or on the
microcontroller. There will be no reverse currents from the bus.
• The LIN transmitter is automatically disabled when either EN or RSTN is LOW.
• After a transition to Normal mode, the LIN transmitter is only enabled if a recessive
level is present on pin TXD.
7.6.2 TXD dominant time-out function
A TXD dominant time-out timer circuit prevents the bus line being driven to a permanent
dominant state (blocking all network communications) if TXD is forced permanently LOW
by a hardware or software application failure. The timer is triggered by a negative edge
TJA1028
Product data sheet
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
on the TXD pin. If the pin remains LOW for longer than the TXD dominant time-out time
(tto(dom)TXD), the transmitter is disabled, driving the bus line to a recessive state. The timer
is reset by a positive edge on TXD.
7.6.3 Temperature protection
The temperature of the IC is monitored in Normal, Standby and Off modes. If the
temperature is too high (Tvj > Tth(act)otp), the TJA1028 will switch to Off mode (if in
Standby or Normal modes). The voltage regulator and the LIN transmitter will be
switched off and the RSTN pin driven LOW.
When the temperature falls below the overtemperature protection release threshold (Tvj <
Tth(rel)otp), the TJA1028 switches to Standby mode.
TJA1028
Product data sheet
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
8
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to ground.
Symbol
VBAT
Parameter
battery supply voltage
[1]
[1]
Vx
voltage on pin x
Conditions
Min
Max
Unit
DC; continuous
-0.3
+40
V
pin VCC
-0.3
+7
V
pins TXD, RXD, RSTN and EN
-0.3
VCC + 0.3
V
-40
+40
V
pulse 1
-100
-
V
pulse 2a
-
75
V
pulse 3a
-150
-
V
-
100
V
-8
+8
kV
DC value
pin LIN with respect to GND
Vtrt
transient voltage
on pin VBAT via reverse polarity diode/capacitor;
on pin LIN via 1 nF coupling capacitor
[2]
pulse 3b
VESD
electrostatic discharge
voltage
IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)
[3]
on pins LIN and VBAT
Human Body Model (HBM)
on any pin
[4]
-2
+2
kV
on pins LIN and VBAT
[5]
-8
+8
kV
[6]
-250
+250
V
-750
+750
V
Machine Model (MM); 200 pF, 0.75 μH, 10 Ω
on any pin
Charged Device Model (CDM)
[7]
on corner pins
on any other pin
Tvj
Tstg
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
-500
+500
V
virtual junction temperature
[8]
-40
+150
°C
storage temperature
[9]
-55
+150
°C
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
Verified by an external test house according to LIN Conformance Test Specification Package for LIN 2.1; parameters for standard pulses defined in
ISO 7637.
Verified by an external test house according to LIN Conformance Test Specification Package for LIN 2.1.
According to AEC-Q100-002.
Pins stressed to reference group containing all ground and supply pins, emulating the application circuit (xx). HBM pulse as specified in AEC-Q100-002
used.
According to AEC-Q100-003.
According to AEC-Q100-011.
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P × Rth(vj-a), where Rth(vj-a) is a fixed value to be
used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
Tstg in application according to IEC61360-4. For component transport and storage conditions, see instead IEC61760-2.
TJA1028
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
9
Thermal characteristics
Table 5. Thermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction to ambient
[1]
Typ
Unit
SO8 package; in free air
88
K/W
HVSON8 package; in free air
59
K/W
Rth(j-c)
thermal resistance from junction to case
HVSON8 package; in free air
21
K/W
Ѱj-top
thermal characterization parameter from junction
to top of package
SO8 package; in free air
17
K/W
HVSON8 package; in free air
10
K/W
[1]
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).
10 Static characteristics
Table 6. Static characteristics
VBAT = 5.5 V to 28 V; Tvj = -40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω ; typical values are given at VBAT = 12 V unless otherwise
[1]
specified; all voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Standby mode; VLIN = VBAT
-
45
59
μA
Sleep mode; VLIN = VBAT
-
12
18
μA
Normal mode; bus recessive;
VLIN = VBAT; VRXD = VCC; VRSTN = HIGH
-
850
1800
μA
Normal mode; bus dominant;
VBAT = 12 V; VTXD = 0 V; VRSTN = HIGH
-
2.0
4.5
mA
Supply; pin VBAT
IBAT
battery supply current
Vth(det)pon
power-on detection threshold
voltage
-
-
5.25
V
Vth(det)poff
power-off detection threshold
voltage
3
-
4.2
V
Vhys(det)pon
power-on detection hysteresis VBAT = 2 V to 28 V
voltage
50
-
-
mV
VCC(nom) = 5 V; IVCC = -70 mA to 0 mA
4.9
5
5.1
V
VCC(nom) = 3.3 V; VBAT = 4.5 V to 28 V;
IVCC = -70 mA to 0 mA
3.234
3.3
3.366
V
Supply; pin VCC
VCC
supply voltage
IOlim
output current limit
VCC = 0 V to 5.5 V
-250
-
-70
mA
Vuvd
undervoltage detection
voltage
VCC(nom) = 5 V
4.5
-
4.75
V
VCC(nom) = 3.3 V
2.97
-
3.135
V
undervoltage recovery
voltage
VCC(nom) = 5 V
4.6
-
4.9
V
VCC(nom) = 3.3 V
3.036
-
3.234
V
Vuvr
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TJA1028
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LIN transceiver with integrated voltage regulator
Table 6. Static characteristics...continued
VBAT = 5.5 V to 28 V; Tvj = -40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω ; typical values are given at VBAT = 12 V unless otherwise
[1]
specified; all voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
R(VBAT-VCC)
Co
Parameter
Conditions
resistance between pin VBAT
and pin VCC
output capacitance
Min
Typ
Max
Unit
Tvj = 85 °C
-
-
7
Ω
Tvj = 150 °C
-
-
9
Ω
1.8
10
-
μF
VCC(nom) = 5 V; VBAT = 4.5 V to 5.5 V;
IVCC = -70 mA to -5 mA;
regulator in saturation
equivalent series resistance < 5 Ω
[2]
[3]
[3]
LIN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
VCC = 2.97 V to 5.5 V
0.3 ×
VCC
-
0.7 ×
VCC
V
Vhys(i)
input hysteresis voltage
VCC = 2.97 V to 5.5 V
200
-
-
mV
Rpu
pull-up resistance
5
12
25
kΩ
LIN receive data output; pin RXD
IOH
HIGH-level output current
Normal mode;
VLIN = VBAT; VRXD = VCC - 0.4 V
-
-
-0.4
mA
IOL
LOW-level output current
Normal mode;
VLIN = GND; VRXD = 0.4 V
0.4
-
-
mA
Enable input; pin EN
Vth(sw)
switching threshold voltage
0.8
-
2
V
Rpd
pull-down resistance
50
130
400
kΩ
Reset output; pin RSTN
Rpu
pull-up resistance
VRSTN = VCC - 0.4 V;
VCC = 2.97 V to 5.5 V
3
-
12
kΩ
IOL
LOW-level output current
VRSTN = 0.4 V; VCC = 2.97 V to 5.5 V;
-40 °C < Tvj < 195 °C
3.2
-
40
mA
VOL
LOW-level output voltage
VCC = 2.5 V to 5.5 V;
-40 °C < Tvj < 195 °C
-
-
0.5
V
VOH
HIGH-level output voltage
-40 °C < Tvj < 195 °C
0.8 ×
VCC
-
VCC +
0.3
V
LIN bus line; pin LIN
IBUS_LIM
current limitation for driver
dominant state
VBAT = VLIN = 18 V; VTXD = 0 V
40
-
100
mA
IBUS_PAS_rec
receiver recessive input
leakage current
VLIN = 18 V; VBAT = 5.5 V; VTXD = VCC
-
-
2
μA
IBUS_PAS_dom
receiver dominant input
Normal mode;
leakage current including pull- VTXD = VCC; VLIN = 0 V; VBAT = 12 V
up resistor
-600
-
-
μA
IBUS_NO_GND
loss-of-ground bus current
VBAT = 18 V; VLIN = 0 V
-750
-
+10
μA
IBUS_NO_BAT
loss-of-battery bus current
VBAT = 0 V; VLIN = 18 V
-
-
2
μA
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
Table 6. Static characteristics...continued
VBAT = 5.5 V to 28 V; Tvj = -40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω ; typical values are given at VBAT = 12 V unless otherwise
[1]
specified; all voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VBUSrec
receiver recessive state
VBAT = 5.5 V to 18 V
0.6 ×
VBAT
-
-
V
VBUSdom
receiver dominant state
VBAT = 5.5 V to 18 V
-
-
0.4 ×
VBAT
V
VBUS_CNT
receiver center voltage
VBAT = 5.5 V to 18 V;
VBUS_CNT = (VBUSdom + VBUSrec) / 2
[4]
0.475 × 0.5 ×
VBAT
VBAT
0.525 V
× VBAT
VHYS
receiver hysteresis voltage
VBAT = 5.5 V to 18 V;
VHYS = VBUSrec - VBUSdom
[4]
0.05 ×
VBAT
0.15 ×
VBAT
0.175 V
× VBAT
VSerDiode
voltage drop at the serial
diode
in pull-up path with Rres; ISerDiode = 0.
9 mA
[3]
0.4
-
1.0
V
CLIN
capacitance on pin LIN
with respect to GND
[3]
-
-
30
pF
VO(dom)
dominant output voltage
Normal mode;
VTXD = 0 V; VBAT = 7 V
-
-
1.4
V
Normal mode;
VTXD = 0 V; VBAT = 18 V
-
-
2.0
V
between pin LIN and VBAT;
VLIN = 0 V; VBAT = 12 V
20
30
60
kΩ
Rres
responder resistance
Temperature protection
Tth(act)otp
overtemperature protection
activation threshold
temperature
165
180
195
°C
Tth(rel)otp
overtemperature protection
release threshold
temperature
126
138
150
°C
[1]
[2]
[3]
[4]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage range.
See Figure 1 and Figure 6.
Not tested in production; guaranteed by design.
See Figure 8.
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LIN transceiver with integrated voltage regulator
001aan953
7
R(VBAT-VCC)(typ)
(Ω)
6
5
4
3
2
-50
0
50
100
Tvj (°C)
150
Figure 6. Graph of R(VBAT-VCC)(typ) as a function of junction temperature (Tvj)
11 Dynamic characteristics
Table 7. Dynamic characteristics
VBAT = 5.5 V to 18 V; Tvj = -40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; typical values are given at VBAT = 12 V unless otherwise
[1]
specified; all voltages are defined with respect to ground.
Symbol
Parameter
Conditions
Min
duty cycle 1
Vth(rec)(max) = 0.744VBAT;
Vth(dom)(max) = 0.581VBAT;
tbit = 50 μs;
VBAT = 7 V to 18 V
[2]
Vth(rec)(max) = 0.76VBAT;
Vth(dom)(max) = 0.593VBAT;
tbit = 50 μs;
VBAT = 5.5 V to 7.0 V
[2]
Vth(rec)(min) = 0.422VBAT;
Vth(dom)(min) = 0.284VBAT;
tbit = 50 μs;
VBAT = 7.6 V to 18 V
[2]
Vth(rec)(min) = 0.41VBAT;
Vth(dom)(min) = 0.275VBAT;
tbit = 50 μs;
VBAT = 6.1 V to 7.6 V
[2]
Vth(rec)(max) = 0.778VBAT;
Vth(dom)(max) = 0.616VBAT;
tbit = 96 μs;
VBAT = 7 V to 18 V
[3]
Vth(rec)(max) = 0.797VBAT;
Vth(dom)(max) = 0.630VBAT;
tbit = 96 μs;
VBAT = 5.5 V to 7 V
[3]
Typ
Max
Unit
Duty cycles
δ1
δ2
δ3
duty cycle 2
duty cycle 3
TJA1028
Product data sheet
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Rev. 5 — 30 January 2023
[3]
0.396 -
-
0.396 -
-
-
-
0.581
-
-
0.581
[4]
[5]
[3]
[4]
[5]
[4]
[5]
[6]
[4]
[5]
[6]
[4]
0.417 -
-
0.417 -
-
[5]
[4]
[5]
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
Table 7. Dynamic characteristics...continued
VBAT = 5.5 V to 18 V; Tvj = -40 °C to +150 °C; RL(LIN-VBAT) = 500 Ω; typical values are given at VBAT = 12 V unless otherwise
[1]
specified; all voltages are defined with respect to ground.
Symbol
δ4
Parameter
Conditions
duty cycle 4
Vth(rec)(min) = 0.389VBAT;
Vth(dom)(min) = 0.251VBAT ;
tbit = 96 μs;
VBAT = 7.6 V to 18 V
[4]
Vth(rec)(min) = 0.378VBAT;
Vth(dom)(min) = 0.242VBAT;
tbit = 96 μs;
VBAT = 6.1 V to 7.6 V
[4]
[5]
Min
Typ
Max
-
-
0.590
-
-
0.590
Unit
[6]
[5]
[6]
Timing characteristics
trx_pd
receiver propagation delay
rising and falling;
CRXD = 20 pF
-
-
6
μs
trx_sym
receiver propagation delay symmetry
CRXD = 20 pF
-2
-
+2
μs
twake(dom)LIN
LIN dominant wake-up time
Sleep mode
30
80
150
μs
tto(dom)TXD
TXD dominant time-out time
VTXD = 0 V
6
-
20
ms
tmsel
mode select time
3
-
20
μs
0
-
1
μs
1
-
15
μs
2
-
8
ms
[7]
td(EN-TXD)
delay time from EN to TXD
tdet(uv)(VCC)
undervoltage detection time on pin VCC
CRSTN = 20 pF
Reset output; pin RSTN
trst
[1]
[2]
[3]
reset time
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage ranges.
Not applicable to the low slope versions (TJA1028T/xxx/10 and TJA1028TK/xxx/10) of the TJA1028.
. Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 8.
[4]
[5]
[6]
Bus load conditions are: CBUS = 1 nF and RBUS = 1 kΩ; CBUS = 6.8 nF and RBUS = 660 Ω; CBUS = 10 nF and RBUS = 500 Ω.
For VBAT > 18 V, the LIN transmitter might be suppressed. If TXD is HIGH then the LIN transmitter output is recessive.
[7]
Not tested in production; guaranteed by design.
. Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 8.
RXD
CRXD
TXD
VBAT
TJA1028
RLIN
LIN
GND
CLIN
015aaa198
Figure 7. Timing test circuit for LIN transceiver
TJA1028
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
tbit
tbit
tbit
VTXD
tbus(dom)(max)
tbus(rec)(min)
Vth(rec)(max)
VBAT
Vth(dom)(max)
LIN bus
signal
Vth(rec)(min)
Vth(dom)(min)
tbus(dom)(min)
output of receiving
node A
VRXD
output of receiving
node B
VRXD
thresholds of
receiving node A
thresholds of
receiving node B
tbus(rec)(max)
trx_pdf
trx_pdr
trx_pdr
trx_pdf
015aaa199
Figure 8. LIN transceiver timing diagram
12 Application information
The minimum external circuitry needed with the TJA1028 is shown in Figure 9. See the
Application Hints (Section 12.1) for further information about external components and
PCB layout
LIN BUS
LINE
VECU
VCC
VBAT
68 nF
10 µF
VDD
TXD
TX
RXD
RX
MICROCONTROLLER
Px.x
VSS
RSTN
22 µF
TJA1028
EN
RSTN
LIN
GND
220 pF
aaa-049769
Figure 9. Typical application of the TJA1028
TJA1028
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
12.1 Application hints
Further information on the application of the TJA1028 can be found in NXP application
hints AH1103 Application Hints TJA1028 LIN transceiver with integrated voltage
regulator.
13 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
TJA1028
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TJA1028
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LIN transceiver with integrated voltage regulator
14 Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
A2
Q
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
inches
0.010 0.057
0.069
0.004 0.049
0.05
0.244
0.039 0.028
0.041
0.228
0.016 0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Figure 10. Package outline SOT96-1 (SO8)
TJA1028
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TJA1028
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LIN transceiver with integrated voltage regulator
HVSON8: plastic thermal enhanced very thin small outline package; no leads;
8 terminals; body 3 x 3 x 0.85 mm
SOT782-1
X
B
D
A
E
A
A1
c
detail X
terminal 1
index area
e1
terminal 1
index area
e
1
4
C
C A B
C
v
w
b
y1 C
y
L
K
Eh
8
5
Dh
0
1
Dimensions
Unit(1)
mm
2 mm
scale
A
A1
b
max 1.00 0.05 0.35
nom 0.85 0.03 0.30
min 0.80 0.00 0.25
c
0.2
D
Dh
E
Eh
e
e1
K
L
3.10 2.45 3.10 1.65
0.35 0.45
3.00 2.40 3.00 1.60 0.65 1.95 0.30 0.40
2.90 2.35 2.90 1.55
0.25 0.35
v
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT782-1
---
MO-229
---
sot782-1_po
European
projection
Issue date
09-08-25
09-08-28
Figure 11. Package outline SOT782-1 (HVSON8)
TJA1028
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LIN transceiver with integrated voltage regulator
15 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with Table 8
and Table 9
Table 8. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 9. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
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TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17 Revision history
Table 10. Revision history
Document ID
Release date
Data sheet status
TJA1028 v.5
20230130
Product data sheet
Modifications:
•
•
•
•
•
•
•
•
•
•
•
•
TJA1028 v.4
20120725
Product data sheet
-
TJA1028 v.3
TJA1028 v.3
20110519
Product data sheet
-
TJA1028 v.2
TJA1028 v.2
20100225
Product data sheet
-
TJA1028 v.1
TJA1028 v.1
20100921
Product data sheet
-
-
TJA1028
Product data sheet
Change notice
Supersedes
TJA1028 v.4
Added variants TJA1028AT(K), TJA1028BT(K), TJA1028CT(K) and TJA1028DT(K)
'master/slave' replaced by 'commander/responder' throughout document
Section 2: added ISO 17987-4:2016 (12 V) compliance
Section 3: section added
Section 4 'Marking' removed
Table 3: added pin type column
Figure 5: amended text on RXD trace
Table 4: format and footnotes revised; no specification changes
Table 5: parameter definitions and specifications updated
Section 12: section added
Section 13: test informatin section removed
Section 18: legal information updated
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TJA1028
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LIN transceiver with integrated voltage regulator
18 Legal information
18.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1028
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 January 2023
© 2023 NXP B.V. All rights reserved.
23 / 25
TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
Suitability for use in automotive applications — This NXP product has
been qualified for use in automotive applications. If this product is used
by customer in the development of, or for incorporation into, products or
services (a) used in safety critical applications or (b) in which failure could
lead to death, personal injury, or severe physical or environmental damage
(such products and services hereinafter referred to as “Critical Applications”),
then customer makes the ultimate design decisions regarding its products
and is solely responsible for compliance with all legal, regulatory, safety,
and security related requirements concerning its products, regardless of
any information or support that may be provided by NXP. As such, customer
assumes all risk related to use of any products in Critical Applications and
NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any
claims, liabilities, damages and associated costs and expenses (including
attorneys’ fees) that NXP may incur related to customer’s incorporation of
any product in a Critical Application.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated and
English versions.
TJA1028
Product data sheet
Security — Customer understands that all NXP products may be subject to
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design
and operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
18.4 Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 January 2023
© 2023 NXP B.V. All rights reserved.
24 / 25
TJA1028
NXP Semiconductors
LIN transceiver with integrated voltage regulator
Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
General description ............................................ 1
Features and benefits .........................................1
Quick reference data .......................................... 2
Ordering information .......................................... 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 4
Functional description ........................................4
LIN 2.x/SAE J2602 and ISO 17987-4:2016
(12 V) compliant ................................................ 5
7.2
Operating modes ............................................... 5
7.2.1
Off mode ............................................................5
7.2.2
Standby mode ................................................... 6
7.2.3
Normal mode ..................................................... 6
7.2.3.1
The LIN transceiver in Normal mode ................. 6
7.2.4
Sleep mode ....................................................... 6
7.2.5
Transition from Normal to Sleep or Standby
mode .................................................................. 6
7.3
Power supplies .................................................. 7
7.3.1
Battery (pin VBAT) .............................................7
7.3.2
Voltage regulator (pin VCC) .............................. 7
7.3.3
Reset (pin RSTN) .............................................. 7
7.4
LIN transceiver .................................................. 8
7.5
Remote wake-up ............................................... 8
7.6
Fail-safe features ............................................... 8
7.6.1
General fail-safe features .................................. 8
7.6.2
TXD dominant time-out function ........................ 8
7.6.3
Temperature protection ......................................9
8
Limiting values .................................................. 10
9
Thermal characteristics ....................................11
10
Static characteristics ........................................ 11
11
Dynamic characteristics ...................................14
12
Application information .................................... 16
12.1
Application hints .............................................. 17
13
Quality information ........................................... 17
14
Package outline .................................................18
15
Handling information ........................................ 20
16
Soldering of SMD packages .............................20
16.1
Introduction to soldering .............................
16.2
Wave and reflow soldering .........................
16.3
Wave soldering ...........................................
16.4
Reflow soldering .........................................
17
Revision history ................................................ 22
18
Legal information .............................................. 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© 2023 NXP B.V.
All rights reserved.
For more information, please visit: http://www.nxp.com
Date of release: 30 January 2023
Document identifier: TJA1028