TJA1046V
Dual high-speed CAN transceiver with Standby mode
Rev. 1 — 2 March 2018
Product data sheet
1. General description
The TJA1046V is a dual high-speed CAN transceiver that provides two interfaces
between a Controller Area Network (CAN) protocol controller and the physical two-wire
CAN-bus. It is composed of two fully independent TJA1044V transceivers. The
transceivers are designed for high-speed CAN applications in the automotive industry,
providing the differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller. The TJA1046V guarantees robust communication at data rates up to
5 Mbit/s as used in, for example, CAN FD networks.
The TJA1046V offers a feature set optimized for 12 V automotive applications and
excellent ElectroMagnetic Compatibility (EMC) performance.
Additionally, the TJA1046V features:
• Ideal passive behavior to the CAN-bus when the supply voltage is off
• A very low-current Standby mode with bus wake-up capability
• Excellent EMC performance at speeds up to 500 kbit/s, even without a common mode
choke
The HVSON package allows for more than 70 % PCB space saving compared with
traditional SO packages. These features make the TJA1046V an excellent choice for
networks containing more than one HS-CAN interface requiring a low-power mode with
wake-up capability via the CAN-bus, especially for body and gateway control units.
The TJA1046V implements the CAN physical layer as defined in ISO 11898-2:2016 and
SAE J2284-1 to SAE J2284-5. Additional timing parameters defining loop delay symmetry
are specified. This implementation enables reliable communication in the CAN FD fast
phase at data rates up to 5 Mbit/s.
2. Features and benefits
2.1 General
Two fully independent TJA1044V HS-CAN transceivers combined in a single package
Fully ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant
Certified according to latest VeLIO (Vehicle LAN Interoperability and Optimization) test
requirements
Timing guaranteed for data rates up to 5 Mbit/s
Improved TXD to RXD propagation delay of 210 ns
Very low-current Standby mode with host and bus wake-up capability
Optimized for use in 12 V automotive systems
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
EMC performance satisfies 'Hardware Requirements for LIN, CAN and FlexRay
Interfaces in Automotive Applications’, Version 1.3, May 2012.
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
Can interface with 3.3 V and 5 V-supplied microcontrollers, provided the
microcontroller I/Os are 5 V tolerant.
AEC-Q100 qualified
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.2 Predictable and fail-safe behavior
Functional behavior predictable under all supply conditions
Transceivers disengage from bus when not powered (zero load)
Transmit Data (TXD) and bus dominant time-out functions
Internal biasing of TXDx and STBx input pins
2.3 Protection
High ESD handling capability on the bus pins (8 kV IEC and HBM)
Bus pins protected against transients in automotive environments
Undervoltage detection on VCCx pins
Thermally protected
3. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC
supply voltage
on pins VCC1 and VCC2
4.75
-
5.25
V
Vuvd(stb)
standby undervoltage detection
voltage
on pins VCC1 and VCC2
3.5
4
4.3
V
ICC
supply current
per transceiver:
Standby mode
-
10
15
A
Normal mode; bus recessive
2
5
10
mA
Normal mode; bus dominant
20
45
60
mA
VESD
electrostatic discharge voltage
IEC 61000-4-2 on pins CANH1, CANH2,
CANL1 and CANL2
8
-
+8
kV
VCANH
voltage on pin CANH
pins CANH1 and CANH2; limiting value
according to IEC60134
42
-
+42
V
VCANL
voltage on pin CANL
pins CANL1 and CANL2; limiting value
according to IEC60134
42
-
+42
V
Tvj
virtual junction temperature
40
-
+150
C
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
2 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
4. Ordering information
Table 2.
Ordering information
Type number
Package
TJA1046VTK
Name
Description
Version
HVSON14
plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 4.5 0.85 mm
SOT1086-2
5. Block diagram
9&&
9&&
7;'
5;'
6/23(
&21752/
$1'
'5,9(5
08;$1'
'5,9(5
5;'
&$1+
&$1/
02'(
&21752/
:$.(83
),/7(5
9&&
7(03(5$785(
3527(&7,21
6/23(
&21752/
$1'
'5,9(5
7,0(287
9&&
67%
7-$9
9&&
7,0(287
9&&
7;'
7(03(5$785(
3527(&7,21
9&&
67%
9&&
&$1+
&$1/
02'(
&21752/
08;$1'
'5,9(5
:$.(83
),/7(5
DDD
*1'
Fig 1.
*1'
Block diagram
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
3 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
6. Pinning information
6.1 Pinning
WHUPLQDO
LQGH[DUHD
7;'
67%
*1'
&$1+
9&&
&$1/
5;'
7;'
&$1+
*1'
&$1/
9&&
5;'
7-$9
67%
DDD
7UDQVSDUHQWWRSYLHZ
Fig 2.
Pin configuration diagram
6.2 Pin description
Table 3.
Pin
Description
TXD1
1
transmit data input 1
GND1[1]
2
transceiver ground 1
VCC1
3
transceiver supply voltage 1
RXD1
4
receive data output 1; reads out data from the bus lines 1
TXD2
5
transmit data input 2
GND2[1]
6
transceiver ground 2
VCC2
7
transceiver supply voltage 2
RXD2
8
receive data output 2; reads out data from the bus lines 2
CANL2
9
LOW-level CAN-bus line 2
CANH2
10
HIGH-level CAN-bus line 2
STB2
11
Standby mode control input 2
CANL1
12
LOW-level CAN-bus line 1
CANH1
13
HIGH-level CAN-bus line 1
STB1
14
Standby mode control input 1
[1]
TJA1046V
Product data sheet
Pin description
Symbol
HVSON14 package die supply ground is connected to both the GNDx pins and the exposed center pad.
The GNDx pins must be connected together externally in the application and soldered to board ground. For
enhanced thermal and electrical performance, it is recommended that the exposed center pad also be
soldered to board ground.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
4 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
7. Functional description
7.1 Operating modes
The TJA1046V supports two operating modes per transceiver, Normal and Standby. The
operating mode is selected independently for each transceiver via pins STB1 and STB2.
See Table 4 for a description of the operating modes under normal supply conditions.
Table 4.
Mode
Normal
Operating modes
Inputs
Outputs
Pin STB1/STB2 Pin TXD1/TXD2 CAN driver
Pin RXD1/RXD2
LOW
LOW
dominant
LOW
HIGH
recessive
LOW when bus dominant
x[1]
biased to ground follows BUS when wake-up
detected
HIGH when bus recessive
Standby HIGH
HIGH when no wake-up detected
[1]
‘x’ = don’t care
7.1.1 Normal mode
A LOW level on pin STBx selects Normal mode. In this mode, the enabled transceiver can
transmit and receive data via the bus lines CANHx and CANLx (see Figure 1 for the block
diagram). The differential receiver converts the analog data on the bus lines into digital
data which is output on pin RXDx. The slopes of the output signals on the bus lines are
controlled internally and are optimized in a way that guarantees the lowest possible EME.
7.1.2 Standby mode
A HIGH level on pin STBx selects Standby mode. In Standby mode, the enabled
transceiver cannot transmit or correctly receive data via the bus lines. The transmitter and
Normal-mode receiver blocks are switched off to reduce supply current, and only a
low-power differential receiver monitors the bus lines for activity.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied from VCCX and is able to detect CAN-bus
activity. Pin RXDx follows the bus after a wake-up request has been detected. A transition
to Normal mode is triggered when STBx is forced LOW.
7.2 Remote wake-up (via the CAN-bus)
The CAN transceivers contain separate wake-up circuits that operate independently of
each other. When a dedicated wake-up pattern (specified in ISO 11898-2: 2016) is
detected on the bus, the associated transceiver wakes up from Standby mode. This
filtering helps avoid spurious wake-up events. A spurious wake-up sequence could be
triggered by, for example, a dominant clamped bus or by dominant phases generated by
noise or spikes on the bus.
The wake-up pattern consists of:
• a dominant phase of at least twake(busdom) followed by
• a recessive phase of at least twake(busrec) followed by
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
5 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
• a dominant phase of at least twake(busdom)
Dominant or recessive bits inserted between these phases that are shorter than
twake(busdom) and twake(busrec), respectively, are ignored
The complete dominant-recessive-dominant pattern must be received within tto(wake)bus to
be recognized as a valid wake-up pattern (see Figure 3). Otherwise, the internal wake-up
logic is reset. The complete wake-up pattern will then need to be retransmitted to trigger a
wake-up event. Pin RXDx remains HIGH until the wake-up event has been triggered.
After a wake-up sequence has been detected, the transceiver will remain in Standby
mode with the bus signals reflected on RXDx. Note that dominant or recessive phases
lasting less than tfltr(wake)bus will not be detected by the low-power differential receiver and
will not be reflected on RXDx in Standby mode.
A wake-up event is not flagged on RXDx if any of the following events occurs while a valid
wake-up pattern is being received:
• The transceiver switches to Normal mode
• The complete wake-up pattern was not received within tto(wake)bus
• A VCC undervoltage is detected (VCC < Vuvd(stb); see Section 7.3.3)
If any of these events occur while a wake sequence is being received, the internal
wake-up logic is reset. The complete wake-up sequence will then need to be
retransmitted to trigger a wake-up event.
&$1+
92 GLI
&$1/
WZDNH EXVGRP
WZDNH EXVUHF
WZDNH EXVGRP
WIOWU ZDNH EXV
WIOWU ZDNH EXV
W WIOWU ZDNH EXV
WIOWU ZDNH EXV
W WIOWU ZDNH EXV
5;'
WWR ZDNH EXV
Fig 3.
DDD
Wake-up timing
7.3 Fail-safe features
7.3.1 TXD dominant time-out function
A 'TXD dominant time-out' timer is started when pin TXDx goes LOW. If the LOW state on
this pin persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXDx is set HIGH.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
6 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
The TXD dominant time-out time also defines the minimum possible bit rate of
approximately 25 kbit/s. Each of the transceivers in the TJA1046V has its own TXD
dominant time-out timer. The two timers operate independently of each other.
7.3.2 Internal biasing of TXDx and STBx input pins
Pins TXDx and STBx have internal pull-ups to VCCx to ensure a safe, defined state in case
they are left floating. Pull-up currents flow in these pins in all states; both pins should be
held HIGH in Standby mode to minimize supply current.
7.3.3 Undervoltage detection on pins VCCx
The TJA1046V features two fully independent supply voltages. If VCCx drops below the
standby undervoltage detection level, Vuvd(stb), the transceiver switches to Standby mode.
The logic state of pin STBx is ignored until VCCx has recovered. A LOW level on TXDx is
also ignored. This precaution prevents the bus being driven dominant while VCCx is
recovering. TXDx will continue to be ignored until a HIGH level (bus recessive) is
detected.
If VCCx drops below the switch-off undervoltage detection level, Vuvd(swoff), the transceiver
switches off and disengages from the bus (zero load; bus pins floating) until VCCx has
recovered.
Each of the transceivers in the TJA1046V has its own undervoltage protection circuit. The
two circuits operate independently of each other.
7.3.4 Overtemperature protection
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, Tj(sd), both output drivers are
disabled. When the virtual junction temperature drops below Tj(sd) again, the output
drivers recover independently once TXDx has been reset to HIGH. Including the TXDx
condition prevents output driver oscillation due to small variations in temperature. Each of
the transceivers in the TJA1046V has its own temperature protection circuit. The two
circuits operate independently of each other.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
7 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol
Parameter
voltage on pin
Vx
x[1]
Conditions
Min
Max
Unit
on pins CANH1, CANL1, CANH2, CANL2
42
+42
V
0.3
+7
V
0.3
VCC + 0.3
V
27
+27
V
pulse 1
100
-
V
pulse 2a
-
75
V
pulse 3a
150
-
V
-
100
V
8
+8
kV
on pins CANH1, CANL1, CANH2, CANL2
8
+8
kV
on any other pin
4
+4
kV
200
+200
V
750
+750
V
500
+500
V
40
+150
C
55
+150
C
on pins VCC1, VCC2
on any other pin
[2]
V(CANH-CANL) voltage between pin CANH
and pin CANL
Vtrt
transient voltage
on pins CANH1, CANL1, CANH2, CANL2
[3]
pulse 3b
VESD
IEC 61000-4-2 (150 pF, 330 )
electrostatic discharge
voltage
[4]
on pins CANH1, CANL1, CANH2, CANL2
Human Body Model (HBM); 100 pF, 1.5 k
Machine Model (MM); 200 pF, 0.75 H, 10
[5]
[6]
on any pin
Charged Device Model (CDM); field Induced
charge; 4 pF
[7]
on corner pins
on any other pin
Tvj
virtual junction temperature
Tstg
storage temperature
[8]
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2]
Maximum voltage should never exceed 7 V.
[3]
According to IEC TS 62228 (2007), Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2: 2004-06.
[4]
According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[5]
According to AEC-Q100-002.
[6]
According to AEC-Q100-003.
[7]
According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[8]
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(vj-a), where Rth(vj-a) is a
fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
8 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
9. Thermal characteristics
Table 6.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from junction to ambient
Value
Unit
dual-layer board
[1]
76
K/W
four-layer board
[2]
46
K/W
[1]
According to JEDEC JESD51-2, JESD51-3 and JESD51-5 at natural convection on 1s board with thermal via array under the exposed
pad connected to the second copper layer.
[2]
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer.
10. Static characteristics
Table 7.
Static characteristics
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; RL = 60 ; CL = 100 pF unless specified otherwise; All voltages are defined
with respect to ground. Positive currents flow into the IC.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pins VCC1 and VCC2
VCC
supply voltage
4.75
-
5.25
V
Vuvd(stb)
standby undervoltage
detection voltage
3.5
4
4.3
V
Vuvd(swoff)
switch-off undervoltage
detection voltage
1.3
2.4
3.4
V
ICC
supply current
-
10
15
A
per transceiver:
Standby mode; VTXDx = VCC
Normal mode; recessive; VTXDx = VCC
2
5
10
mA
Normal mode; dominant; VTXDx = 0 V
20
45
60
mA
Normal mode; dominant; VTXDx = 0 V;
short circuit on bus lines;
3 V VCANH = VCANL) +18 V
2
80
110
mA
Standby mode control input; pins STB1 and STB2
VIH
HIGH-level input voltage
2
-
VCC + 0.3 V
VIL
LOW-level input voltage
0.3
-
0.8
V
IIH
HIGH-level input current
per transceiver; VSTBx = VCC
1
-
+1
A
IIL
LOW-level input current
per transceiver; VSTBx = 0 V
15
-
1
A
2
-
VCC + 0.3 V
0.3
-
0.8
V
5
-
+5
A
260
150
70
A
-
5
10
pF
8
3
1
mA
CAN transmit data input; pins TXD1 and TXD2
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
IIH
HIGH-level input current
per transceiver; VTXDx = VCCx
IIL
LOW-level input current
per transceiver; VTXDx = 0 V
Ci
[2]
input capacitance
CAN receive data output; pins RXD1 and RXD2
IOH
HIGH-level output
current
TJA1046V
Product data sheet
per transceiver; VRXDx = VCCx 0.4 V
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
9 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
Table 7.
Static characteristics …continued
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; RL = 60 ; CL = 100 pF unless specified otherwise; All voltages are defined
with respect to ground. Positive currents flow into the IC.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOL
LOW-level output current per transceiver; VRXDx = 0.4 V; bus
dominant
1
-
12
mA
pin CANHx; RL = 50 to 65
2.75
3.5
4.5
V
pin CANLx; RL = 50 to 65
0.5
1.5
2.25
V
400
-
+400
mV
0.9VCC -
1.1VCC
V
RL = 50 to 65
1.5
-
3
V
RL = 45 to 70
1.4
-
3.3
V
RL = 2240
1.5
-
5
V
Bus lines; pins CANH1, CANL1, CANH2 and CANL2
VO(dom)
dominant output voltage
VTXDx = 0 V; t < tto(dom)TXD
Vdom(TX)sym
transmitter dominant
voltage symmetry
Vdom(TX)sym = VCCx VCANHx VCANLx
VTXsym
transmitter voltage
symmetry
VTXsym = VCANHx + VCANLx;
fTXD = 250 kHz, 1 MHz and 2.5 MHz;
CSPLIT = 4.7 nF
VO(dif)
[2]
[3]
differential output voltage dominant; Normal mode;
VTXDx = 0 V; t < tto(dom)TXD
recessive; no load
VO(rec)
Vth(RX)dif
Vrec(RX)
Vdom(RX)
recessive output voltage
differential receiver
threshold voltage
receiver recessive
voltage
receiver dominant
voltage
Normal mode: VTXDx = VCCx
50
-
+50
mV
Standby mode
0.2
-
+0.2
V
Normal mode; VTXDx = VCC; no load
2
0.5VCC 3
V
Standby mode; no load
0.1
-
+0.1
V
Normal mode
0.5
-
0.9
V
Standby mode
0.4
-
1.15
V
Normal mode
4
-
0.5
V
Standby mode
4
-
0.4
V
Normal mode
0.9
-
9.0
V
Standby mode
1.15
-
9.0
V
50
-
300
mV
12 V VCANLx +12 V;
12 V VCANHx +12 V
12 V VCANL +12 V;
12 V VCANH +12 V
12 V VCANL +12 V;
12 V VCANH +12 V
Vhys(RX)dif
differential receiver
hysteresis voltage
12 V VCANL +12 V;
12 V VCANH +12 V; Normal mode
IO(sc)dom
dominant short-circuit
output current
per transceiver; VTXDx = 0 V;
t < tto(dom)TXD; VCC = 5 V
IO(sc)rec
recessive short-circuit
output current
TJA1046V
Product data sheet
pin CANHx; VCANHx = 15 V to +40 V
100
70
40
mA
pin CANLx; VCANLx = 15 V to +40 V
40
70
100
mA
5
-
+5
mA
per transceiver; Normal mode;
VCANHx = VCANLx = 27 V to +32 V;
VTXDx = VCC;
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
10 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
Table 7.
Static characteristics …continued
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; RL = 60 ; CL = 100 pF unless specified otherwise; All voltages are defined
with respect to ground. Positive currents flow into the IC.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IL
leakage current
per transceiver; VCC = 0 V or VCC
shorted to GND via 47 k;
VCANHx = VCANLx = 5 V
5
-
+5
A
Ri
input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
[2]
9
15
28
k
Ri
input resistance
deviation
0 V VCANL +5 V;
0 V VCANH +5 V
[2]
3
-
+3
%
Ri(dif)
differential input
resistance
2 V VCANL +7 V;
2 V VCANH +7 V
[2]
19
30
52
k
Ci(cm)
common-mode input
capacitance
[2]
-
-
20
pF
Ci(dif)
differential input
capacitance
[2]
-
-
10
pF
[2]
-
185
-
C
Temperature detection
Tj(sd)
shutdown junction
temperature
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
Not tested in production; guaranteed by design.
[3]
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 8.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
11 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tvj = 40 C to +150 C; VCC = 4.75 V to 5.25 V; RL = 60 ; CL = 100 pF unless specified otherwise. All voltages are defined
with respect to ground. All values are specified per transceiver.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Transceiver timing; pins CANH1, CANH2, CANL1, CANL2, TXD1, TXD2, RXD1 and RXD2; see Figure 7 and Figure 4
td(TXD-busdom)
delay time from TXD to bus dominant
Normal mode
-
65
-
ns
td(TXD-busrec)
delay time from TXD to bus recessive
Normal mode
-
90
-
ns
td(busdom-RXD) delay time from bus dominant to RXD
Normal mode
-
60
-
ns
td(busrec-RXD)
delay time from bus recessive to RXD
Normal mode
-
65
-
ns
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
Normal mode
50
-
210
ns
[2]
-
-
300
ns
delay time from TXD HIGH to RXD
HIGH
Normal mode
50
-
210
ns
Normal mode; RL = 120 ;
CL = 200 pF
[2]
-
-
300
ns
transmitted recessive bit width
tbit(TXD) = 500 ns
[3]
435
-
530
ns
tbit(TXD) = 200 ns
[3]
155
-
210
ns
tbit(TXD) = 500 ns
[3]
400
-
550
ns
tbit(TXD) = 200 ns
[3]
120
-
220
ns
td(TXDH-RXDH)
tbit(bus)
tbit(RXD)
bit time on pin RXD
Normal mode; RL = 120 ;
CL = 200 pF
trec
receiver timing symmetry
tbit(TXD) = 500 ns
65
-
+40
ns
tbit(TXD) = 200 ns
45
-
+15
ns
tto(dom)TXD
TXD dominant time-out time
VTXDx = 0 V; Normal mode
0.8
3
6.5
ms
td(stb-norm)
standby to normal mode delay time
7
25
47
s
twake(busdom)
bus dominant wake-up time
Standby mode
0.5
-
3
s
twake(busrec)
bus recessive wake-up time
Standby mode
0.5
-
3
s
tto(wake)bus
bus wake-up time-out time
Standby mode
0.8
3
6.5
ms
tfltr(wake)bus
bus wake-up filter time
Standby mode
0.5
1
3
s
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
Not tested in production; guaranteed by design.
[3]
See Figure 5.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
12 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
+,*+
7;'
/2:
&$1+
&$1/
GRPLQDQW
9
92 GLI
9
UHFHVVLYH
+,*+
5;'
/2:
WG 7;'EXVGRP
WG 7;'EXVUHF
WG EXVGRP5;'
WG 7;'/5;'/
Fig 4.
WG EXVUHF5;'
WG 7;'+5;'+
DDD
CAN transceiver timing diagram
7;'[
[WELW 7;'
WELW 7;'
9
92 GLI
9
WELW EXV
5;'[
WELW 5;'
DDD
Fig 5.
TJA1046V
Product data sheet
CAN FD timing definitions according to ISO 11898-2:2016
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
13 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
12. Application information
12.1 Application diagram
9
%$7
9&&
9&&
&$1+
67%
67%
7;'
5;'
&$1/
7-$9
&$1+
7;'
5;'
3[[
9''
3\\
0,&52
7;
&21752//(5
5;
7;
5;
*1'
*1'
*1'
&$1/
DDD
(1) Optional, depends on regulator.
Fig 6.
Typical application with a 5 V microcontroller.
12.2 Application hints
Further information on the application of the TJA1046V can be found in NXP application
hints AH1308 ‘Application Hints - Standalone high speed CAN transceivers Mantis
TJA1044/TJA1057 and Dual-Mantis TJA1046’.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
14 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
13. Test information
9
)
Q)
9&&
9&&
&$1+
7;'
7;'
5/
ȍ
&/
S)
5/
ȍ
&/
S)
&$1/
5;'
7-$9
&$1+
S)
5;'
&$1/
S)
*1'
*1'
67%
67%
DDD
Fig 7.
CAN transceiver timing test circuit
9&&[
7;'[
&$1+[
ȍ
I N+]
0+]RU
0+]
7-$9
5;'[
&63/,7
Q)
ȍ
&$1/[
*1'[
DDD
Fig 8.
Test circuit for measuring transceiver driver symmetry
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
15 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
14. Package outline
+9621 SODVWLFWKHUPDOHQKDQFHGYHU\WKLQVPDOORXWOLQHSDFNDJH QROHDGV
WHUPLQDOV ERG\[[PP
627
;
%
'
$
$
(
$
F
WHUPLQDO
LQGH[DUHD
GHWDLO;
H
WHUPLQDO
LQGH[DUHD
H
Y
Z
E
&
& $ %
&
\ &
\
/
N
(K
'K
'LPHQVLRQV
8QLW
PP
PP
VFDOH
$
$
E
F
PD[
QRP
PLQ
'
'K
(
(K
H
H
N
/
Y
Z
\
\
VRW
Fig 9.
5HIHUHQFHV
2XWOLQH
YHUVLRQ
,(&
-('(&
-(,7$
627
02
(XURSHDQ
SURMHFWLRQ
,VVXHGDWH
Package outline SOT1086-2 (HVSON14)
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
16 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
17 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 10) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 10.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 10.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
18 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 10. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
19 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
17. Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 11.
ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)dom
Absolute current on CAN_L
ICAN_L
dominant short-circuit output
current
HS-PMA dominant output characteristics
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
VO(rec)
recessive output voltage
VDiff
VO(dif)
differential output voltage
tdom
tto(dom)TXD
TXD dominant time-out time
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
Differential output voltage
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
Dominant state differential input voltage range
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
Ri
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
HS-PMA implementation loop delay requirement
Loop delay
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
tRec
trec
receiver timing symmetry
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
20 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
Table 11.
ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
General maximum rating VCAN_H and VCAN_L
VCAN_H
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
tFilter
twake(busdom)[1] bus dominant wake-up time
HS-PMA bus biasing control timings
CAN activity filter time, long
twake(busrec)[1]
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
Timeout for bus inactivity
tSilence
tto(silence)
bus silence time-out time
Bus Bias reaction time
tBias
td(busact-bias)
delay time from bus active to bias
CAN activity filter time, short
Wake-up timeout, short
Wake-up timeout, long
[1]
tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
21 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
18. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1046V v.1
20180302
Product data sheet
-
-
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
22 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1046V
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
23 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Mantis — is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1046V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 2 March 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
24 of 25
TJA1046V
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
21. Contents
1
2
2.1
2.2
2.3
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
8
9
10
11
12
12.1
12.2
13
13.1
14
15
16
16.1
16.2
16.3
16.4
17
18
19
19.1
19.2
19.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Predictable and fail-safe behavior . . . . . . . . . . 2
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Remote wake-up (via the CAN-bus) . . . . . . . . . 5
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . . 6
TXD dominant time-out function . . . . . . . . . . . . 6
Internal biasing of TXDx and STBx input pins . 7
Undervoltage detection on pins VCCx . . . . . . . . 7
Overtemperature protection . . . . . . . . . . . . . . . 7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal characteristics . . . . . . . . . . . . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
Application information. . . . . . . . . . . . . . . . . . 14
Application diagram . . . . . . . . . . . . . . . . . . . . 14
Application hints . . . . . . . . . . . . . . . . . . . . . . . 14
Test information . . . . . . . . . . . . . . . . . . . . . . . . 15
Quality information . . . . . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Handling information. . . . . . . . . . . . . . . . . . . . 17
Soldering of SMD packages . . . . . . . . . . . . . . 17
Introduction to soldering . . . . . . . . . . . . . . . . . 17
Wave and reflow soldering . . . . . . . . . . . . . . . 17
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix: ISO 11898-2:2016 parameter
cross-reference list . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
19.4
20
21
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Contact information . . . . . . . . . . . . . . . . . . . . 24
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 March 2018
Document identifier: TJA1046V
工商网监
湘ICP备2023018690号
