TJA1081GTS/0Z

TJA1081G FlexRay node transceiver Rev. 1 — 28 October 2016 Product data sheet 1. General description The TJA1081G is a FlexRay transceiver that is fully compliant with FlexRay electrical physical layer specification ISO 17458-4:2013 (see Ref. 1 and Ref. 2). It is intended for communication systems from 2.5 Mbit/s to 10 Mbit/s and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1081G features enhanced low-power modes, optimized for ECUs that are permanently connected to the battery. The TJA1081G provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as effective ESD protection. The TJA1081G actively monitors system performance using dedicated error and status information (that any microcontroller can read), along with internal voltage and temperature monitoring. The TJA1081G supports mode control as used in the TJA1080A (see Ref. 3) and is fully functionally and pin compatible with the TJA1081B (see Ref. 4). 2. Features and benefits 2.1 Optimized for time triggered communication systems           Compliant with ISO 17458-4:2013 (see Ref. 2) Automotive product qualification in accordance with AEC-Q100 Data transfer rates from 2.5 Mbit/s to 10 Mbit/s Very low ElectroMagnetic Emissions (EME) to support unshielded cable, meeting latest industry standards Differential receiver with wide common-mode range for high ElectroMagnetic Immunity (EMI), meeting latest industry standards Enhanced EMC performance compared with TJA1081B Auto I/O level adaptation to host controller supply voltage VIO Can be used in 14 V, 24 V and 48 V powered systems Instant transmitter shut-down interface (via BGE pin) Independent power supply ramp-up for VBAT, VCC and VIO 2.2 Low-power management  Low-power management including inhibit switch  Very low current in Sleep and Standby modes TJA1081G NXP Semiconductors FlexRay node transceiver      VBAT operating range: 4.75 V to 60 V Gap-free specification Local and remote wake-up Supports remote wake-up via dedicated data frames Wake-up source recognition 2.3 Diagnosis (detection and signaling)       Enhanced supply monitoring of VBAT, VCC and VIO Overtemperature detection Short-circuit detection on bus lines VBAT power-on flag (first battery connection and cold start) Clamping diagnosis on pin TXEN BGE status feedback 2.4 Protection  Bus pins protected against 6 kV ESD pulses according to IEC 61000-4-2 and HBM  Pins VBAT and WAKE protected against 6 kV ESD pulses according to IEC 61000-4-2  Bus pins protected against transients in automotive environment (according to ISO 7637 class C)  Bus pins short-circuit proof to battery voltage (14 V, 24 V and 48 V) and ground  Fail-silent behavior in the event of an undervoltage on pins VBAT, VCC or VIO  Passive behavior of bus lines while the transceiver is not powered  No reverse currents from the digital input pins to VIO or VCC when the transceiver is not powered 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 2)     TJA1081G Product data sheet Bus driver voltage regulator control Bus driver - bus guardian interface Bus driver logic level adaptation Bus driver remote wake-up All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 2 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 3. Quick reference data Table 1. Quick reference data Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 4.75 - 5.25 V Vuvd(VCC) undervoltage detection voltage on pin VCC 4.45 - 4.72 V ICC supply current - 37 50 mA VBAT battery supply voltage 4.75 - 60 V Vuvd(VBAT) undervoltage detection voltage on pin VBAT 4.45 - 4.715 V IBAT battery supply current low-power modes; no load on pin INH - - 55 A normal-power modes - - 1 mA V Normal mode; VBGE = VIO; VTXEN = 0 V VIO supply voltage on pin VIO 2.8 - 5.25 Vuvd(VIO) undervoltage detection voltage on pin VIO 2.55 - 2.765 V IIO supply current on pin VIO Normal and Receive-only modes; VTXD = VIO - - 1 mA VESD electrostatic discharge voltage IEC 61000-4-2 on pins BP and BM to ground 6 - +6 kV 4. Ordering information Table 2. Ordering information Type number TJA1081GTS TJA1081G Product data sheet Package Name Description Version SSOP16 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 3 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 5. Block diagram 9,2 9&&  9%$7    ,1+ 7-$*  6,*1$/ 5287(5 75$16 0,77(5  %3 %0 9,2 7;' 7;(1 %*( 67%1 (1 5;' (551 5;(1   ,1387 92/7$*( $'$37$7,21       287387 92/7$*( $'$37$7,21 9%$7 :$.( %86 )$,/85( '(7(&7,21  5;',17 67$7( 0$&+,1( 5;',17 1250$/ 5(&(,9(5 29(5 7(03(5$785( '(7(&7,21 :$.(83 '(7(&7,21 26&,//$725 /2: 32:(5 5(&(,9(5 81'(592/7$*( '(7(&7,21  DDD *1' Fig 1. Block diagram TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 4 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 6. Pinning information 6.1 Pinning ,1+   9&& (1   %3 9,2   %0 7;'  7;(1  5;'   9%$7 %*(   (551 67%1  7-$*  *1'  :$.(  5;(1 DDD Fig 2. Pin configuration 6.2 Pin description Table 3. Symbol Pin Type[1] INH 1 AO inhibit output for switching external voltage regulator EN 2 I enable input; enabled when HIGH; internal pull-down VIO 3 P supply voltage for VIO voltage level adaptation TXD 4 I transmit data input; internal pull-down TXEN 5 I transmitter enable input; when HIGH transmitter disabled; internal pull-up RXD 6 O receive data output BGE 7 I bus guardian enable input; when LOW transmitter disabled; internal pull-down STBN 8 I standby input; low-power mode when LOW; internal pull-down RXEN 9 O receive data enable output; when LOW bus activity detected ERRN 10 O error diagnoses output; when LOW error detected Product data sheet Description VBAT 11 P battery supply voltage WAKE 12 AI local wake-up input; internal pull-up or pull-down (depends on voltage at pin WAKE) GND 13 G ground BM 14 AIO bus line minus BP 15 AIO bus line plus VCC 16 P supply voltage (+5 V) [1] TJA1081G Pin description AO: analog output; AI: analog input; I: digital input (VIO related); O: digital output (VIO related); I/O: digital input/output (VIO related); AIO: analog input/output; P: power supply; G: ground. All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 5 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7. Functional description The block diagram of the transceiver is shown in Figure 1. 7.1 Operating modes The TJA1081G supports the following operating modes: • • • • • • Normal (normal-power mode) Receive-only (normal-power mode) Standby (low-power mode) Go-to-sleep (low-power mode) Sleep (low-power mode) PowerOff 7.1.1 Bus activity and idle detection The following mechanisms for activity and idle detection are valid in normal power modes: • If the absolute differential voltage on the bus lines is higher than Vi(dif)det(act) for tdet(act)(bus), activity is detected on the bus lines. Pin RXEN is switched LOW, releasing pin RXD: – if, after activity has been detected on the bus, the differential voltage on the bus lines is lower than VIL(dif), pin RXD will go LOW – if, after activity has been detected on the bus, the differential voltage on the bus lines is higher than VIH(dif), pin RXD will go HIGH • If the absolute differential voltage on the bus lines is lower than Vi(dif)det(act) for tdet(idle)(bus), idle is detected on the bus lines. Pin RXEN is switched HIGH, blocking pin RXD (which is switched HIGH or remains HIGH) TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 6 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7.1.2 Signaling on pin ERRN Pin ERRN provides either error information or wake-up information. The behavior of ERRN is determined by the host (via pins STBN and EN) and not by the operating mode. If STBN is LOW, pin ERRN is configured to signal a wake-up event. When STBN and EN are both HIGH, pin ERRN is configured to provide an error alert. Signaling on pin ERRN is described in Table 4. If pin ERRN goes LOW in Standby mode or Sleep mode to signal a wake-up event, the host can switch the TJA1081G to Receive only mode (STBN  H) to determine if the wake-up is local or remote. A LOW level on ERRN in Receive only mode (provided the transition to Receive only mode was not triggered by EN going LOW in Normal mode) indicates a remote wake-up was detected. A HIGH level on ERRN signals a local wake-up. If EN had been forced HIGH after an earlier wake-up event (to switch the TJA1081G to Normal mode), ERRN will always indicate the error detection status (in both Normal and Receive only modes). Table 4. STBN Signaling on pin ERRN EN Conditions ERRN Normal mode active H H no error detected HIGH H H error detected LOW Receive only mode active H L a wake-up was detected (ERRN went LOW in Standby/Sleep mode; EN was LOW) before the TJA1081G was switched to Receive only mode H L local wake-up detected HIGH remote wake-up detected LOW EN was forced HIGH previously in response to an earlier wake-up event before the transition to Receive only mode no error detected HIGH error detected LOW Standby or Sleep modes active L X no local or remote wake-up detected HIGH L X local or remote wake-up detected LOW ERRN is in a high-impedance state in PowerOff mode. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 7 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7.1.3 Signaling on pins RXEN and RXD The TJA1081G operating mode determines signaling on pins RXEN and RXD, as detailed in Table 5. Table 5. RXEN and RXD signaling Operating mode RXEN LOW HIGH RXD LOW HIGH Transmitter INH Normal bus active bus idle DATA_0 DATA_1 or idle Receive-only Go-to-Sleep Standby enabled disabled local or remote wake-up detected[1] no local or remote local or remote no local or remote wake-up detected wake-up detected[1] wake-up detected Sleep PowerOff [1] HIGH floating high impedance HIGH Valid if VIO and (VCC or VBAT) are present. TXD BGE TXEN BP BM RXEN RXD 015aaa342 Fig 3. Timing diagram in Normal mode TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 8 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7.1.4 Operating mode transitions State transitions are summarized in the state transition diagram in Figure 4 and detailed in Table 6 to Table 9. Numbers are used to represent the state transitions. The numbers in the diagram correspond to the numbers in the third column in the tables. 1 RECEIVE ONLY NORMAL STBN = HIGH EN = LOW STBN = HIGH EN = HIGH 4 3, 31 15, 26, 44, 45 8, 18, 41 5 6, 34 10, 21 32, 33 11, 22 2 14, 25, 42, 43 7, 17, 40 29, 30 12, 23 20 STANDBY(1) GO-TO-SLEEP STBN = LOW EN = LOW STBN = LOW EN = HIGH 24 9, 19 37, 38 13, 35, 36 16, 27, 46, 47 28, 48, 49 50 SLEEP STBN = LOW EN = X POWEROFF 39 from any mode 015aaa275 Fig 4. State diagram TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 9 of 46 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081G Product data sheet Table 6. State transitions forced by EN and STBN  indicates the action that initiates a transaction; 1 and 2  indicated the consequences of a transaction. Transition from mode Direction to mode Normal Rev. 1 — 28 October 2016 All information provided in this document is subject to legal disclaimers. Sleep Flag Notes EN UVVIO UVVBAT UVVCC PWON Wake Receive-only 1 H L cleared cleared cleared cleared X Go-to-sleep L H cleared cleared cleared cleared X 2 3 L L cleared cleared cleared cleared X 4 H H cleared cleared cleared X X Go-to-sleep 5 L H cleared cleared cleared X X Standby 6 L L cleared cleared cleared X X Normal Standby Go-to-sleep Pin STBN Receive-only Normal Standby Transition number 7 H H cleared cleared cleared X X Receive-only 8 H L cleared cleared cleared X X Go-to-sleep 9 L H cleared cleared X X X Normal 10 H H cleared cleared cleared X X [1] Receive-only 11 H L cleared cleared cleared X X [1] Standby 12 L L cleared cleared X X X [1] Sleep 13 L H cleared cleared X X cleared [2] Normal 14 H H cleared cleared cleared X X Receive-only 15 H L cleared cleared cleared X X Standby H X cleared cleared X X X 16 [1] Hold time of go-to-sleep is less than th(gotosleep). [2] Hold time of go-to-sleep becomes greater than th(gotosleep). [3] Transition to a non-low-power mode is blocked when the voltage on pin VCC is below Vuvd(VCC) for longer than tdet(uv)(VCC). [3] TJA1081G FlexRay node transceiver 10 of 46 © NXP Semiconductors N.V. 2016. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081G Product data sheet Table 7. State transitions forced by a wake-up  indicates the action that initiates a transaction; 1 and 2  indicated the consequences of a transaction. Transition from mode Direction to mode Transition number Pin STBN EN UVVIO UVVBAT UVVCC PWON Wake Standby Normal 17 H H cleared cleared 1  cleared X  set [1] Receive-only 18 H L cleared cleared 1  cleared X  set [1] Go-to-sleep 19 L H cleared cleared 1  cleared X  set [1] Standby 20 L L cleared cleared 1  cleared X  set [1] Normal 21 H H cleared cleared 1  cleared X  set [1] Receive-only 22 H L cleared cleared 1  cleared X  set [1] Standby 23 L L cleared cleared 1  cleared X  set [1] Go-to-sleep 24 L H cleared cleared 1  cleared X  set [1] Go-to-sleep Rev. 1 — 28 October 2016 All information provided in this document is subject to legal disclaimers. Sleep Flag Note Normal 25 H H 1  cleared 1  cleared 1  cleared X  set [1][2] Receive-only 26 H L 1  cleared 1  cleared 1  cleared X  set [1][2] Standby 27 L L 1  cleared 1  cleared 1  cleared X  set [1] Go-to-sleep 28 L H 1  cleared 1  cleared 1  cleared X  set [1][2] [1] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. [2] Transition via Standby mode. TJA1081G FlexRay node transceiver 11 of 46 © NXP Semiconductors N.V. 2016. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081G Product data sheet Table 8. State transitions forced by an undervoltage condition  indicates the action that initiates a transaction; 1 and 2  indicated the consequences of a transaction. Transition from mode Direction to mode Transition number Flag UVVIO UVVBAT UVVCC PWON Wake Normal Sleep 29  set cleared cleared cleared 1  cleared [1] Sleep 30 cleared  set cleared cleared 1  cleared [1] Standby 31 cleared cleared  set cleared 1  cleared [1][2] Sleep 32  set cleared cleared X 1  cleared [1] Sleep 33 cleared  set cleared X 1  cleared [1] Standby 34 cleared cleared  set X 1  cleared [1][2] Sleep 35  set cleared cleared X 1  cleared [1] Sleep 36 cleared  set cleared X 1  cleared [1] Sleep 37  set cleared X X 1  cleared [1][3] Sleep 38 cleared  set X X 1  cleared [1][4] PowerOff 39 X X X X X Receive-only Go-to-sleep Rev. 1 — 28 October 2016 All information provided in this document is subject to legal disclaimers. Standby X Note [1] UVVIO, UVVBAT or UVVCC detected clears the wake flag. [2] Transition already completed when the voltage on pin VCC is below Vuvd(VCC) for longer than tdet(uv)(VCC). [3] UVVIO overrules UVVCC. [4] UVVBAT overrules UVVCC. [5] VDIG (the internal digital supply voltage to the state machine) < Vth(det)POR. [5] TJA1081G FlexRay node transceiver 12 of 46 © NXP Semiconductors N.V. 2016. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1081G Product data sheet Table 9. State transitions forced by an undervoltage recovery  indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition from mode Direction to mode Transition number Pin STBN EN UVVIO UVVBAT UVVCC PWON Wake Standby Normal 40 H H cleared cleared  cleared X X [1] Receive-only 41 H L cleared cleared  cleared X X [1] Normal 42 H H cleared  cleared cleared X X Normal 43 H H  cleared cleared cleared X X Receive-only 44 H L cleared  cleared cleared X X Receive-only 45 H L  cleared cleared cleared X X Sleep Rev. 1 — 28 October 2016 All information provided in this document is subject to legal disclaimers. PowerOff Flag Note Standby 46 L L cleared  cleared cleared X X Standby 47 L L  cleared cleared cleared X X Go-to-sleep 48 L H cleared  cleared cleared X X Go-to-sleep 49 L H  cleared cleared cleared X X Standby 50 X X X X X  set X [1] Transition already completed when the voltage on pin VCC is above Vuvr(VCC) for longer than trec(uv)(VCC). [2] The voltage on pin VBAT is above Vuvr(VBAT) for longer than trec(uv)(VBAT) AND VDIG (the internal digital supply voltage to the state machine) > Vth(rec)POR. [2] TJA1081G FlexRay node transceiver 13 of 46 © NXP Semiconductors N.V. 2016. All rights reserved. TJA1081G NXP Semiconductors FlexRay node transceiver 7.1.5 Normal mode In Normal mode, the transceiver is able to transmit and receive data via bus lines BP and BM. The output of the normal receiver is connected directly to pin RXD. Transmitter behavior in Normal mode, with no TXEN timeout (see Section 7.4.7) and the temperature flag not set (TEMP HIGH = 0; see Table 11), is detailed in Table 10. In this mode, pin INH is set HIGH. Table 10. Transmitter function table BGE TXEN TXD Transmitter L X X transmitter is disabled X H X transmitter is disabled H L H transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW H L L transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH The first LOW level detected on pin TXD when pin BGE is HIGH and pin TXEN is LOW activates the transmitter. 7.1.6 Receive-only mode In Receive-only mode, the transceiver can only receive data. The transmitter is disabled, regardless of the voltage levels on pins BGE and TXEN. In this mode, pin INH is set HIGH. 7.1.7 Standby mode Standby mode is a low-power mode featuring very low current consumption. In this mode, the transceiver cannot transmit or receive data. The low-power receiver is activated to monitor the bus for wake-up patterns. A transition to Standby mode can be triggered by applying the appropriate levels on pins EN and STBN (see Figure 4 and Table 6) or if an undervoltage is detected on pin VCC (see Figure 4 and Section 7.1.9). In this mode, pin INH is set HIGH. If the wake flag is set, pins RXEN and RXD are driven LOW; otherwise pins RXEN and RXD are set HIGH (see Section 7.2). 7.1.8 Go-to-sleep mode In this mode, the transceiver behaves as in Standby mode. If Go-to-sleep mode remains active longer than the go-to-sleep hold time (th(gotosleep)) and the wake flag has been cleared previously, the transceiver switches to Sleep mode regardless of the voltage on pin EN. 7.1.9 Sleep mode Sleep mode is a low-power mode. The only difference between Sleep mode and Standby mode is that pin INH is set floating in Sleep mode. A transition to Sleep mode is triggered from all other modes when the UVVIO flag or the UVVBAT flag is set (see Table 8). TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 14 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver When the wake flag is set and VIO is valid, the undervoltage flags are reset. The transceiver switches from Sleep mode to the mode indicated by the levels on pins EN and STBN (see Table 8). 7.2 Wake-up mechanism From Sleep mode (pin INH floating), the transceiver enters Standby mode if the wake flag is set. Consequently, pin INH is switched on (HIGH). If an undervoltage is not detected on pins VIO, VCC or VBAT, the transceiver switches immediately to the mode indicated by the levels on pins EN and STBN. In Standby, Go-to-sleep and Sleep modes, pins RXD, RXEN and ERRN are driven LOW if the wake flag is set. 7.2.1 Remote wake-up 7.2.1.1 Bus wake-up via wake-up pattern A valid wake-up pattern on the bus triggers a remote wake-up. A valid remote wake-up pattern consists of a DATA_0, DATA_1 or idle, DATA_0, DATA_1 or idle sequence. The DATA_0 phases must last at least tdet(wake)DATA_0 and the DATA_1 or idle phases at least tdet(wake)idle. The entire sequence must be completed within tdet(wake)tot. < tdet(wake)tot 0V Vdif -500 mV > tdet(wake)DATA_0 > tdet(wake)idle > tdet(wake)DATA_0 > tdet(wake)idle 015aaa273 Fig 5. 7.2.1.2 Bus wake-up timing Bus wake-up via dedicated FlexRay data frame If the TJA1081G receives a dedicated data frame that emulates a valid wake-up pattern as detailed Figure 6, the remote wake-up source flag is set. Due to the Byte Start Sequence (BSS) preceding each byte, the DATA_0 and DATA_1 phases for the wake-up symbol are interrupted every 1 s. For 10 Mbit/s, the maximum interruption time is 130 ns. Such interruptions do not prevent the transceiver from recognizing the wake-up pattern in the payload of a data frame. The remote wake-up source flag is not set if an invalid wake-up pattern is received. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 15 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Vdif 130 ns wake-up 870 ns 870 ns +2000 0V -2000 770 870 870 ns ns ns 130 130 ns ns 5 µs 5 µs 5 µs 5 µs 015aaa361 Each interruption is 130 ns. The transition time from DATA_0 to DATA_1 and from DATA_1 to DATA_0 is about 20 ns. The following pattern sets the TJA1081G remote wake-up source flag: FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, FFh Fig 6. Minimum bus pattern for bus wake-up 7.2.2 Local wake-up via pin WAKE If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than tfltr(WAKE) (falling edge on pin WAKE), a local wake-up event on pin WAKE is detected. At the same time, the biasing of this pin is switched to pull-down. If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than tfltr(WAKE), the biasing of this pin is switched to pull up and a local wake-up is not detected. pull-up tfltr(WAKE) pull-down pull-up tfltr(WAKE) VBAT WAKE 0V RXD, RXEN and ERRN VBAT INH 0V 015aaa069 Sleep mode: VIO and (VBAT or VCC) still provided. Fig 7. TJA1081G Product data sheet Local wake-up timing via pin WAKE All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 16 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7.3 Fail-silent behavior To ensure fail-silent behavior, a reset mechanism for the digital state machine has been implemented along with undervoltage detection. If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver switches to a low-power mode. This action ensures that the transmitter and receiver are passive when an undervoltage is detected and that their behavior is defined. The digital state machine is supplied by VCC, VIO or VBAT. Therefore, the digital state machine is properly supplied as long as the voltage on pin VCC, VIO or VBAT remains above 4.5 V. If the voltage on all pins (i.e. VCC, VIO and VBAT) breaks down, a reset signal is transmitted to the digital state machine. The reset signal is transmitted as soon as the internal supply voltage to the digital state machine is no longer high enough to guarantee proper operation. This precaution ensures that the digital state machine is passive, and its behavior defined, when an undervoltage is detected. 7.3.1 VBAT undervoltage If the UVVBAT flag is set, the transceiver enters Sleep mode (pin INH is switched off) regardless of the voltage levels on pins EN and STBN. If the undervoltage recovers, the transceiver switches to the mode determined by the voltages on pins EN and STBN. 7.3.2 VCC undervoltage If the UVVCC flag is set, the transceiver switches to Standby mode regardless of the voltage levels on pins EN and STBN. If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is again enabled. 7.3.3 VIO undervoltage If the voltage on pin VIO is lower than Vuvd(VIO) for longer than tdet(uv)(VIO) (even if the UVVIO flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set, the transceiver enters Sleep mode (pin INH is switched off). If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is again enabled. 7.4 Flags 7.4.1 Local wake-up source flag The local wake-up source flag can only be set in a low-power mode. When a wake-up event is detected on pin WAKE (see Section 7.2.2), the local wake-up source flag is set. The local wake-up source flag is reset by entering a low-power mode. 7.4.2 Remote wake-up source flag The remote wake-up source flag can only be set in a low-power mode if pin VBAT is within its operating range. When a remote wake-up event is detected on the bus lines (see Section 7.2.1), the remote wake-up source flag is set. The remote wake-up source flag is reset by entering a low-power mode. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 17 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7.4.3 Wake flag The wake flag is set if the local or remote wake-up source flag is set. The wake flag is reset by entering a low-power mode or by setting one of the undervoltage flags. 7.4.4 Power-on flag If the internal supply voltage to the digital section rises above the minimum operating level, the PWON power-on flag is set. The PWON flag is reset when the TJA1081G enters Normal mode. 7.4.5 Temperature medium flag If the junction temperature exceeds Tj(warn)(medium) in a normal-power mode, the temperature medium flag is set. The temperature medium flag is reset when the junction temperature drops below Tj(warn)(medium) (in a normal-power mode or after the status register has been read in a low-power mode). No action is taken when this flag is set. 7.4.6 Temperature high flag If the junction temperature exceeds Tj(dis)(high) in a normal-power mode, the temperature high flag is set. If a negative edge is applied to pin TXEN while the junction temperature is below Tj(dis)(high) in a normal-power mode, the temperature high flag is reset. The transmitter is disabled when the temperature high flag is set. 7.4.7 TXEN clamped flag If pin TXEN is LOW for longer than tdetCL(TXEN), the TXEN clamped flag is set. If pin TXEN is HIGH, the TXEN clamped flag is reset. The transmitter is disabled when the TXEN clamped flag is set. 7.4.8 Bus error flag The bus error flag is set if pin TXEN is LOW, pin BGE is HIGH and the data received on the bus lines (pins BP and BM) is different to that received on pin TXD. The transmission of any valid communication element, including a wake-up pattern, is not detected as a bus error. The bus error flag is reset if the data on the bus lines (pins BP and BM) is the same as on pin TXD or if the transmitter is disabled. No action is taken when the bus error flag is set. 7.4.9 UVVBAT flag If the voltage on pin VBAT is lower than Vuvd(VBAT) for longer than tdet(uv)(VBAT), the UVVBAT flag is set. The UVVBAT flag is reset if the voltage is higher than Vuvr(VBAT) for longer than tto(uvr)(VBAT) or by setting the wake flag; see Section 7.3.1. 7.4.10 UVVCC flag In a non-low-power mode, the UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than tdet(uv)(VCC). In a low-power mode, the UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than tto(uvd)(VCC). The UVVCC flag is reset if the voltage on pin VCC is higher than Vuvr(VCC) for longer than tto(uvr)(VCC) or the wake flag is set; see Section 7.3.2. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 18 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 7.4.11 UVVIO flag If the voltage on pin VIO is lower than Vuvd(VIO) for longer than tto(uvd)(VIO), the UVVIO flag is set. The UVVIO flag is reset if the voltage on pin VIO is higher than Vuvr(VIO) for longer than tto(uvr)(VIO) or the wake flag is set; see Section 7.3.3. 7.5 Status register Pin ERRN goes LOW when one or more of status bits S4 to S10 is set. The contents of the status register (Table 11) can be read out on pin ERRN using the input signal on pin EN as a clock. The timing diagram is shown in Figure 8. The status register is accessible if: • UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V • UVVCC flag is not set and the voltage on pin VIO is between 2.8 V and 4.75 V If an edge is not detected on pin EN for tdet(EN) after reading the status register, status bits S4 to S10 are cleared provided the corresponding flags have been reset. Table 11. Status bits Bit number Status bit Description S0 LOCAL WAKEUP local wake-up source flag is redirected to this bit S1 REMOTE WAKEUP remote wake-up source flag is redirected to this bit S2 - not used; always set S3 PWON status bit set means that PWON flag has been set previously S4 BUS ERROR status bit set means that bus error flag has been set previously S5 TEMP HIGH status bit set means temperature high flag has been set previously S6 TEMP MEDIUM status bit set means that temperature medium flag has been set previously S7 TXEN CLAMPED status bit set means that TXEN clamped flag has been set previously S8 UVVBAT status bit set means UVVBAT flag has been set previously S9 UVVCC status bit set means UVVCC flag has been set previously S10 UVVIO status bit set means UVVIO flag has been set previously S11 BGE FEEDBACK BGE feedback (status bit reset if pin BGE LOW; status bit set if pin BGE HIGH) S12 - not used; always reset TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 19 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver receive only normal 0.7VIO STBN tdet(EN) 0.7VIO EN Tclk(EN) td(EN-ERRN) 0.7VIO ERRN 0.3VIO S0 S1 S2 015aaa341 Fig 8. Timing diagram for status bits TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 20 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 8. Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to ground. Symbol Parameter voltage on pin x Vx IO(INH) output current on pin INH Io(WAKE) output current on pin WAKE transient voltage Vtrt Tstg storage temperature Tvj virtual junction temperature Tamb ambient temperature VESD electrostatic discharge voltage Conditions Min Max Unit on pin VBAT [1] 0.3 +60 V on pins VCC, VIO, BGE, TXEN, TXD, EN and STBN [1] 0.3 +5.5 V on pins INH, WAKE [1] 0.3 VBAT + 0.3 V on pins ERRN, RXD and RXEN [1] 0.3 VIO + 0.3 V on pins BP and BM with resect to pins VBAT, WAKE, INH, GND and each other [1] 60 +60 V 1 - mA 15 - mA pin GND not connected on pins BM and BP [2] pulse 1 100 - V pulse 2a - 75 V pulse 3a 150 - V pulse 3b - 100 V 55 +150 C 40 +150 C 40 +125 C [3] IEC 61000-4-2 (150 pF, 330 ) [4] 6.0 +6.0 kV on pin VBAT to ground [5] 6.0 +6.0 kV on pin WAKE to ground [6] 6.0 +6.0 kV on pins BP and BM to ground Human Body Model (HBM); 100 pF, 1.5 k [7] on pins BP and BM to ground 6.0 +6.0 kV on pins VBAT and WAKE to ground 4.0 +4.0 kV 2.0 +2.0 kV 100 +100 V on corner pins 750 +750 V on any other pin 500 +500 V on any other pin Machine Model (MM); 200 pF, 0.75 H, 10 ; any pin [8] Charged Device Model (CDM); field induced charge; 4 pF [9] [1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these values. [2] According to TS 62228 (2007), Section 4.2.4; parameters for standard pulses defined in ISO 7637-2:2004-09-15. [3] In accordance with IEC 60747-1. An alternative definition of Tvj is: Tvj = Tamb + P  Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [4] According to TS 62228 (2007), Section 4.3; DIN EN IEC 61000-4-2. [5] With 100 nF from VBAT to GND. [6] With 3.3 kin series. [7] According to AEC-Q100-002. [8] According to AEC-Q100-003. [9] According to AEC-Q100-011 Rev-C1. The classification level is C4B. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 21 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 9. Thermal characteristics Table 13. Symbol Rth(j-a) Thermal characteristics Parameter Conditions thermal resistance from junction to ambient Typ Unit dual-layer board [1] 96 K/W four-layer board [2] 72 K/W [1] According to JEDEC JESD51-2, JESD51-3 and JESD51-5 at natural convection on 1s board with thermal via array under the exposed pad connected to the second copper layer. [2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer. 10. Static characteristics Table 14. Static characteristics All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40 to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit 4.75 - 60 V low-power modes; no load on pin INH - - 55 A normal-power modes - - 1 mA Pin VBAT VBAT battery supply voltage IBAT battery supply current Vuvd(VBAT) undervoltage detection voltage on pin VBAT 4.45 - 4.715 V Vuvr(VBAT) undervoltage recovery voltage on pin VBAT 4.475 - 4.74 V Vuvhys(VBAT) undervoltage hysteresis voltage on pin VBAT 25 - 290 mV VCC supply voltage 4.75 - 5.25 V ICC supply current low-power modes 1 +2 +10 A Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode - 13 21 mA Normal mode; VBGE = VIO; VTXEN = 0 V - 37 50 mA Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus =   - 14 22 mA Pin VCC Vuvd(VCC) undervoltage detection voltage on pin VCC 4.45 - 4.72 V Vuvr(VCC) undervoltage recovery voltage on pin VCC 4.47 - 4.74 V Vuvhys(VCC) undervoltage hysteresis voltage on pin VCC 20 - 290 mV supply voltage on pin VIO 2.8 - 5.25 V Pin VIO VIO TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 22 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 14. Static characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40 to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit IIO supply current on pin VIO low-power modes; VTXEN = VIO 1 +2 +10 A Normal and Receive-only modes; VTXD = VIO - - 1 mA from digital input pins; PowerOff mode; VTXEN = 5.25 V; VTXD = 5.25 V; VBGE = 5.25 V; VEN = 5.25 V; VSTBN = 5.25 V; VCC = VIO = 0 V 5 - +5 A Ir(VIO) reverse current on pin VIO Vuvd(VIO) undervoltage detection voltage on pin VIO 2.55 - 2.765 V Vuvr(VIO) undervoltage recovery voltage on pin VIO 2.575 - 2.79 V Vuvhys(VIO) undervoltage hysteresis voltage on pin VIO 25 - 240 mV VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VEN = 0.7VIO 3 - 15 A IIL LOW-level input current VEN = 0 V 1 0 +1 A Pin EN Pin STBN VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VSTBN = 0.7VIO 3 - 15 A IIL LOW-level input current VSTBN = 0 V 1 0 +1 A 0.7VIO - 5.5 V Pin TXEN VIH HIGH-level input voltage VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VTXEN = VIO 1 0 +1 A IIL LOW-level input current VTXEN = 0.3VIO 300 - 50 A IL leakage current VTXEN = 5.25 V; VIO = 0 V 1 0 +1 A Pin BGE VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VBGE = 0.7VIO 3 - 15 A IIL LOW-level input current VBGE = 0 V 1 0 +1 A VIH HIGH-level input voltage normal-power modes 0.6VIO - VIO + 0.3 V VIL LOW-level input voltage normal-power modes 0.3 - 0.4VIO V IIH HIGH-level input current VTXD = VIO 3 - 15 A Pin TXD TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 23 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 14. Static characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40 to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit IIL LOW-level input current normal-power modes; VTXD = 0 V 5 0 +5 A low-power modes 1 0 +1 A 1 0 +1 A - 5 10 pF 20 - 1 mA ILI input leakage current VTXD = 5.25 V; VIO = 0 V input capacitance not tested; with respect to all other pins at ground; VTXD = 100 mV; f = 5 MHz IOH HIGH-level output current VRXD = VIO  0.4 V; VIO = VCC IOL LOW-level output current VRXD = 0.4 V VOH HIGH-level output voltage VOL VO Ci [1] Pin RXD 1 - 20 mA IOH(RXD) = 1 mA [1] VIO  0.4 - VIO V LOW-level output voltage IOL(RXD) = 1 mA [1] - - 0.4 V output voltage when undervoltage on VIO; VCC  4.75 V; RL = 100 k to ground - - 0.5 V RL = 100 k to VIO; power off VIO  0.5 - VIO V 8 3 0.5 mA Pin ERRN IOH HIGH-level output current VERRN = VIO  0.4 V; VIO = VCC IOL LOW-level output current VERRN = 0.4 V VOH HIGH-level output voltage VOL 0.5 2 8 mA IOH(ERRN) = 0.5 mA [1] VIO  0.4 - VIO V LOW-level output voltage IOL(ERRN) = 0.5 mA [1] - - 0.4 V IL leakage current 0 V  VERRN  VIO; power off 5 0 +5 A VO output voltage when undervoltage on VIO; VCC > 4.75 V; RL = 100 k to ground - - 0.5 V RL = 100 k to ground; power off - - 0.5 V VRXEN = VIO  0.4 V; VIO = VCC 8 3 0.5 mA Pin RXEN IOH HIGH-level output current IOL LOW-level output current VRXEN = 0.4 V 0.5 2 8 mA VOH HIGH-level output voltage IOH(RXEN) = 0.5 mA [1] VIO  0.4 - VIO V VOL LOW-level output voltage IOL(RXEN) = 0.5 mA [1] - - 0.4 V IL leakage current 0 V  VRXEN  VIO; power off 5 0 +5 A TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 24 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 14. Static characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40 to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit VO output voltage when undervoltage on VIO; VCC > 4.75 V; RL = 100 k to ground - - 0.5 V RL = 100 k to VIO; power off VIO  0.5 - VIO V Normal or Receive-only mode; VTXEN = VIO; 4.5 V  VCC  5.25 V 0.4VCC 0.5VCC 0.6VCC V Standby, Go-to-sleep or Sleep mode 0.1 Normal or Receive-only mode; VTXEN = VIO; 4.5 V  VCC  5.25 V 0.4VCC 0.5VCC 0.6VCC V Standby, Go-to-sleep or Sleep mode 0.1 0 +0.1 V Pins BP and BM Vo(idle)(BP) Vo(idle)(BM) idle output voltage on pin BP idle output voltage on pin BM 0 +0.1 V Io(idle)BP idle output current on pin BP 60 V  VBP  +60 V; with respect to ground and VBAT 7.5 - +7.5 mA Io(idle)BM idle output current on pin BM 60 V  VBM  +60 V; with respect to ground and VBAT 7.5 - +7.5 mA Vo(idle)(dif) differential idle output voltage [2] 25 0 +25 mV 4.75 V  VCC  5.25 V [2] 600 - 2000 mV 4.45 V  VCC  5.25 V [2] 530 - 2000 mV 4.75 V  VCC  5.25 V [2] 2000 - 600 mV 4.45 V  VCC  5.25 V [2] 2000 - 530 mV normal-power modes; 10 V  Vcm  +15 V; see Figure 10 [3] 150 210 300 mV normal-power modes; 10 V  Vcm  +15 V; see Figure 10 [3] 300 210 150 mV low-power modes; see Figure 10 [4] 400 300 100 mV normal-power modes; Vcm = 2.5 V [4] 30 - +30 mV 150 210 300 mV VOH(dif) VOL(dif) VIH(dif) VIL(dif) differential HIGH-level output voltage differential LOW-level output voltage differential HIGH-level input voltage differential LOW-level input voltage Vi(dif)(H-L) differential input volt. diff. betw. HIGHand LOW-levels (abs. value) Vi(dif)det(act) activity detection differential input voltage normal-power modes (absolute value) TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 [4] [4] © NXP Semiconductors N.V. 2016. All rights reserved. 25 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 14. Static characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40 to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol IO(sc) Parameter Conditions short-circuit output current (absolute value) on pin BP; 5 V  VBP  +60 V Rsc  1 ; tsc  1500 s [5] on pin BM; 5 V  VBM  +60 V Rsc  1 ; tsc  1500 s [5] on pins BP and BM; Rsc  1 ; tsc  1500 s; VBP = VBM [5] Min Typ Max Unit - - 60 mA - - 60 mA - - 60 mA [6] [6] [6] Ri(BP) input resistance on pin BP idle level; Rbus =   10 18 40 k Ri(BM) input resistance on pin BM idle level; Rbus =   10 18 40 k Ri(dif)(BP-BM) differential input resistance between pin BP and pin BM idle level; Rbus =   20 36 80 k ILI(BP) input leakage current on pin BP power off; VBP = VBM = 5 V; all other pins connected to GND; GND connected to 0 V 5 0 +5 A +1600 A +5 A +1600 A loss of ground; VBP = VBM = 0 V; all other pins connected to 16 V via 0  ILI(BM) input leakage current on pin BM [1] 5 power off; VBP = VBM = 5 V; all other pins connected to GND; GND connected to 0 V loss of ground; VBP = VBM = 0 V; all other pins connected to 16 V via 0  1600 [1] 0 1600 Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage 0.4VCC 0.5VCC 0.6VCC V Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage 0.4VCC 0.5VCC 0.6VCC V Vcm(bus) bus common-mode voltage difference 30 0 +30 mV - 8 15 pF Ci(BP) input capacitance on pin BP with respect to all other pins at ground; VBP = 100 mV; f = 5 MHz [1] Ci(BM) input capacitance on pin BM with respect to all other pins at ground; VBM = 100 mV; f = 5 MHz [1] - 8 15 pF Ci(dif)(BP-BM) differential input capacitance between pin with respect to all other BP and pin BM pins at ground; V(BM-BP) = 100 mV; f = 5 MHz [1] - 2 5 pF Zo(eq)TX transmitter equivalent output impedance [1] 35 - 100  TJA1081G Product data sheet Normal mode; Rbus = 40  or 100 ; Cbus = 100 pF All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 [7] © NXP Semiconductors N.V. 2016. All rights reserved. 26 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 14. Static characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40 to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit HIGH-level output voltage on pin INH IINH = 0.2 mA VBAT  VBAT  VBAT 0.8 0.3 V IINH = 1 mA; VBAT  5.5 V VBAT  4 VBAT V Pin INH VOH(INH) IL(INH) leakage current on pin INH Sleep mode 5 0 +5 A IOL(INH) LOW-level output current on pin INH VINH = 0 V 7 4 1 mA Pin WAKE Vth(det)(WAKE) detection threshold voltage on pin WAKE low-power mode 2 - 3.75 V Vhys hysteresis voltage 0.3 - 1.2 V IIL LOW-level input current VWAKE = 2 V for t > tfltr(WAKE) 3 - 11 A VWAKE = 0 V 2 - 0.3 A IIH HIGH-level input current VWAKE = 3.75 V for t > tfltr(WAKE); 4.75 V  VBAT  60 V 11 - 3 A VWAKE = VBAT 0.2 - 2 A Temperature protection Tj(warn)(medium) medium warning junction temperature VBAT > 5.5 V 155 165 175 C Tj(dis)(high) high disable junction temperature VBAT > 5.5 V 180 190 200 C Vth(det)POR power-on reset detection threshold voltage of internal digital circuitry 3.0 - 3.4 V Vth(rec)POR power-on reset recovery threshold voltage of internal digital circuitry 3.1 - 3.5 V Vhys(POR) power-on reset hysteresis voltage of internal digital circuitry 100 - 500 mV Power-on reset [1] Not tested in production; guaranteed by design. [2] Values also guaranteed when the signal on TXD is constant for between 100 ns and 4400 ns before the first edge. [3] Activity detected previously. [4] Vcm is the BP/BM common mode voltage. [5] Rsc is the short-circuit resistance; voltage difference between bus pins BP and BM is 60 V max. [6] tsc is the minimum duration of the short circuit. [7] Zo(eq)TX = 50   (Vbus(100) - Vbus(40))/(2.5  Vbus(40) - Vbus(100)) where: - Vbus(100) is the differential output voltage on a load of 100 and 100 pF in parallel - Vbus(40) is the differential output voltage on a load of 40  and 100 pF in parallel when driving a DATA_1. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 27 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 11. Dynamic characteristics Table 15. Dynamic characteristics All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40  to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit delay time from TXD to bus Normal mode; see Figure 9 DATA_0 - - 60 ns DATA_1 - - 60 ns 4 - +4 ns - - 75 ns - - 75 ns 5 - +5 ns Pins BP and BM td(TXD-bus) [1] [2] td(TXD-bus) td(bus-RXD) delay time difference from TXD to bus delay time from bus to RXD Normal mode; between DATA_0 and DATA_1; see Figure 10 [1] Normal mode; Vcm = 2.5 V; CRXD = 25 pF; see Figure 10 [3] [2] [3] DATA_0 DATA_1 td(bus-RXD) delay time difference from bus to RXD Normal mode; Vcm = 2.5 V; CRXD = 25 pF; between DATA_0 and DATA_1; see Figure 10 td(TXEN-busidle) delay time from TXEN to bus idle Normal mode; see Figure 9 - 50 75 ns td(TXEN-busact) delay time from TXEN to bus active Normal mode; see Figure 9 - 51 75 ns td(TXEN-bus) delay time difference from TXEN to bus Normal mode; between TXEN-to-bus active and TXEN-to-bus idle; TXD LOW; see Figure 9 50 - +50 ns td(BGE-busidle) delay time from BGE to bus idle Normal mode; see Figure 9 - 50 75 ns td(BGE-busact) delay time from BGE to bus active Normal mode; see Figure 9 - 53 75 ns td(TXENH-RXDH) delay time from TXEN HIGH to RXD HIGH Normal mode; TXD LOW - - 325 ns bus differential rise time 20 % to 80 % 6 - 18.75 ns - - 30 ns [3] Bus slope tr(dif)(bus) [1] DATA_0 to idle; 300 mV to 30 mV; Normal mode tf(dif)(bus) t(r-f)(dif) TJA1081G Product data sheet bus differential fall time 80 % to 20 % [1] 6 - 18.75 ns idle to DATA_0; 30 mV to 300 mV; Normal mode - - 30 ns DATA_1 to idle; 300 mV to 30 mV; Normal mode - - 30 ns 3 - +3 ns difference between differential rise and 80 % to 20 % fall time All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 28 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 15. Dynamic characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40  to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit rise time CRXD = 15 pF; 20 % to 80 % - - 9 ns CRXD = 25 pF; 20 % to 80 % - - 10.75 - - 9 Pin RXD tr tf fall time CRXD = 15 pF; 80 % to 20 % CRXD = 25 pF; 80 % to 20 % - - 10.75 t(r+f) sum of rise and fall time CRXD = 15 pF; 20 % to 80 % and 80 % to 20 % - - 13 ns CRXD = 25 pF; 20 % to 80 % and 80 % to 20 % - - 16.5 ns CRXD = 10 pF load at end of 50  strip with 1 ns delay; 20 % to 80 % and 80 % to 20 %; simulation only - - 16.5 ns CRXD = 15 pF; 20 % to 80 % 5 - +5 ns CRXD = 25 pF; 20 % to 80 % 5 - +5 ns CRXD = 10 pF load at end of 50  strip with 1 ns delay; 20 % to 80 % and 80 % to 20 %; simulation only 5 - +5 ns t(r-f) difference between rise and fall time ns WAKE symbol detection tdet(wake)DATA_0 DATA_0 wake-up detection time tdet(wake)idle idle wake-up detection time tdet(wake)tot total wake-up detection time tsup(int)wake Standby or Sleep mode; 10 V  Vcm  +15 V [4] wake-up interruption suppression time 1 - 4 s 1 - 4 s 50 - 115 s 130 - 1000 ns Reaction time td(wakedet-INHH) delay time from wake-up detection to INH HIGH low-power mode; RL(INH-GND) = 100 k; VINH = 2 V - - 35 s td(event-ERRNL) delay time from event detection to ERRN LOW low-power mode - - 10 s td(wakedet-RXDL) delay time from wake-up detection to RXD LOW low-power mode - - 10 s td(STBNX-moch) delay time from STBN changing to mode change - - 100 s td(ENX-moch) delay time from EN changing to mode change - - 100 s Undervoltage detection tdet(uv)(VCC) undervoltage detection time on pin VCC VCC = 4.35 V 5 - 100 s tto(uvd)(VCC) undervoltage detection time-out time on pin VCC 100 - 670 ms trec(uv)(VCC) undervoltage recovery time on pin VCC VCC = 4.85 V 5 - 100 s tto(uvr)(VCC) undervoltage recovery time-out time on pin VCC 1 - 5.2 ms TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 29 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 15. Dynamic characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40  to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit tdet(uv)(VIO) undervoltage detection time on pin VIO VIO = 2.45 V 5 - 100 s tto(uvd)(VIO) undervoltage detection time-out time on pin VIO 100 - 670 ms trec(uv)(VIO) undervoltage recovery time on pin VIO 5 - 100 s tto(uvr)(VIO) undervoltage recovery time-out time on pin VIO 1 - 5.2 ms tdet(uv)(VBAT) undervoltage detection time on pin VBAT VBAT = 4.35 V 5 - 100 s trec(uv)(VBAT) undervoltage recovery time on pin VBAT VBAT = 4.85 V 5 - 100 s tto(uvr)(VBAT) undervoltage recovery time-out time on pin VBAT 1 - 5.2 ms VIO = 2.9 V Activity detection tdet(act)(bus) activity detection time on bus pins Vdif: 0 mV  400 mV; Vcm = 2.5 V; 100 - 200 ns tdet(idle)(bus) idle detection time on bus pins Vdif: 400 mV  0 mV; Vcm = 2.5 V; 50 - 200 ns tdet(act-idle) difference between active and idle detection time Vcm = 2.5 V 75 - +75 ns 3 - 12 s 3 - 10 s - - 10 s 20 35 50 s Mode control pins td(STBN-RXD) STBN to RXD delay time STBN HIGH to RXD HIGH; remote or local wake-up source flag set tfltr(STBN) filter time on pin STBN rising and falling edges td(STBN-stb) delay time from STBN to standby mode STBN LOW to Standby mode; Receive-only mode th(gotosleep) go-to-sleep hold time [5] Status register tdet(EN) detection time on pin EN for mode control 5 - 20 s Tclk(EN) clock period on pin EN EN signal used as clock for reading status bits; see Figure 8 1 - 5 s td(EN-ERRN) delay time from EN to ERRN when reading status bits; see Figure 8 - - 0.5 s filter time on pin WAKE low-power modes; falling edge on pin WAKE; 5.5 V  VBAT  27 V 2.9 - 100 s low-power modes; falling edge on pin WAKE; 27 V  VBAT  60 V 2.9 - 175 s Pin WAKE tfltr(WAKE) TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 30 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 15. Dynamic characteristics …continued All parameters are guaranteed for VBAT = 4.45 V to 60 V; VCC = 4.45 V to 5.25 V; VIO = 2.55 V to 5.25 V; Tvj = 40 C to +150 C; Cbus = 100 pF; Rbus = 40  to 55  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit 650 - 2600 s 100 - 275 ns 100 - 275 ns Miscellaneous tdetCL(TXEN) td(busact-RXDL) td(busidle-RXDH) TXEN clamp detection time delay time from bus active to RXD LOW Normal mode; Vcm = 2.5 V; CRXD = 25 pF; see Figure 9 [6] delay time from bus idle to RXD HIGH Normal mode; Vcm = 2.5 V; CRXD = 25 pF; see Figure 9 [6] [7] [8] [1] Values also guaranteed when the signal on TXD is constant for between 100 ns and 4400 ns before the first edge. [2] Sum of rise and fall times on TXD (20 % to 80 % on VIO) is 9 ns (max). [3] Guaranteed for Vbus(dif) = 300 mV and Vbus(dif) = 150 mV; Vbus(dif) is the differential bus voltage VBP  VBM. [4] The minimum value is guaranteed when the phase that was interrupted was present continuously for at least 870 ns. [5] The same parameter is guaranteed by design for the transition from Normal to Go-to-sleep mode. [6] Not tested in production; guaranteed by design. [7] td(busact-RXDL) = td(bus-RXD) + tdet(act)(bus). [8] td(busidle-RXDH) = td(bus-RXD) + tdet(idle)(bus). TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 31 of 46 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx TXD 0.5VIO TXEN 0.5VIO BGE 0.5VIO Rev. 1 — 28 October 2016 All information provided in this document is subject to legal disclaimers. BP - BM +300 mV +150 mV 0V -300 mV RXEN 0.5VIO RXD 0.5VIO td(TXEN-busact) td(TXEN-busidle) NXP Semiconductors TJA1081G Product data sheet td(TXD-bus) td(TXD-bus) td(BGE-busact) td(BGE-busidle) 80 % -150 mV td(bus-RXD) -30 mV td(bus-RXD) -30 mV -300 mV td(busidle-RXDH) td(busact-RXDL) -300 mV tr(dif)(bus) tf(dif)(bus) 20 % tr(dif)(bus) tf(dif)(bus) 015aaa274 Fig 9. Detailed timing diagram TJA1081G FlexRay node transceiver 32 of 46 © NXP Semiconductors N.V. 2016. All rights reserved. TJA1081G NXP Semiconductors FlexRay node transceiver Vbus tf(bus)(2) tr(bus)(2) 22.5 ns max. 22.5 ns max. +Vbus(1) +300 mV +150 mV 0 mV t -150 mV -300 mV -Vbus(1) 60 ns to 4340 ns td(bus-RXD)DATA_0 td(bus-RXD)DATA_1 RXD 100 % VIO 80 % VIO 50 % VIO 20 % VIO 0 % VIO tf(RXD) tr(RXD) 015aaa142 (1) Vbus = 400 mV (min) to 3000 mV (max). (2) tr(bus) and tf(bus) are defined for Vbus between 300 mV and +300 mV; tr(bus) = tf(bus) = 22.5 ns for Vbus = 400 mV to 800 mV; value is lower for Vbus > 800 mV. Fig 10. Normal receiver timing diagram 12. Application information Further information on the application of the TJA1081G can be found in NXP application hints AH102 TJA1081B/TJA1081G FlexRay node transceiver (Ref. 5). TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 33 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 13. Test information 9 9  Q) —) 9,2  9&&  9%$7   %3 5EXV 7-$*   &EXV %0 5;' S) DDD Fig 11. Test circuit for dynamic characteristics 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 34 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 14. Package outline SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 12. Package outline SOT338-1 (SSOP16) TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 35 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 36 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17 Table 16. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 17. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 37 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 38 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 16. Appendix: EPL 3.0.1 to TJA1081G parameter conversion Table 18. EPL 3.0.1 to TJA1081G conversion This table maps the EPL 3.0.1 parameters names to those in the TJA1081G. Values are provided for reference only (see the characteristics tables for comprehensive listings of guaranteed parameter values). EPL 3.0.1 TJA1081G Symbol Min Max Unit Symbol Min Max Unit dBDRxAsym - 5 ns td(bus-RXD) - 5 ns dBDRx10 - 75 ns td(bus-RXD) - 75 ns dBDRx01 - 75 ns td(bus-RXD) - 75 ns dBDRxai 50 275 ns td(busidle-RXDH) 100 275 ns dBDRxia 100 325 ns td(busact-RXDL) 100 275 ns dBDTxAsym - 4 ns td(TXD-bus) - 4 ns dBDTx10 - 75 ns td(TXD-bus) - 60 ns dBDTx01 - 75 ns td(TXD-bus) - 60 ns dBDTxai - 75 ns td(TXEN-busidle) - 75 ns dBDTxia - 75 ns td(TXEN-busact) - 75 ns dBusTxai - 30 ns tr(dif)(bus)(DATA_0-idle) - 30 ns dBusTxia - 30 ns tf(dif)(bus)(idle-DATA_0) - 30 ns dBusTx01 6 18.75 ns tr(dif)(bus) 6 18.75 ns dBusTx10 6 18.75 ns tf(dif)(bus) 6 18.75 ns uBDTxactive 600 2000 mV VOH(dif) 600 2000 mV uBDTxidle 0 30 mV VO(idle)(dif) 25 +25 mV uVDIG-OUT-HIGH 80 100 % VOH(RXD) VIO  0.4 VIO V uVDIG-OUT-LOW - 20 % VOL(RXD) - 0.4 V uVDIG-IN-HIGH - 70 % VIH(TXEN) 0.7VIO 5.5 V VIH(EN) 0.7VIO 5.5 V VIH(STBN) 0.7VIO 5.5 V VIH(BGE) 0.7VIO 5.5 V VIL(TXEN) 0.3 0.3VIO V VIL(EN) 0.3 0.3VIO V VIL(STBN) 0.3 0.3VIO V VIL(BGE) 0.3 0.3VIO V uVDIG-IN-LOW 30 - % uData0 300 150 mV VIL(dif) 300 150 mV uData1 150 300 mV VIH(dif) 150 300 mV uData1-|uData0| 30 30 mV Vi(dif)(H-L) 30 30 mV dBDActivityDetection 100 250 ns tdet(act)(bus) 100 200 ns dBDIdleDetection 50 200 ns tdet(idle)(bus) 50 200 ns RCM1, RCM2 10 40 k Ri(BP), Ri(BM) 10 40 k uCM 10 +15 V Vcm[1] 10 +15 V iBMGNDShortMax - 60 mA IO(sc)(BM) - 60 mA iBPGNDShortMax - 60 mA IO(sc)(BP) - 60 mA iBMBAT48ShortMax - 72 mA IO(sc)(BM) - 60 mA TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 39 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 18. EPL 3.0.1 to TJA1081G conversion …continued This table maps the EPL 3.0.1 parameters names to those in the TJA1081G. Values are provided for reference only (see the characteristics tables for comprehensive listings of guaranteed parameter values). EPL 3.0.1 TJA1081G Symbol Min Max Unit Symbol Min Max Unit iBPBAT48ShortMax - 72 mA IO(sc)(BP) - 60 mA iBMBAT27ShortMax - 60 mA IO(sc)(BM) - 60 mA iBPBAT27ShortMax - 60 mA IO(sc)(BP) - 60 mA mV Vo(idle)(BP), Vo(idle)(BM)[2] 1800 3150 mV uBias - Non-Low-Power 1800 3200 uBias - Low-Power 200 +200 mV Vo(idle)(BP), Vo(idle)(BM)[3] 0.1 +0.1 V dBDWakePulseFilter 1 500 s tfltr(WAKE) 2.9 100 s dWU0Detect 1 4 s tdet(wake)DATA_0 1 4 s dWUIdleDetect 1 4 s tdet(wake)idle 1 4 s dWUTimeout 48 140 s tdet(wake)tot 50 115 s uVBAT-WAKE (VCC implemented) - 7 V VBAT 4.75 60 V uBDUVVBAT 4 5.5 V Vuvd(VBAT) 4.45 4.715 V uBDUVVCC 4 - V Vuvd(VCC) 4.45 4.72 V dBDUVVCC - 1000 ms tdet(uv)(VCC) 5 100 s tto(uvd)(VCC) 100 670 ms iBPLeak - 25 A ILI(BP) 5 +5 A iBMLeak - 25 A ILI(BM) 5 +5 A Functional class: BD voltage regulator control implemented; see Section 2.5 Functional class: Bus Driver logic level adaptation implemented; see Section 2.5 Functional class: Bus Driver - Bus guardian interface implemented; see Section 2.5 Device qualification according to AEC-Q100 (Rev. F) see Section 2.1 TAMB_Class1 40 +125 C Tamb 40 +125 C dBDTxDM 50 +50 ns td(TXEN-bus) 50 +50 S iBM-5VshortMax - 60 mA IO(sc)(BM) - 60 mA iBP-5VshortMax - 60 mA IO(sc)(BP) - 60 mA iBMBPShortMax - 60 mA IO(sc)(BP-BM) - 60 mA iBPBMShortMax - 60 mA IO(sc)(BM-BP) - 60 mA iBMBAT60ShortMax - 90 mA IO(sc)(BM) - 60 mA iBPBAT60ShortMax - 90 mA IO(sc)(BP) - 60 mA dBDUVVBAT - 1000 ms tdet(uv)(VBAT) 5 100 s uUVIO 2 - V Vuvd(VIO) 2.55 2.765 V dBDUVVIO - 1000 ms tdet(uv)(VIO) 5 100 s tto(uvd)(VIO) 100 670 ms dBDWakeupReactionlocal dBDWakeupReactionremote TJA1081G Product data sheet - - 100 100 s s td(wakedet-INHH) - 35 s td(event-ERRNL) - 10 s td(wakedet-RXDL) - 10 s td(wakedet-INHH) - 35 s td(event-ERRNL) - 10 s td(wakedet-RXDL) - 10 s All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 40 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 18. EPL 3.0.1 to TJA1081G conversion …continued This table maps the EPL 3.0.1 parameters names to those in the TJA1081G. Values are provided for reference only (see the characteristics tables for comprehensive listings of guaranteed parameter values). EPL 3.0.1 TJA1081G Symbol Min Max Unit Symbol Min Max Unit dBDTxActiveMax 650 2600 s tdetCL(TXEN) 650 2600 s dBDModeChange - 100 s td(STBNX-moch) - 100 s td(ENX-moch) - 100 s s td(event-ERRNL) - 10 s dReactionTimeERRN - uINH1Not_Sleep uVBAT 1V V VOH(INH) VBAT  0.8 VBAT V iINH1Leak - 10 A IL(INH) 5 +5 A uData0_LP 400 100 mV VIL(dif) (pins BP and BM) 400 100 mV dWUInterrupt 0.13 1 s tsup(int)wake 130 1000 ns uBDLogic_1 - 60 % VIH(TXD) 0.6VIO VIO + 0.3 V V uBDLogic_0 40 - % VIL(TXD) 0.3 0.4VIO V dBDRVCC - 10 ms dBDRVBAT dBDRVIO 100 - 10 - 10 ms ms trec(uv)(VCC) 5 100 s tto(uvr)(VCC) 1 5.2 ms trec(uv)(VBAT) 5 100 s tto(uvr)(VBAT) 1 5.2 ms trec(uv)(VIO) 5 100 s tto(uvr)(VIO) 1 5.2 ms iBPLeakGND - 1600 A ILI(BP) 1600 +1600 A iBMLeakGND - 1600 A ILI(BM) 1600 +1600 A 6 - kV VESD: HBM on pins VBAT and 4 WAKE to GND - kV Functional class: Bus Driver Remote Wakeup implemented; see Section 2.5 Functional class: Increased Voltage Amplitude Transmitter implemented; see Section 2.5 uESDEXT 6 - kV VESD: HBM on pins BP and BM to GND uESDINT 2 - kV VESD (HBM on any other pin) 2 - kV uESD 6 - kV IEC 61000-4-2 on pins BP, BM, VBAT and WAKE 6 - kV dBDRxDR15 + dBDRxDF15 - 13 ns t(r+f) (pin RXD; 15 pF load) - 13 ns dBDRxDR15  dBDRxDF15 - 5 ns t(r-f) (pin RXD) - 5 ns C_BDTxD - 10 pF CI (pin TXD) - 10 pF dBDTxRxai - 325 ns td(TXENH-RXDH) - 325 ns uVDIG-OUT-UV - 500 mV VO(ERRN); with VIO < Vuvd(VIO) - 500 mV VO(RXD); with VIO < Vuvd(VIO) - 500 mV VO(RXEN); with VIO < Vuvd(VIO) - 500 mV valid operating modes when VBAT  5.5 V; VCC = nominal (if implemented) Normal, Receive only, Standby, Sleep valid operating modes when VBAT  7 V; VCC = nominal Normal, Receive only, Standby, Sleep TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 41 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver Table 18. EPL 3.0.1 to TJA1081G conversion …continued This table maps the EPL 3.0.1 parameters names to those in the TJA1081G. Values are provided for reference only (see the characteristics tables for comprehensive listings of guaranteed parameter values). EPL 3.0.1 Symbol uVDIG-OUT-OFF TJA1081G Min Max Unit product specific Symbol VO(ERRN) [4] Unit - 0.5 V V VIO  0.5 VIO V Zo(eq)TX 35 100  VO(RXEN) product-specific Max VIO  0.5 VIO VO(RXD)[4] RBDTransmitter Min [4] RxD signal sum of rise and fall time at TP4_CC 16.5 ns t(r+f)(RXD) (10 pF load on 50  strip; simulated) - 16.5 ns uVBAT-WAKE (no VCC) - 5.5 V VBAT (operating range) 4.75 60 V dBDRxDR25 + dBDRxDF25 - 16.5 ns t(r+f)(RXD) (25 pF load) - 16.5 ns dBDRxDR25  dBDRxDF25 - 5 ns t(r-f)(RXD) 5 +5 ns dBusTxDif - 3 ns t(r-f)(dif) (on bus) 3 +3 ns RxD signal difference of rise and fall time at TP4_CC - 5 ns t(r-f)(RXD) (10 pF load on 50  strip; simulated) - 5 ns [1] Vcm is the BP/BM common mode voltage (VBP + VBM/2) and is specified in conditions column for VIH(dif) and VIH(dif) for pins BP and BM; see Table 14. Vcm is tested on a receiving bus driver with a transmitting bus driver that has a ground offset voltage in the range 12.5 V to +12.5 V and that transmits a 50/50 pattern. [2] Min: Vo(idle)(BP) = Vo(idle)(BM) = 0.4VCC = 0.4  4.5 V = 1800 mV; max value: Vo(idle)(BP) = Vo(idle)(BM) = 0.6VCC = 0.6 5.25 V = 3150 mV; the nominal voltage is 2500 mV. [3] The nominal voltage is 0 mV. [4] Power off. TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 42 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 17. Abbreviations Table 19. Abbreviations Abbreviation Description BSS Byte Start Sequence CDM Charged Device Model ECU Electronic Control Unit EMC ElectroMagnetic Compatibility EME ElectroMagnetic Emission EMI ElectroMagnetic Immunity ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TSS Transmission Start Sequence 18. References [1] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 3.0.1, FlexRay Consortium [2] ISO 17458-4:2013 — Road vehicles - FlexRay Communications System part 4: Electrical physical layer specification [3] TJA1080A — FlexRay transceiver data sheet, www.nxp.com [4] TJA1081B — FlexRay transceiver data sheet, www.nxp.com [5] AH1102 — TJA1081B/TJA1081G FlexRay node transceiver application hints, available from NXP Semiconductors 19. Revision history Table 20. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1081G v.1 20161028 Product data sheet - - TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 43 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TJA1081G Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 44 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 20.4 Licenses Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. This NXP product contains functionality that is compliant with the FlexRay specifications. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. NXP ICs with FlexRay functionality These specifications and the material contained in them, as released by the FlexRay Consortium, are for the purpose of information only. The FlexRay Consortium and the companies that have contributed to the specifications shall not be liable for any use of the specifications. The material contained in these specifications is protected by copyright and other types of Intellectual Property Rights. The commercial exploitation of the material contained in the specifications requires a license to such Intellectual Property Rights. These specifications may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. For any other purpose, no part of the specifications may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher. The FlexRay specifications have been developed for automotive applications only. They have neither been developed nor tested for non-automotive applications. The word FlexRay and the FlexRay logo are registered trademarks. 20.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TJA1081G Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 28 October 2016 © NXP Semiconductors N.V. 2016. All rights reserved. 45 of 46 TJA1081G NXP Semiconductors FlexRay node transceiver 22. Contents 1 2 2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Low-power management . . . . . . . . . . . . . . . . . 1 2.3 Diagnosis (detection and signaling) . . . . . . . . . 2 2.4 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 2) . . . . . . . . . . . . . . . . . 2 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 Bus activity and idle detection . . . . . . . . . . . . . 6 7.1.2 Signaling on pin ERRN . . . . . . . . . . . . . . . . . . . 7 7.1.3 Signaling on pins RXEN and RXD . . . . . . . . . . 8 7.1.4 Operating mode transitions . . . . . . . . . . . . . . . 9 7.1.5 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1.6 Receive-only mode . . . . . . . . . . . . . . . . . . . . . 14 7.1.7 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1.8 Go-to-sleep mode . . . . . . . . . . . . . . . . . . . . . . 14 7.1.9 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 Wake-up mechanism . . . . . . . . . . . . . . . . . . . 15 7.2.1 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 15 7.2.1.1 Bus wake-up via wake-up pattern. . . . . . . . . . 15 7.2.1.2 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2.2 Local wake-up via pin WAKE . . . . . . . . . . . . . 16 7.3 Fail-silent behavior . . . . . . . . . . . . . . . . . . . . . 17 7.3.1 VBAT undervoltage . . . . . . . . . . . . . . . . . . . . . 17 7.3.2 VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 17 7.3.3 VIO undervoltage. . . . . . . . . . . . . . . . . . . . . . . 17 7.4 Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4.1 Local wake-up source flag . . . . . . . . . . . . . . . 17 7.4.2 Remote wake-up source flag . . . . . . . . . . . . . 17 7.4.3 Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.4 Power-on flag . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.5 Temperature medium flag . . . . . . . . . . . . . . . . 18 7.4.6 Temperature high flag . . . . . . . . . . . . . . . . . . . 18 7.4.7 TXEN clamped flag. . . . . . . . . . . . . . . . . . . . . 18 7.4.8 Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.9 UVVBAT flag . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4.10 7.4.11 7.5 8 9 10 11 12 13 13.1 14 15 15.1 15.2 15.3 15.4 16 17 18 19 20 20.1 20.2 20.3 20.4 20.5 21 22 UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . . UVVIO flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . Status register . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Appendix: EPL 3.0.1 to TJA1081G parameter conversion. . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 19 21 22 22 28 33 34 34 35 36 36 36 36 37 39 43 43 43 44 44 44 44 45 45 45 46 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2016. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 October 2016 Document identifier: TJA1081G