TJA1082TT,112

TJA1082 FlexRay node transceiver Rev. 6 — 28 November 2012 Product data sheet 1. General description The TJA1082 FlexRay node transceiver is compliant with the FlexRay electrical physical layer specification V2.1 Rev. B (see Ref. 1). In addition, it incorporates features and parameters included in V3.0.1 (see Ref. 2 and Section 14). It is primarily intended for communication systems operating at between 2.5 Mbit/s and 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1082 offers an optimized solution for Electronic Control Unit (ECU) applications that do not need enhanced power management and are typically switched by the ignition or activated by a dedicated wake-up line. The TJA1082 provides a differential transmit capability to the network and a differential receive capability to the FlexRay controller. It offers excellent ElectroMagnetic Compatibility (EMC) performance as well as high ElectroStatic Discharge (ESD) protection. The TJA1082 actively monitors system performance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring. 2. Features and benefits 2.1 Optimized for time triggered communication systems       Compliant with Electrical Physical Layer specification 2.1 Rev. B Automotive product qualification in accordance with AEC-Q100 (Grade 1) Data transfer at 2.5 Mbit/s, 5 Mbit/s and 10 Mbit/s Supports 60 ns minimum bit time at 400 mV differential voltage Very low ElectroMagnetic Emission (EME) to support unshielded cable Differential receiver with high common-mode range for excellent ElectroMagnetic Immunity (EMI)  Auto I/O level adaptation to host controller supply voltage VIO  Can be used in 14 V and 42 V powered systems  Instant shut-down interface (via BGE pin) 2.2 Low power management  Very low current consumption in Standby mode  Remote wake-up via a wake-up pattern or dedicated FlexRay data frames on the bus lines TJA1082 NXP Semiconductors FlexRay node transceiver 2.3 Diagnosis and robustness  Enhanced supply voltage monitoring for VCC and VIO  Two error diagnosis modes:  Status register readout via the Serial Peripheral Interface (SPI)  Simple error indication via pin ERRN  Overtemperature detection  Short-circuit detection on bus lines  Power-on flag  Clamping diagnosis for pins TXEN and BGE  Bus pins protected against 8 kV ESD pulses (according to IEC61000-4-2 and HBM)  Bus pins protected against transients in automotive environment (according to ISO 7637 class C)  Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground  Maximum differential voltage between pins BP or BM and any other pin of 60 V  Bus lines remain passive when the transceiver is not powered  No reverse currents from the digital input pins to VIO or VCC when the transceiver is not powered 2.4 FlexRay conformance classes  Bus driver - bus guardian interface  Bus driver logic level adaptation 3. Ordering information Table 1. Ordering information Type number TJA1082TT TJA1082 Product data sheet Package Name Description Version TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 2 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 4. Block diagram VCC VIO 14 VCC UNDERVOLTAGE DETECTION 1 TJA1082 VIO UNDERVOLTAGE DETECTION OVERTEMPERATURE DETECTION TXEN TIMEOUT TXEN 3 I/O 13 TXD 2 TRANSMITTER I/O 12 BP BM I/O STBN ERRN BGE SDO SCSN SCLK 6 10 5 8 9 7 I/O STATE MACHINE I/O I/O I/O LOW-POWER RECEIVER I/O SPI BUS ERROR I/O ACTIVITY DETECTION RXD 4 I/O NORMAL RECEIVER MUX 11 015aaa000 GND Fig 1. Block diagram TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 5. Pinning information 5.1 Pinning VIO 1 14 VCC TXD 2 13 BP TXEN 3 RXD 4 BGE 5 10 ERRN STBN 6 9 SCSN SCLK 7 8 SDO 12 BM TJA1082 11 GND 015aaa001 Fig 2. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Type Description VIO 1 P supply voltage for VIO voltage level adaptation TXD 2 I transmit data input; internal pull-down TXEN 3 I transmitter enable input; when HIGH transmitter disabled; internal pull-up RXD 4 O receive data output BGE 5 I bus guardian enable input; when LOW transmitter disabled; internal pull-down STBN 6 I mode control input; transceiver in Normal mode when HIGH; internal pull-down SCLK 7 I SPI clock signal; internal pull-up SDO 8 O SPI data output SCSN 9 I SPI chip select input; internal pull-up/pull-down ERRN 10 O error diagnosis output and wake-up indication GND 11 P ground BM 12 I/O bus line minus BP 13 I/O bus line plus VCC 14 P supply voltage (+5 V) 6. Functional description 6.1 Power modes The TJA1082 features three power modes: Normal, Standby and Power-off. Normal and Standby modes can be selected via the STBN input (HIGH for Normal mode) once the transceiver has been powered up. See Table 3 for a detailed description of pin signaling in the three power modes. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 4 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 3. Mode Pin signalling in the different power modes STBN UV at UV VIO at VCC ERRN RXD LOW HIGH LOW Normal HIGH no no error error flag flag set reset Standby LOW no no wake wake flag flag set reset LOW no yes[3] wake wake flag flag set[4] reset[4] bus bus highVCC / 2 DATA_ DATA_1 impedance 0 or idle (in simple error wake wake GND indication flag flag mode) or set reset enabled (in wake wake SPI mode) flag flag set[4] reset[4] yes[3] error error flag flag set reset wake flag set[4] HIGH no Power-off[6] X yes[5] no LOW LOW X yes[5] LOW LOW X X[5] yes[3] yes highimpedance SDO HIGH Biasing BP, BM UV-det Transmitter Lowpower receiver enabled enabled enabled[1] disabled enabled[2] disabled wake flag reset[4] enabled[2] highimpedance HIGH disabled GND[7] [1] The wake flag is set if a valid wake-up event is detected while switching to Standby mode. [2] The wake flag is set if a valid wake-up event is detected. disabled disabled [3] Vuvd(VCC) > VCC > Vth(det)POR. [4] Pins ERRN and RXD reflect the state of the wake flag prior to the VCC undervoltage event. [5] The internal signals at pins STBN, BGE and TXD are set LOW; the internal signals at pins TXEN, SCLK and SCSN are set HIGH. [6] VCC < Vth(rec)POR at power-up and VCC < Vth(det)POR at power-down (see Figure 6 and Figure 7). [7] Except when VCC = 0; in this case BP and BM are floating. 6.1.1 Normal mode In Normal mode, the transceiver transmits and receives data via the bus lines BP and BM. The transmitter and the normal receiver are enabled, along with the undervoltage detection function. The timing diagram for Normal mode is illustrated in Figure 3. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 5 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver TXD BGE TXEN BP BM RXD 015aaa002 Fig 3. Timing diagram in Normal mode Table 4 describes the behavior of the transmitter in Normal mode, when the temperature flag (TEMP HIGH) is not set and with no time-out on pin TXEN. Transmitter behavior is illustrated in Figure 14. Table 4. Transmitter operation in Normal mode BGE TXEN TXD Bus state Transmitter L X X idle transmitter is disabled X H X idle transmitter is disabled H L H DATA_1 transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW H L L DATA_0 transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH The transmitter is activated during the first LOW level on pin TXD while pin BGE is HIGH and pin TXEN is LOW. In Normal mode, the normal receiver output is connected directly to pin RXD (see Table 5). Receiver behavior is illustrated in Figure 15. Table 5. Behavior of normal receiver in Normal mode Bus state RXD DATA_0 L DATA_1 H idle H When VIO and VCC are within their operating ranges, pin ERRN indicates the status of the error flag. See Section 6.8 for a detailed description of error signalling in Normal mode. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 6 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 6.1.1.1 Bus activity and idle detection In Normal mode, bus activity and bus idle are detected as follows: • Bus activity is detected when the absolute differential voltage on the bus lines is higher than Vi(dif)det(act) for tdet(act)(bus): – If the differential voltage on the bus lines is lower than VIL(dif) after bus activity has been detected, pin RXD switches LOW. – If the differential voltage on the bus lines is higher than VIH(dif) after bus activity has been detected, pin RXD remains HIGH. • Bus idle is detected when the absolute differential voltage on the bus lines is lower than Vi(dif)det(act) for tdet(idle)(bus). This results in pin RXD being switched HIGH or staying HIGH. 6.1.2 Standby mode Standby mode is a low-power mode featuring very low current consumption. In Standby mode, the transceiver is unable to transmit or receive data since both the transmitter and the normal receiver are switched off. The low-power receiver is activated to monitor the bus for wake-up activity, provided an undervoltage has not been detected on pin VCC. The low-power receiver is deactivated if an undervoltage is detected on pin VCC - with the result that the wake flag is not set if a wake-up pattern or dedicated data frame is received. Pins ERRN and RXD indicate the status of the wake flag when VIO and VCC are within their operating ranges. See Table 3 for a description of pins ERRN and RXD when an undervoltage is detected on pin VIO or pin VCC. The status register cannot be read via the SPI interface if an undervoltage is detected on pin VIO. The BGE input has no effect in Standby mode. 6.1.3 Power-off mode The transmitter and the two receivers (normal and low-power) are deactivated in Power-off mode. As a result, the wake flag is not set if a wake-up pattern or dedicated data frame is received. If the voltage at VCC rises above Vth(rec)POR, the transceiver switches to Standby mode and the digital section is reset. If VCC subsequently drops below Vth(det)POR, the transceiver reverts to Power-off mode (see Section 6.2). The status register cannot be read via the SPI interface in Power-off mode. 6.1.4 State transitions Figure 4 shows the TJA1082 state transition diagram. The timing diagram for the ERRN indication signal during transitions between Normal and Standby modes, when the error flag is set and the wake flag is not set, is illustrated in Figure 5 and described in Table 6. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 7 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver NORMAL STBN -> LOW or UVVCC flag set or UVVIO flag set (STBN -> HIGH while UV flags cleared) or (UV flags cleared while STBN = HIGH) STANDBY VCC < Vth(det)POR VCC > Vth(rec)POR POWER OFF 015aaa004 Fig 4. State transitions diagram 20 μs STBN td(norm-stb) td(stb-norm) ERRN 015aaa003 Fig 5. TJA1082 Product data sheet State transitions timing (error flag set) All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 8 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 6. State transitions  indicates the action that initiates a transaction; 1 and 2 are the consequences of a transaction. Transition UVVIO flag[1] UVVCC flag[1] wake flag[1] PWON flag[1] STBN Normal to Standby cleared cleared cleared cleared L VCC > Vuvd(VCC)  set cleared cleared cleared H VCC > Vuvd(VCC) cleared  set cleared cleared H Vuvd(VCC) > VCC > Vth(det)POR cleared cleared 1  cleared 2  cleared H VCC > Vuvd(VCC)  cleared cleared 1  cleared 2  cleared H VCC > Vuvd(VCC) cleared  cleared 1  cleared 2  cleared H Vuvd(VCC) > VCC > Vth(det)POR Standby to Power-off X set X X X  VCC < Vth(det)POR Power-off to Standby X set X 1  set X  VCC > Vth(rec)POR Standby to Normal [1] VCC level See Table 7 for set and reset conditions of all flags. 6.2 Power-up and power-down behavior 6.2.1 Power-up The TJA1082 has two supply pins: VCC (+5 V) and VIO (for the voltage level adaptation). The ramp up of the different power supplies can vary, depending on the state or value of a number of signals and parameters. The power-up behavior of the TJA1082 is not affected by the sequence in which power is supplied to these pins or by the voltage ramp up. As an example, Figure 6 shows one possible power supply ramp-up scenario. The digital section of the TJA1082 is supplied by VCC. The voltage on pin VCC ramps up before the voltage on pin VIO. As long as the voltage on VCC remains below the power-on reset recovery threshold, Vth(rec)POR, the internal state machine is not active and the transceiver is totally passive, remaining in Power-off mode. As soon as the voltage crosses the Vth(rec)POR threshold, the internal state machine starts running, setting the PWON flag and switching the TJA1082 to Standby mode. This initializes the VCC and VIO under-voltage flags to the set state (since both VCC and VIO are actually in undervoltage state just after power-on). Once both VIO and VCC have reached their operating ranges, the under-voltage flags are reset. The operating mode is then determined by the level on STBN (the TJA1082 switches to Normal mode if STBN is HIGH and remains in Standby mode if STBN is LOW), provided VIO and VCC are above their respective undervoltage recovery levels (Vuvr(VIO) and Vuvr(VCC)). TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 9 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Power-off Standby Normal Vuvr(VCC) Vth(rec)POR VCC Vuvr(VIO) VIO STBN RXD ERRN 015aaa005 Fig 6. Power-up behavior (example) 6.2.2 Power-down The behavior of the TJA1082 during power-down is illustrated in Figure 7. Standby Normal Power-off Vuvd(VCC) Vth(det)POR VCC Vuvd(VIO) VIO STBN RXD ERRN 015aaa006 Fig 7. TJA1082 Product data sheet Power-down behavior (example) All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 10 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 6.3 Remote wake-up 6.3.1 Bus wake-up via wake-up pattern A valid remote wake-up event occurs when a wake-up pattern is received. A wake-up pattern consists of at least two consecutive wake-up symbols. A wake-up symbol consists of a DATA_0 phase lasting longer than tdet(wake)DATA_0, followed by an idle phase lasting longer than tdet(wake)idle, provided both wake-up symbols occur within a time span of tdet(wake)tot (see Figure 8). The transceiver also wakes up if the idle phases are replaced by DATA_1 phases. wake-up < tdet(wake)tot Vdif (mV) > tdet(wake)idle > tdet(wake)idle 0 -500 > tdet(wake)DATA_0 > tdet(wake)DATA_0 > tdet(wake)idle > tdet(wake)idle +500 0 -500 > tdet(wake)DATA_0 > tdet(wake)DATA_0 wake-up symbol wake-up symbol wake-up pattern 015aaa007 Fig 8. Bus wake-up timing The wake-up mechanism of the TJA1082 follows the state transition diagram shown in Figure 9. See Ref. 1 for more details of the wake-up mechanism. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 11 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver power on Wait I' DATA_1 or idle on bus start tdet(wake)idle DATA_0 for longer than tsup(int)wake tdet(wake)idle expired Wait S' DATA_0 on bus DATA_1 or idle for longer than tsup(int)wake tdet(wake)Data_0 expired tdet(wake)tot expired Wait A' DATA_1 or idle on bus Initial state start tdet(wake)Data_0 start tdet(wake)idle tdet(wake)tot expired DATA_0 for longer than tsup(int)wake tdet(wake)idle expired tdet(wake)tot expired Wait B' DATA_0 on bus DATA_1 or idle for longer than tsup(int)wake tdet(wake)Data_0 expired tdet(wake)tot expired Wait C' DATA_1 or idle on bus tdet(wake)tot expired Start state Wait state A start tdet(wake)Data_0 Wait state B start tdet(wake)idle tdet(wake)tot expired DATA_0 for longer than tsup(int)wake Wait state C Wake-up! tdet(idle)wake expired Fig 9. 015aaa008 Wake-up state machine 6.3.2 Bus wake-up via dedicated FlexRay data frame The TJA1082 wake flag is set when a dedicated data frame emulating a valid wake-up pattern, as shown in Figure 10, is received. The DATA_0 and DATA_1 phases of the emulated wake-up symbol are interrupted by the Byte Start Sequence (BSS) preceding each byte in the data frame. With a data rate of 10 Mbit/s, the interruption has a maximum duration of 130 ns and does not prevent the transceiver from recognizing the wake-up pattern in the payload. For longer interruptions at lower data rates (5 Mbit/s and 2.5 Mbit/s), the wake-up pattern should be used (see Section 6.3.1). The wake flag is not set if an invalid wake-up pattern is received. See Ref. 1 for more details on invalid wake-up patterns. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 12 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Vdif 130 ns wake-up 870 ns 870 ns +1500 0V −1500 770 870 870 ns ns ns 130 130 ns ns 5 μs 5 μs 5 μs 5 μs 015aaa097 The duration of each interruption is 130 ns. The transition time from DATA_0 to DATA_1 and vice versa is about 20 ns. The TJA1082 wake-up flag is set on receipt of the following frame payload: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF Fig 10. Minimum bus pattern for bus wake-up via dedicated FlexRay data frame 6.4 Bus error detection The TJA1082 detects the following bus errors during transmission: • • • • • Short-circuit BP to BM at the ECU connector or on the bus Short-circuit BP to GND at the ECU connector or on the bus Short-circuit BM to GND at the ECU connector or on the bus Short-circuit BP to VCC at the ECU connector or on the bus Short-circuit BM to VCC at the ECU connector or on the bus The bus error flag is not set when a wake-up pattern or a FlexRay Collision Avoidance Symbol (CAS) is being transmitted or received. 6.5 Fail silent behavior Three mechanisms guarantee the ‘fail silent’ behavior of the TJA1082: • The TXEN Clamped flag is set if pin TXEN goes LOW for longer than tdetCL(TXEN) in Normal mode; the transmitter is disabled. • The BGE Clamped flag is set if pin BGE goes HIGH for longer than tdetCL(BGE) in Normal mode; no action is taken. • If a loss-of-ground occurs at the transceiver, resulting in the TJA1082 switching to Power-off mode, no current flows out of the digital input pins (TXD, TXEN, BGE, STBN, SCLK, SCSN); see Table 3 for details of the behavior of the bus pins. 6.6 TJA1082 flags The TJA1082 has 11 status/error flags. These are described in Table 7. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 13 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 7. TJA1082 flags and set/reset conditions Flag name Flag type Flag description Set condition Reset condition[1] Consequence of flag set bus wake status flag indicates if a wake-up event has occurred wake-up event on bus in Standby mode[2] transition to Normal mode RXD  LOW; ERRN  LOW [3] Normal mode status flag indicates if the transceiver entering Normal mode is in Normal mode leaving Normal mode - transmitter status enabled flag indicates the transmitter status transmitter enabled[4] transmitter disabled - BGE clamped status flag indicates if pin BGE is clamped BGE HIGH for longer than tdetCL(BGE)[5] BGE LOW[5] - PWON status flag indicates when the digital section is initialized VCC > Vth(rec)POR transition to Normal mode - bus error error flag indicates if a bus error has bus error detected[5] been detected TEMP HIGH error flag indicates if the max. junction temperature has been reached Tvj > Tj(dis)(high)[5] TXEN = HIGH while Tvj < Tj(dis)(high)[5] ERRN  LOW [6]; transmitter disabled TXEN clamped error flag indicates if pin TXEN is clamped TXEN LOW for longer than tdetCL(TXEN)[5] TXEN = HIGH[5] ERRN  LOW [6]; transmitter disabled UVVCC error flag indicates if there is an undervoltage at pin VCC VCC < Vuvd(VCC) for longer than tdet(uv)(VCC) VCC > Vuvr(VCC) for longer than trec(uv)(VCC) ERRN  LOW [6]; entering Standby mode UVVIO error flag indicates if there is an undervoltage at pin VIO VIO < Vuvd(VIO) for longer than tdet(uv)(VIO) VIO > Vuvr(VIO) for longer ERRN  LOW [6]; than trec(uv)(VIO) entering Standby mode SPI error error flag indicates if an SPI error has occurred SPI error detected[8] falling edge on SCSN [1] no bus error detected or ERRN  LOW [6] positive edge on TXEN[5] ERRN  LOW [7]; SDO goes to a high impedance state All flags, with the exception of the PWON flag, are reset after a power-on reset. [2] If an undervoltage has not been detected on pin VCC. [3] If STBN = LOW. [4] If BGE = HIGH, the Normal mode flag is set, the TEMP HIGH flag is not set and the TXEN clamped flag is not set. [5] Flag can only be set or reset in Normal mode or on leaving Normal mode. [6] If STBN = HIGH. [7] If STBN = HIGH in SPI mode [8] The SPI error flag is set when: a) more than 16 falling edges occur on pin SCLK while pin SCSN = LOW b) less than 16 falling edges occur on pin SCLK while pin SCSN = LOW. 6.7 TJA1082 status register The TJA1082 contains a 16-bit status register, of which bits S0 to S4 reflect the state of the status flags, bits S5 to S10 reflect the state of the error flags and bit S15 is a parity bit. All flags can be individually read out on pin SDO via a 16-bit SPI interface when the transceiver is configured in SPI mode. The status register bits are described in Table 8. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 14 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 8. TJA1082 status register Status bit Flag name Set condition S0 bus wake bus wake flag set bus wake flag cleared S1 Normal mode Normal mode flag set Normal mode flag cleared S2 transmitter transmitter enabled flag set enabled transmitter enabled flag cleared S3 BGE clamped BGE clamped flag set BGE clamped flag cleared S4 PWON PWON flag set PWON flag cleared and successful readout[1] S5 bus error bus error flag set bus error flag cleared and successful readout[1] S6 TEMP HIGH TEMP HIGH flag set TEMP HIGH flag cleared and successful readout[1] S7 TXEN clamped TXEN clamped flag set TXEN clamped flag cleared and successful readout[1] S8 UVVCC UVVCC flag set UVVCC flag cleared and successful readout[1] S9 UVVIO UVVIO flag set UVVIO flag cleared and successful readout[1] S10 SPI error SPI error flag set SPI error flag cleared and successful readout[1] S11 reserved always LOW S12 reserved always HIGH S13 reserved always LOW S14 reserved always HIGH S15 parity bit odd parity of status bits [1] Reset condition even parity of status bits Also cleared during Power-off. 6.8 Error signalling The TJA1082 provides two modes for error indication: • SPI mode (default mode) • Simple error indication mode SPI mode is active on power-up. To switch to simple error indication mode, SCSN has to be held LOW (connected to GND) and SCLK held HIGH (connected to VIO) for longer than tdet(L)(SCLK) (provided a VIO undervoltage has not occurred). When the TJA1082 is in simple error indication mode, a rising edge on SCSN initiates a transition to SPI mode (provided a VIO undervoltage has not occurred). TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 15 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver SPI mode SCSN (V) VIO simple error indication mode SPI mode 0 t SCLK (V) VIO 0 t tdet(L)(SCLK) Fig 11. 015aaa015 Timing diagram for configuration of error indication mode If a VIO undervoltage condition is detected, it is not possible to switch between SPI mode and simple error indication mode. 6.8.1 SPI mode The error flag information in the status register is latched in SPI mode. This means that the status bit is reset once the status register has been completely read (provided the corresponding error flag has been reset). If an error condition is detected in Normal mode, pin ERRN goes LOW (provided one of the error bits, S5-S10, is set). Pin ERRN goes HIGH again once all the error bits (S5-S10) have been reset. 6.8.2 Simple error indication mode If an error condition is detected in Normal mode, pin ERRN goes LOW once the relevant error flag has been set. Pin ERRN goes HIGH again when all error conditions have been cleared and all flags have been reset. Error flags are not latched. It is not possible to read-out the status bits in this mode. 6.9 SPI interface The TJA1082 includes a 16-bit SPI interface to enable a host to read the status register when the transceiver is in SPI mode (see Section 6.8). While pin SCSN is HIGH, the SDO output is in a high-impedance state. To begin a status register readout, the host must force pin SCSN LOW. This causes the SDO pin to output a LOW level by default. The data at pin SDO is then shifted out on the rising edge of the clock signal on pin SCLK. The status bits shifted out at SDO are active HIGH. The status bits are refreshed and pin SDO returned to a high-impedance state once the status register has been read successfully (after exactly 16 clock cycles) and SCSN has been forced HIGH again. Clock signals on SCLK are ignored while SCSN is HIGH. The timing diagram for the SPI readout is illustrated in Figure 12. The SLCK period ranges from 500 ns to 100 s (10 kbit/s to 2 Mbit/s). TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 16 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver If SCSN remains LOW for longer than 16 clock cycles, it recognized as an SPI error. When this happens, the SPI error flag is set and pin SDO goes to a high-impedance state until the next falling edge on pin SCSN. An SPI error is also assumed if fewer than 16 clock cycles are received while SCSN is LOW. If this happens, the SPI error flag is set. All status bits are refreshed once the status register has been successfully read. When the transceiver is in simple error indication mode the SDO output is in a high-impedance state and pin SCSN is in pull-down mode. In SPI mode pin SCSN is in pull-up mode. SPI readout is not possible when the transceiver has detected an undervoltage on VIO. SCSN tSPILEAD SCLK 01 td(SCSNHL-SDOL) SDO TSCLK 02 tSPILAG 03 15 16 td(SCSNLH-SDOZ) td(SCLKLH-SDODV) Z L S0 S1 S2 S14 S15 Z 015aaa009 Fig 12. SPI readout timing diagram 7. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit VCC supply voltage no time limit 0.3 +5.5 V VIO supply voltage on pin VIO no time limit 0.3 +5.5 V VERRN voltage on pin ERRN no time limit 0.3 VIO + 0.3 V VRXD voltage on pin RXD no time limit 0.3 VIO + 0.3 V VSDO voltage on pin SDO no time limit 0.3 VIO + 0.3 V VTXEN voltage on pin TXEN no time limit 0.3 +5.5 V VTXD voltage on pin TXD no time limit 0.3 +5.5 V VSTBN voltage on pin STBN no time limit 0.3 +5.5 V VSCSN voltage on pin SCSN no time limit 0.3 +5.5 V VSCLK voltage on pin SCLK no time limit 0.3 +5.5 V VBGE voltage on pin BGE no time limit 0.3 +5.5 V VBP voltage on pin BP no time limit (with respect to pins BM and GND) 60 +60 V TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 17 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit VBM voltage on pin BM no time limit (with respect to pins BP and GND) 60 +60 V II(ERRN) input current on pin ERRN no time limit; VIO = 0 V 10 10 mA II(RXD) input current on pin RXD no time limit; VIO = 0 V 10 10 mA II(SDO) input current on pin SDO no time limit; VIO = 0 V transient voltage Vtrt on pins BM and BP 10 10 mA [1] 100 - V [2] - 75 V [3] 150 - V [4] - 100 V 55 +150 C storage temperature Tstg Tvj virtual junction temperature VESD electrostatic discharge voltage [5] 40 +150 C IEC61000-4-2 on pins BP and BM to ground [6] 8.0 +8.0 kV HBM on pins BP and BM to ground [7] 8.0 +8.0 kV HBM on any other pin [7] 4.0 +4.0 kV MM on all pins [8] 200 +200 V CDM on all pins [9] 1000 +1000 V [1] According to ISO7637, test pulse 1, class C; verified by an external test house. [2] According to ISO7637, test pulse 2a, class C; verified by an external test house. [3] According to ISO7637, test pulse 3a, class C; verified by an external test house. [4] According to ISO7637, test pulse 3b, class C; verified by an external test house. [5] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + TD x Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [6] IEC61000-4-2: C = 150 pF; R = 330 . [7] HBM: C = 100 pF; R = 1.5 k. [8] MM: C = 200 pF; L = 0.75 H; R = 10 . [9] CDM: R = 1 . 8. Thermal characteristics Table 10. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 130 K/W TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 18 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 9. Static characteristics Table 11. Static characteristics All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit supply current Standby mode with no undervoltage; Tvj  85 C - 20 30 A Standby mode with no undervoltage; Tvj  150 C - 20 40 A Power-off mode; Tvj  85 C - - 30 A Power-off mode; Tvj  150 C - - 40 A Normal mode; VBGE = 0 V or VTXEN = VIO - - 15 mA Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus  45  - - 35 mA Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus > 10 M - - 15 mA Pin VCC ICC Vuvd(VCC) undervoltage detection voltage on pin VCC 4.5 - 4.729 V Vuvr(VCC) undervoltage recovery voltage on pin VCC 4.52 - 4.749 V Vuvhys(VCC) undervoltage hysteresis voltage on pin VCC 20 - 240 mV Vth(det)POR power-on reset detection threshold voltage 3.75 - 4.15 V Vth(rec)POR power-on reset recovery threshold voltage 3.85 - 4.25 V Vhys(POR) power-on reset hysteresis voltage 100 - 500 mV Normal mode; VTXEN = VIO; VBGE = VIO; RRXD > 10 M - - 1000 A Normal mode; VTXEN = 0 V; VBGE = VIO; RRXD > 10 M - - 1000 A Standby mode with no undervoltage - 2.2 7 A Power-off mode; VIO = 5 V - 3 7 A Pin VIO IIO supply current on pin VIO Vuvd(VIO) undervoltage detection voltage on pin VIO 2.6 - 2.779 V Vuvr(VIO) undervoltage recovery voltage on pin VIO 2.62 - 2.799 V Vuvhys(VIO) undervoltage hysteresis voltage on pin VIO 20 - 190 mV VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V Pin SCSN TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 19 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 11. Static characteristics …continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit IIH HIGH-level input current simple error indication mode; VSCSN = 0.7VIO 3 - 15 A IIL LOW-level input current SPI mode; VSCSN = 0.3VIO 15 - 3 A Ir reverse current Power-off mode; to VCC / VIO; VSCSN = 5 V; VCC = VIO = 0 V 5 0 +5 A Pin SCLK VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VSCLK = VIO 1 0 +1 A IIL LOW-level input current VSCLK = 0.3VIO 15 - 3 A Ir reverse current Power-off mode; to VCC / VIO; VSCLK = 5 V; VCC = VIO = 0 V 5 0 +5 A Pin STBN VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VSTBN = 0.7VIO 3 - 15 A IIL LOW-level input current VSTBN = 0 V 1 0 +1 A Ir reverse current Power-off mode; to VCC / VIO; VSTBN = 5 V; VCC = VIO = 0 V 5 0 +5 A 0.7VIO - VIO + 0.3 V Pin TXEN VIH HIGH-level input voltage VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VTXEN = VIO 1 0 +1 A IIL LOW-level input current VTXEN = 0.3VIO 300 - 50 A Ir reverse current Power-off mode; to VCC / VIO; VTXEN = 5 V; VCC = VIO = 0 V 5 0 +5 A Pin BGE VIH HIGH-level input voltage 0.7VIO - 5.5 V VIL LOW-level input voltage 0.3 - 0.3VIO V IIH HIGH-level input current VBGE = 0.7VIO 3 - 15 A IIL LOW-level input current VBGE = 0 V 1 0 +1 A Ir reverse current Power-off mode; to VCC / VIO; VBGE = 5 V; VCC = VIO = 0 V 5 0 +5 A VIH HIGH-level input voltage Normal mode 0.7VIO - VIO + 0.3 V VIL LOW-level input voltage Normal mode 0.3 - 0.3VIO V IIH HIGH-level input current VTXD = 0.7VIO 3 - 15 A IIL LOW-level input current VTXD = 0 V 1 0 +1 A Ir reverse current Power-off mode; to VCC / VIO; VTXD = 5 V; VCC = VIO = 0 V 5 0 +5 A Pin TXD TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 20 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 11. Static characteristics …continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Ci Parameter input capacitance Conditions with respect to all other pins at ground; VTXD = 100 mV; f = 5 MHz [1] Min Typ Max Unit - - 10 pF Pin RXD IOH HIGH-level output current VRXD = VIO  0.4 V; VIO = VCC 15 - 1.7 mA IOL LOW-level output current 2 - 20 mA VRXD = 0.4 V Pin ERRN IOH HIGH-level output current VERRN = VIO  0.4 V; VIO = VCC 1500 - 100 A IOL LOW-level output current VERRN = 0.4 V 200 - 1700 A IL leakage current Power-off mode; VERRN  VIO 5 - +5 A Pin SDO IOH HIGH-level output current VSDO = VIO  0.4 V 8 3 0.5 mA IOL LOW-level output current VSDO = 0.4 V 0.8 3 9 mA IL leakage current high-impedance state; 0 V < VSDO < VIO 5 - +5 A Normal mode; VTXEN = VIO; Rbus = 45  0.4VCC 0.5VCC 0.6VCC V Standby mode with no undervoltage on pin VCC 0.1 V Pins BP and BM Vo(idle)(BP) Vo(idle)(BM) idle output voltage on pin BP idle output voltage on pin BM 0 +0.1 Normal mode; VTXEN = VIO; Rbus = 45  0.4VCC 0.5VCC 0.6VCC V Standby mode with no undervoltage on pin VCC 0.1 0 +0.1 V Io(idle)BP idle output current on pin BP Normal and Standby modes with no undervoltage; 60 V  VBP  +60 V 7.5 - +7.5 mA Io(idle)BM idle output current on pin BM Normal and Standby modes with no undervoltage; 60 V  VBM  +60 V 7.5 - +7.5 mA Vo(idle)(dif) differential idle output voltage Normal mode; Rbus = 45  25 0 +25 mV VOH(dif) differential HIGH-level output voltage Normal mode; 40   Rbus  55 ; Cbus = 100 pF 600 1000 1500 mV VOL(dif) differential LOW-level output voltage Normal mode; 40   Rbus  55 ; Cbus = 100 pF 1500 1000 600 mV VIH(dif) differential HIGH-level input voltage Normal mode; 10 V  VBP  +15 V; 10 V  VBM  +15 V 150 225 300 mV VIL(dif) differential LOW-level input voltage Normal mode; 10 V  VBP  +15 V; 10 V  VBM  +15 V 300 225 150 mV Standby mode with no undervoltage on pin VCC; 10 V  VBP  +15 V; 10 V  VBM  +15 V 400 225 125 mV 150 225 300 mV Vi(dif)det(act) activity detection differential input voltage (absolute value) TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 21 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 11. Static characteristics …continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit IO(sc) short-circuit output current (absolute value) on pin BP; 5 V  VBP  +60 V - - 35 mA on pin BM; 5 V  VBM  +60 V - - 35 mA on pins BP and BM; VBP = VBM; 5 V  VBP  +60 V; 5 V  VBM  +60 V - - 35 mA Ri(BP) input resistance on pin BP Rbus =   10 20 40 k Ri(BM) input resistance on pin BM Rbus =   10 20 40 k Ri(dif)(BP-BM) differential input resistance between pin BP and pin BM Rbus =   20 40 80 k ILI(BP) input leakage current on pin BP Power-off mode; VCC = VIO = 0 V; 0 V  VBP  5 V 5 0 +5 A 1600 - +1600 A 5 0 +5 A 1600 - +1600 A loss of ground; VBP = VBM = 0 V; all other pins connected to 16 V via 0  ILI(BM) input leakage current on pin BM [1] Power-off mode; VCC = VIO = 0 V; 0 V  VBM  5 V loss of ground; VBP = VBM = 0 V; all other pins connected to 16 V via 0  [1] Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage Normal mode; Rbus = 45  0.4VCC 0.5VCC 0.6VCC V Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Normal mode; Rbus = 45  0.4VCC 0.5VCC 0.6VCC V Vcm(bus) bus common-mode voltage difference Normal mode; DATA_1  DATA_0; Rbus = 45  25 0 +25 mV Vcm(act-idle) active to idle common-mode voltage difference Normal mode; Rbus = 45  300 0 +300 mV Vi(dif)(H-L) differential input voltage difference between HIGH-level and LOW-level Normal mode; (VBP + VBM)/2 = 2.5 V - - 10 % Ci(BP) input capacitance on pin BP with respect to all other pins at ground; VBP = 100 mV; f = 5 MHz [1] - - 15 pF Ci(BM) input capacitance on pin BM with respect to all other pins at ground; VBM = 100 mV; f = 5 MHz [1] - - 15 pF Ci(dif)(BP-BM) differential input capacitance between pin BP and pin BM with respect to all other pins at ground; VBP = 100 mV; VBM = 100 mV; f = 5 MHz [1] - - 5 pF 180 - 200 C Temperature protection Tj(dis)(high) [1] high disable junction temperature Guaranteed by design. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 22 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 10. Dynamic characteristics Table 12. Dynamic characteristics All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit delay time from TXD to bus Normal mode - - 50 ns - - 50 ns 4 - +4 ns DATA_0 - - 50 ns DATA_1 - - 50 ns DATA_0 - - 60 ns DATA_1 - - 60 ns CRXD = 15 pF 5 - 5 ns CRXD = 25 pF 6 - 6 ns - - 75 ns - - Pins BP and BM td(TXD-bus) [1][2] DATA_0 DATA_1 td(TXD-bus) delay time difference from TXD to bus Normal mode; between DATA_0 and DATA_1 td(bus-RXD) delay time from bus to RXD Normal mode; CRXD = 15 pF; (VBP + VBM)/2 = 2.5 V Normal mode; CRXD = 25 pF; (VBP + VBM)/2 = 2.5 V td(bus-RXD) delay time difference from bus to RXD Normal mode; between DATA_0 and DATA_1; (VBP + VBM)/2 = 2.5 V [1][2] [3] [3] [3] td(TXEN-busidle) delay time from TXEN to bus idle Normal mode; VTXD = 0 V td(TXEN-busact) delay time from TXEN to bus active Normal mode; VTXD = 0 V td(TXEN-bus) delay time difference from TXEN to bus Normal mode; between TXEN (absolute value) to bus active and TXEN to bus idle; VTXD = 0 V td(BGE-busidle) delay time from BGE to bus idle Normal mode; VTXD = 0 V - td(BGE-busact) delay time from BGE to bus active Normal mode; VTXD = 0 V - 75 ns 50 ns - 75 ns - 75 ns 3.75 - 18.75 ns [4] tr(dif)(bus) bus differential rise time DATA_0 to DATA_1; 20 % to 80 %; Rbus = 45 ; Cbus = 100 pF [5] tf(dif)(bus) bus differential fall time DATA_1 to DATA_0; 80 % to 20 %; Rbus = 45 ; Cbus = 100 pF [5] 3.75 - 18.75 ns t(r-f)(dif) difference between differential rise and fall time on bus; 80 % to 20 % Rbus = 45 ; Cbus = 100 pF [5] 3 - 3 ns tf(bus)(idle-act) bus fall time from idle to active bus idle to DATA_0; Rbus = 45 ; Cbus = 100 pF; 30 mV > Vdif > 300 mV [5][6] - - 30 ns tf(bus)(act-idle) bus fall time from active to idle DATA_1 to bus idle; Rbus = 45 ; Cbus = 100 pF; 300 mV > Vdif > 30 mV [5][6] - - 30 ns TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 23 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 12. Dynamic characteristics …continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol tr(bus)(act-idle) Parameter Conditions bus rise time from active to idle Min Typ Max Unit DATA_0 to bus idle; Cbus = 100 pF 300 mV < Vdif < 30 mV [5][6] - - 30 ns Wake-up detection tdet(wake)DATA_0 DATA_0 wake-up detection time Standby mode with no undervoltage on pin VCC; 10 V  VBP  +15 V; 10 V  VBM  +15 V [7] 1 - 4 s tdet(wake)idle idle wake-up detection time Standby mode with no undervoltage on pin VCC; 10 V  VBP  +15 V; 10 V  VBM  +15 V [7] 1 - 4 s tdet(wake)tot total wake-up detection time Standby mode with no undervoltage on pin VCC; 10 V  VBP  +15 V; 10 V  VBM  +15 V [7] 50 - 115 s tsup(int)wake wake-up interruption suppression time Standby mode with no undervoltage on pin VCC; 10 V  VBP  +15 V; 10 V  VBM  +15 V [8] 130 - - ns tdet(uv)(VCC) undervoltage detection time on pin VCC 0 V  VIO  5.5 V; VCC = 4.4 V 2 - 100 s trec(uv)(VCC) undervoltage recovery time on pin VCC 0 V  VIO  5.5 V; VCC = 4.85 V 2 - 100 s tdet(uv)(VIO) undervoltage detection time on pin VIO Vth(det)POR < VCC < 5.5 V; VIO = 2.5 V 5 - 100 s trec(uv)(VIO) undervoltage recovery time on pin VIO Vth(det)POR < VCC < 5.5 V; VIO = 2.9 V 5 - 100 s Undervoltage Activity detection tdet(act)(bus) activity detection time on bus pins Normal mode; Vdif: 0 mV  400 mV; (VBP + VBM)/2 = 2.5 V [6] 100 - 250 ns tdet(idle)(bus) idle detection time on bus pins Normal mode; Vdif: 400 mV  0 mV; (VBP + VBM)/2 = 2.5 V [6] 100 - 250 ns tdet(act-idle) active to idle detection time difference (absolute value) Normal mode; on bus pins; (VBP + VBM)/2 = 2.5 V - - 150 ns LOW-level detection time on pin SCLK Normal or Standby mode with no undervoltage on pin VIO 95 - 310 s SCSN falling edge to SDO LOW-level delay time Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF - - 250 ns ERRN signalling tdet(L)(SCLK) SPI td(SCSNHL-SDOL) TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 [9] © NXP B.V. 2012. All rights reserved. 24 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver Table 12. Dynamic characteristics …continued All parameters are guaranteed for VCC = 4.5 V to 5.25 V; VIO = 2.6 V to 5.25 V; Tvj = 40 C to +150 C and Rbus = 45  unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit - - 200 ns td(SCLKLH-SDODV) SCLK rising edge to SDO data valid delay time Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF [9] td(SCSNLH-SDOZ) SCSN rising edge to SDO three-state delay time Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF [9] - - 500 ns TSCLK SCLK period Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF [9] 0.5 - 100 s tSPILEAD SPI enable lead time Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF [9] 250 - - ns tSPILAG SPI enable lag time Vuvd(VIO) < VIO < 5.5 V; 4.5 V < VCC < 5.5 V; CSDO = 50 pF [9] 250 - - ns rise time 20 % to 80 %; CRXD = 15 pF [4] - - 5 ns 20 % to 80 %; CRXD = 25 pF [4] - - 9 ns 80 % to 20 %; CRXD = 15 pF [4] - - 5 ns 80 % to 20 %; CRXD = 25 pF [4] - - 9 ns CRXD = 15 pF [4] 4 - 4 ns CRXD = 25 pF [4] 7 - 7 ns RXD tr fall time tf t(r-f) difference between rise and fall time Bus error flag td(norm-stb) normal mode to standby delay time bus error flag set 3 - 10 s td(stb-norm) standby to normal mode delay time bus error flag set 3 - 10 s tdetCL(TXEN) TXEN clamp detection time 4.5 V < VCC < 5.5 V 1500 - 2600 s tdetCL(BGE) BGE clamp detection time 4.5 V < VCC < 5.5 V 1500 - 2600 s Miscellaneous [1] Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 1 ns. [2] See Figure 14. [3] See Figure 15. [4] Guaranteed by design. [5] See Figure 17. [6] Vdif = VBP  VBM. [7] See Figure 8. [8] See Figure 10. [9] See Figure 12. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 25 of 38 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Rev. 6 — 28 November 2012 All information provided in this document is subject to legal disclaimers. TXD 0.5VIO TXEN 0.5VIO BGE 0.5VIO BP and BM +300 mV 0V −300 mV RXD td(TXEN-busact) td(TXEN-busidle) NXP Semiconductors TJA1082 Product data sheet td(TXD-bus0) td(TXD-bus1) td(BGE-busact) td(BGE-busidle) 80 % −30 mV −300 mV −30 mV −300 mV 20 % 0.5VIO td(bus-RXD) td(bus-RXD) td(bus-RXD) + tdet(idle)(bus) td(bus-RXD) + tr(busact-busidle) tf(busact-busidle) tdet(act)(bus) tr(dif)(bus) tf(dif)(bus) 015aaa010 Fig 13. Detailed timing diagram TJA1082 FlexRay node transceiver 26 of 38 © NXP B.V. 2012. All rights reserved. TJA1082 NXP Semiconductors FlexRay node transceiver > 100 ns TXD 100 % of VIO 50 % of VIO 0 % of VIO t td(TXD-bus) td(TXD-bus) Vdif(VBP-VBM) (mV) 100 % > 600 80 % 300 0 t −300 20 % < −600 0% tf(dif)(bus) tr(dif)(bus) 015aaa011 Vdif is the transmitter test signal. Fig 14. Transmitter timing diagram Vdif(VBP-VBM) (mV) 22 ns 22 ns 400 300 0 −300 −400 30 ns 30 ns 30 ns td(bus-RXD) RXD td(bus-RXD) 100 % VIO 80 % VIO 50 % VIO 20 % VIO 0 % VIO tf(RXD) tr(RXD) 015aaa012 Vdif is the receiver test signal. Fig 15. Normal receiver timing diagram TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 27 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 11. Test information +5 V 100 nF 1 14 VIO VCC BP 13 Rbus TJA1082 BM RXD Cbus 12 4 CRXD 015aaa013 Fig 16. Test circuit for measuring dynamic characteristics +5 V 100 nF 1 VIO 14 VCC BP 1 nF 13 Rbus TJA1082 BM Cbus 12 ISO 7637 PULSE GENERATOR 1 nF RXD 4 15 pF 015aaa014 The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2a, 3a and 3b. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz Fig 17. Test circuit for measuring automotive transients TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 28 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 12. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 18. Package outline SOT402-1 (TSSOP14) TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 29 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 30 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 and 14 Table 13. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 14. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 31 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 19. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 32 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 14. Appendix 14.1 EPL 3.0.1 requirements implemented in the TJA1082 Table 15. EPL 3.0.1 requirements implemented EPL 3.0.1 parameter Description - wake-up via dedicated data frames dBusTxDif difference between rise and fall times:  3 ns RDCLoad transmitter output voltage defined for DC bus load of 40  to 55 /100 pF - transmission not allowed to start with DATA_1 dBDTx10, dBDTx01 transmitter delay:  75 ns dBDTxia, dBDTxai transmitter idle-to-active/active-to-idle transition delay:  75 ns dBDTxDM transmitter idle-to-active delay mismatch: 50 ns uData0_LP receiver thresholds for detecting DATA_0 in low-power modes: 400 mV (min)/ 100 mV (max) dBDRxai idle reaction time: 50 ns to 275 ns dBDActivityDetection activity detection time 100 ns to 250 ns dBDRxia activity reaction time: 100 ns to 325 ns uData1  uData0 receiver threshold mismatch:  30 mV dBDRx10, dBDRx01 receiver delay:  75 ns dBusRx0BD, dBusRx1BD minimum bit time: 70 ns C_StarTxD, C_BDTxD maximum input capacitance on pin TXD: 10 pF dBDRxDR15 + dBDRxDF15 sum of RXD rise and fall times (20 %/80 %):  13 ns with a 15 pF load dBDTxRxai idle loop delay:  325 ns dStarTxActiveMax TXEN timeout: 650 s to 2600 s - BD_Off mode defined (TJA1082 Power-off mode) dBDModeChange Reaction time to mode change request 100 s (max) - Short circuit currents: iBPBMShortMax,iBMBPShortMax BP shorted to BM: < 60 mA; no time limit iBPGNDShortMax,iBMGNDShortMax BP/BM shorted to ground: < 60 mA; no time limit iBP-5ShortMax,iBM-5ShortMax BP/BM shorted to 5 V: < 60 mA; no time limit iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 27 V: < 60 mA; no time limit iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 48 V: < 72 mA; no time limit iBPBAT60ShortMax,iBMBAT60ShortMax BP/BM shorted to 60 V: < 90 mA; for 400 ms (max) - ERRN output signals errors including wake-up status and wake-up source iBPLeakGND, IBMLeakGND leakage current on BP/BM in case of loss of GND 1600 A (max) uBDUVVCC VCC undervoltage detection threshold: > 4 V uUVIO VIO undervoltage detection threshold: > 2 V; detection timeout 1000 ms (max) dBDRVCC, dBDRVIO, dStarRVBAT VCC/VIO/VBAT undervoltage recovery time: 10 ms (max) - Qualification according to AEC-Q100 temperature classes uESDExt 6 kV ESD (min) on pins BP and BM according to HBM (100 pF/1500 ) uESDInt 2 kV ESD (min) on all other pins according to HBM (100 pF/1500 ) uESDIEC 6 kV ESD (min) on pins BP and BM according to IEC 61000-4-2 TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 33 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 15. Abbreviations Table 16. Abbreviations Abbreviation Description CDM Charged Device Model ECU Electronic Control Unit EMC ElectroMagnetic Compatibility EME ElectroMagnetic Emission EMI ElectroMagnetic Immunity ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PWON Power-on 16. References TJA1082 Product data sheet [1] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. B, FlexRay Consortium, Nov 2006 [2] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 3.0.1, FlexRay Consortium [3] AN — Application hint AN10365 - Surface mount reflow soldering description All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 34 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 17. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1082 v.6 20121128 Product data sheet - TJA1082 v.5 Modifications: • • • Section 6.2.1, Section 6.8: text revised Table 9: parameter values revised: VCC, VIO Table 12: parameter conditions revised: tr(bus)(act-idle) TJA1082 v.5 20120620 Product data sheet - TJA1082 v.4 TJA1082 v.4 20120613 Product data sheet - TJA1082 v.3 TJA1082 v.3 20110224 Product data sheet - TJA1082 v.2 TJA1082 v.2 20090810 Product data sheet - TJA1082 v.1 TJA1082 v.1 20090701 Preliminary data sheet - - TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 35 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TJA1082 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 36 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Licenses Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. This NXP product contains functionality that is compliant with the FlexRay specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. NXP ICs with FlexRay functionality These specifications and the material contained in them, as released by the FlexRay Consortium, are for the purpose of information only. The FlexRay Consortium and the companies that have contributed to the specifications shall not be liable for any use of the specifications. The material contained in these specifications is protected by copyright and other types of Intellectual Property Rights. The commercial exploitation of the material contained in the specifications requires a license to such Intellectual Property Rights. These specifications may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. For any other purpose, no part of the specifications may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher. The FlexRay specifications have been developed for automotive applications only. They have neither been developed nor tested for non-automotive applications. The word FlexRay and the FlexRay logo are registered trademarks. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TJA1082 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 28 November 2012 © NXP B.V. 2012. All rights reserved. 37 of 38 TJA1082 NXP Semiconductors FlexRay node transceiver 20. Contents 1 2 2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Low power management . . . . . . . . . . . . . . . . . 1 2.3 Diagnosis and robustness . . . . . . . . . . . . . . . . 2 2.4 FlexRay conformance classes . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.1.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1.1.1 Bus activity and idle detection . . . . . . . . . . . . . 7 6.1.2 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.3 Power-off mode . . . . . . . . . . . . . . . . . . . . . . . . 7 6.1.4 State transitions . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Power-up and power-down behavior . . . . . . . . 9 6.2.1 Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2.2 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 11 6.3.1 Bus wake-up via wake-up pattern. . . . . . . . . . 11 6.3.2 Bus wake-up via dedicated FlexRay data frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.4 Bus error detection . . . . . . . . . . . . . . . . . . . . . 13 6.5 Fail silent behavior . . . . . . . . . . . . . . . . . . . . . 13 6.6 TJA1082 flags. . . . . . . . . . . . . . . . . . . . . . . . . 13 6.7 TJA1082 status register . . . . . . . . . . . . . . . . . 14 6.8 Error signalling . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8.1 SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8.2 Simple error indication mode . . . . . . . . . . . . . 16 6.9 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Thermal characteristics . . . . . . . . . . . . . . . . . 18 9 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 23 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 28 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29 13 Soldering of SMD packages . . . . . . . . . . . . . . 30 13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 30 13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 30 13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 30 13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 14 14.1 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPL 3.0.1 requirements implemented in the TJA1082. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 34 35 36 36 36 36 37 37 37 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 November 2012 Document identifier: TJA1082