TJA1100
100BASE-T1 PHY for Automotive Ethernet
Rev. 3 — 23 May 2017
Product data sheet
1. General description
The TJA1100 is a 100BASE-T1 compliant Ethernet PHY optimized for automotive use
cases. The device provides 100 Mbit/s transmit and receive capability over a single
Unshielded Twisted Pair (UTP) cable, supporting a cable length of up to at least 15 m.
Optimized for automotive use cases such as IP camera links, driver assistance systems
and back-bone networks, the TJA1100 has been designed to minimize power
consumption and system costs, while still providing the robustness required for
automotive use cases.
2. Features and benefits
2.1 Optimized for automotive use cases
Transmitter optimized for capacitive coupling to unshielded twisted-pair cable
Enhanced integrated PAM-3 pulse shaping for low RF emissions
Adaptive receive equalizer optimized for automotive cable length of up to at least 15 m
Reduced power consumption through configurable transmitter pulse amplitude
adapted to cable length
Dedicated PHY enable/disable input pin to minimize power consumption
Low-power Sleep mode with local wake-up support
Robust remote wake-up via the bus lines
Gap-free supply undervoltage detection with fail-silent behavior
EMC-optimized output driver strength for Media Independent Interface (MII) and
Reduced MII (RMII)
Diagnosis of cabling errors (shorts and opens)
Small HVQFN-36 package for PCB space-constrained applications
MDI pins protected against ESD to 6kV HBM and 6kV IEC61000-4-2
MDI pins protected against transients in automotive environment
Automotive-grade temperature range from 40 C to +125 C
Automotive product qualification in accordance with AEC-Q100
2.2 Miscellaneous
MII as well as RMII standard compliant interface
Reverse MII mode for back-to-back connection of two PHYs
3V3 single supply operation with on-chip 1.8 V LDO regulators
On-chip termination resistors for balanced UTP cable
Jumbo frame support up to 16 kB
Internal, external and remote loopback mode for diagnosis
TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
Bus pins short-circuit proof to battery voltage and ground (including common mode
choke, 100 nF coupling capacitors)
LED control output for link diagnosis
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
TJA1100HN
TJA1100
Product data sheet
Description
Version
HVQFN36 plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; SOT1092-2
body 6 6 0.85 mm
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TJA1100
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100BASE-T1 PHY for Automotive Ethernet
4. Block diagram
A block diagram of the TJA1100 is shown in Figure 1. The 100BASE-T1 section contains
the functional blocks specified in the 100BASE-T1 standard that make up the Physical
Coding Sublayer (PCS) and the Physical Medium Attachment (PMA) layer for both the
transmit and receive signal paths. The MII/RMII interface (including the Serial
Management Interface (SMI)) conforms to IEEE802.3 clause 22.
Additional blocks are defined for mode control, register configuration, interrupt control,
system configuration, reset control, LED control, local wake-up and configuration control.
A number of power supply related functional blocks are defined: Very Low Power (VLP)
supply in Sleep mode, Reset circuit, supply monitoring and a 1.8 V regulator for the digital
core. Pin strapping allows a number of default PHY settings (e.g. Master or Slave
configuration) to be hardware-configured at power-up.
The clock signals needed for the operation of the PHY are generated in the PLL block,
derived from an external crystal or an oscillator input signal.
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Fig 4.
Table 3.
MII signaling
MII encoding of TXD[3:0], TXEN and TXER
TXEN
TXER
TXD[3:0]
Indication
0
0
0000 through 1111
normal interframe
0
1
0000 through 1111
reserved
1
0
0000 through 1111
normal data transmission
1
1
0000 through 1111
transmit error propagation
Table 4.
MII encoding of RXD[3:0], RXDV and RXER
RXDV
RXER
RXD[3:0]
Indication
0
0
0000 through 1111
normal interframe
0
1
0000
normal interframe
0
1
0001 through 1101
reserved
0
1
1110
false carrier indication
0
1
1111
reserved
1
0
0000 through 1111
normal data transmission
1
1
0000 through 1111
data reception with errors
Since 100BASE-T1 provides full-duplex communication, the standard signals COL and
CRS are not needed.
6.2.2 RMII
6.2.2.1
Signaling and encoding
In the case of RMII, data is exchanged via 2-bit wide data nibbles on TXD[1:0] and
RXD[1:0], as illustrated in Figure 5. To achieve the same data rate as MII, the interface is
clocked at a nominal frequency of 50 MHz. A single clock signal, REF_CLK, is provided
for both transmit and received data. This clock signal is provided by the PHY and is
typically derived from an external 25 MHz (100 ppm) crystal (see Figure 5). Alternatively,
a 50 MHz clock signal (50 ppm) generated by an external oscillator can be connected to
pin REFCLK_IN (see Figure 6).
RMII encoding is described in Table 5 and Table 6.
TJA1100
Product data sheet
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8 of 55
TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
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Fig 5.
RMII signaling using an external crystal
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Fig 6.
Table 5.
Product data sheet
RMII signaling using an externally generated reference clock
RMII encoding of TXD[1:0], TXEN
TXEN
TXD[1:0]
Indication
0
00 through 11
normal interframe
1
00 through 11
normal data transmission
Table 6.
TJA1100
DDD
RMII encoding of RXD[1:0], CRSDV and RXER
CRSDV
RXER
RXD[1:0]
Indication
0
0
00 through 11
normal interframe
0
1
00
normal interframe
0
1
01 through 11
reserved
1
0
00 through 11
normal data transmission
1
1
00 through 11
data reception with errors
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TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
6.2.3 Reverse MII
In Reverse MII mode, two PHYs are connected back-to-back via the MII interface to
realize a repeater function on the physical layer (see Figure 7). The MII signals are
cross-connected: RX output signals from each PHY are connected to the TX inputs on the
other PHY. For the PHY connected in Reverse MII mode, the TXC and RXC clock signals
become inputs.
Since the MII interface is a standardized solution, two PHYs can be used to implement
two different physical layers to realize, for example, a conversion from Fast Ethernet to
100BASE-T1 and vice versa. Another use case for such a repeater could be to double the
link length up to 30 m.
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Fig 7.
Fast Ethernet to 100BASE-T1 media converter with TJA1100 Reverse MII
6.3 System controller
6.3.1 Operating modes
6.3.1.1
Power-off mode
TJA1100 remains in Power-off mode as long as the voltage on pin VBAT is below the
power-on reset threshold. The analog blocks are disabled and the digital blocks are in a
passive reset state in this mode.
6.3.1.2
Standby mode
At power-on, when the voltage on pin VBAT rises above the under-voltage recovery
threshold (Vuvr(VBAT)), the TJA1100 enters Standby mode, switching on the INH control
output. This control signal may be used to activate the supply to the microcontroller in the
ECU. Once the 3.3 V supply voltage is available, the internal 1.8 V regulators are
activated and the PHY is configured according to the pin-strapping implemented on the
CONFIGn and PHYADn pins. No SMI access takes place during the power-on settling
time (ts(pon)).
From an operating point of view, Standby mode corresponds to the IEEE 802.3
Power-down mode, where the transmit and receive functions (in the PHY) are disabled.
Standby mode also acts as a fail-silent mode. The TJA1100 switches to Standby mode
when an under-voltage condition is detected on VDDA(3V3), VDDA(1V8), VDDD(1V8) or VDD(IO).
TJA1100
Product data sheet
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TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
6.3.1.3
Normal mode
To establish a communication link, the TJA1100 must be switched to Normal mode, either
autonomously (AUTO_OP = 1; see Table 20) or via an SMI command (AUTO_OP = 0).
When the PHY is configured for autonomous operation, the TJA1100 will automatically
enter Normal mode and activate the link on power-on.
When the PHY is host-controlled, the internal PLL starts running when the TJA1100
enters Normal mode and the transmit and receive functions (both PCS and PMA) are
enabled. After a period of stabilization, tinit(PHY), the TJA1100 is ready to set up a link.
Once the LINK_CONTROL bit is set to 'ENABLE', the PHY configured as Master initiates
the training sequence by transmitting idle pulses. The link is established when bit
LINK_UP in the Communication Status register is set.
6.3.1.4
Disable mode
Whenever the Ethernet interface is not in use or must be disabled for fail-safe reasons,
the PHY can be switched off by pulling pin EN LOW. The PHY is switched off completely
in Disable mode, minimizing power consumption. The configuration register settings are
maintained. To exit Disable mode, pin EN must be forced HIGH to activate the PHY.
6.3.1.5
Sleep mode
If the network management in a node decides to withdraw from the network because the
functions of the node are no longer needed, it may power down the entire ECU via PHY
Sleep mode. In Sleep mode, the transmit and receive functions are switched off and no
signal is driven onto the twisted-pair lines. Transmit requests from the MII interface are
ignored and the MII output pins are in a high-ohmic state. The SMI is also deactivated to
minimize power consumption.
By releasing the INH output, the ECU is allowed to switch off its main power supply unit.
Typically, the entire ECU is powered-down. The TJA1100 is kept partly alive by the
permanent battery supply and can still react to activity on the Ethernet lines. Once valid
Ethernet idle pulses are detected on the lines, the TJA1100 wakes up, switching on the
main power unit via the INH control signal. As soon as the supply voltages are stable
within their operating ranges, the TJA1100 can be switched to Normal mode via an SMI
command and the communication link to the partner can be re-established. Sleep mode
can be entered from Normal mode via the intermediate Sleep Request mode as well as
from Standby mode, as shown in Figure 8. Note that the configuration register settings are
maintained in Sleep mode.
6.3.1.6
Sleep Request mode
Sleep Request mode is an intermediate state used to introduce a transition to Sleep
mode. The PHY sleep request timer starts when the TJA1100 enters Sleep Request
mode. This timer determines how long the PHY remains in Sleep Request mode. When
the timer expires (after tto(req)sleep), the PHY switches to Sleep mode and INH is switched
off. The PHY does not expect to receive Ethernet frames in Sleep Request mode. If any
Ethernet frames are received at MDI or MII in Sleep Request mode, the PHY returns to
Normal mode, the DATA_DET_WU flag in the General status register is set and a
WAKEUP interrupt is generated.
Table 7 presents an overview of the status of TJA1100 functional blocks in each operating
mode.
TJA1100
Product data sheet
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TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
Table 7.
Status of functional blocks in TJA1100 operating modes
Functional block
MII
6.3.1.7
Normal
Standby[1]
Sleep Request Sleep
Disable
on
high-ohmic[2]
on
high-ohmic
high-ohmic
PMA/PCS-TX
on
off
on
off
off
PMA/PCS-RX
on
off
on
off
off
SMI
on
on
on
off
off
Activity detection
off
on
off
on
off
Crystal oscillator
on
off
on
off
off
LDO_1V8
on
on
on
off
off
RST_N input
on
on
on
off
on
EN input
on[3]
on
on
off
on
WAKE input
off
on/off[4]
on/off[4]
on/off[4]
off
INT_N output
on
on
on
high-ohmic
high-ohmic
LED output
on/off[4]
off
on/off[4]
off
off
INH output
on
on
on
off
on/off[5]
Temp detection
on
on
on
off
off
[1]
Outputs RXD[3:0], RXER and RXDV are LOW in Standby mode; the other MII pins are configured as inputs
via internal 100 k pull-down resistors.
[2]
Pins configured as outputs will be LOW in Standby mode.
[3]
In Normal mode, this pin is used as the TXCLK output for the test modes and the slave jitter test (the PHY
enable input is held HIGH internally during this time).
[4]
The WAKE input is active in Standby, Sleep Request and Sleep modes if LED_ENABLE = 0; the LED
output is active in Normal and Sleep Request modes if LED_ENABLE = 1.
[5]
The behavior of the INH output in Disable mode is configurable.
Reset mode
The TJA1100 switches to Reset mode from any mode except Power-off when pin RST_N
is held LOW for at least the maximum reset detection time (tdet(rst)(max)), provided the
voltage on VDD(IO) is above the undervoltage threshold.
When RST_N goes HIGH again, or an undervoltage is detected on VDD(IO), the TJA1100,
switches to Standby mode. All register bits are reset to their default values in Reset mode.
TJA1100
Product data sheet
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TJA1100
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100BASE-T1 PHY for Automotive Ethernet
6.3.2 Transitions between operating modes
One of the key features of the TJA1100 is the possibility to put a link and its associated
nodes into Sleep mode, while ensuring that the node can be woken up by activity on the
Ethernet wires. A node can be switched to Sleep mode when link operation is not needed,
minimizing power consumption.
Figure 8 shows the TJA1100 mode transition diagram. For a detailed description of the
Sleep transition process, see the TJA1100 application hints [Ref. 1].
The following events, listed in order of priority, trigger mode transitions:
•
•
•
•
•
•
TJA1100
Product data sheet
Power on/off
Undervoltage on VDD(IO) or VDDD(1V8)
RST_N input
EN input
Overtemperature or Undervoltage on VDDA(3V3), VDDA(1V8) or VDDD(1V8)
SMI command and wake-up (local or remote)
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TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
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260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
TJA1100
Product data sheet
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TJA1100
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100BASE-T1 PHY for Automotive Ethernet
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. References
TJA1100
Product data sheet
[1]
AH1310 TJA1100 Application Hints
[2]
IEEE Std 802.3bw-2015, 26 October 2015
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100BASE-T1 PHY for Automotive Ethernet
16. Revision history
Table 35.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1100 v.3
20170523
Product data sheet
-
TJA1100 v.2.2
Modifications:
•
Compliance with 100BASE-T1 IEEE 802.3bw instead of OPEN Alliance BroadR-Reach
(OABR):
– old specification replaced with new throughout document
– reference to BroadR-Reach removed from Figure 1
– Section 6.9: text of 1st paragraph revised
– Table 17: text of bit 6 revised
– Table 20: text of bit 13 revised
– TX Enable removed:
Table 23: bit 4 TXEN_CLAMPED removed; bit now reserved
Table 24: bit 4 TXEN_CLAMPED_EN removed; bit now reserved
Table 32: parameter tdetCL(TXEN) removed
– Table 32: value of parameter tPD changed
•
text ‘SNR’/‘signal-to-noise ratio’ replaced by ‘SQI’/ ‘Signal Quality Indicator’ throughout the
document
•
•
Figure 1 revised: pin names corrected/added
•
•
Table 2, Figure 2: TXCLK functionality added to pin 35; associated Table note 3 added in
Table 7; description text amended for pins 4 and 16
Figure 3: low-pass filter (LP) and ESD stages added at input and output
LPS/WUR functions removed as not in line with new TC10 Sleep/Wake-up specification
– Section 6.3.2: text of first two paragraphs amended; Figure 9 deleted
– Section 6.4: final paragraph deleted
– Table 20: bits 0 and 6 now reserved; Table note 4 added
– Table 23, Table 24: bits 13 and 12 now reserved (interrupts removed)
•
•
Section 6.10.2: 2nd paragraph deleted, replaced by Table 9
•
Section 6.10.8 restructured/revised
Section 6.10.6: polarity detection re-introduced; POLARITY_DETECT added (bit 6) in
Table 27
– Section 6.10.8.2: reference to open link in Figure 10 replaced with ‘terminated MDI’, and
text in preceding paragraph changed accordingly
•
PHY identification register 3 for manufacturer's firmware revision number added:
– register 16 added to Table 11
– Table 18 added
•
•
•
•
•
TJA1100
Product data sheet
Table 16: value of bits REVISION_NO changed
Table 21: Table note 2 added
Table 23: description of bit 0 clarified
Table 25: changed description for bits 7:5
Table 31: parameter values/conditions changed - IBAT, VDDD(3V3), P; VOH and VOL
parameters added for pin TXCLK
•
Table 32: parameter values/conditions changed - (R)MII rise and fall times (tr and tf); INT_N
timing parameters added, tw(LED) added, tf and tr parameters added for pin TXCLK
•
•
Figure 17 amended (Ethernet terminal connections added; text ‘optional’ removed)
Figure 18 and associated text amended
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TJA1100
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100BASE-T1 PHY for Automotive Ethernet
Table 35.
Revision history …continued
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1100 v.2.2
20160721
Product data sheet
-
TJA1100 v.1
TJA1100 v.1
20160104
Product data sheet
-
-
TJA1100
Product data sheet
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100BASE-T1 PHY for Automotive Ethernet
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 23 May 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
53 of 55
TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
TJA1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 23 May 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
54 of 55
TJA1100
NXP Semiconductors
100BASE-T1 PHY for Automotive Ethernet
19. Contents
1
2
2.1
2.2
3
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.1.1
6.2.2
6.2.2.1
6.2.3
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.1.5
6.3.1.6
6.3.1.7
6.3.2
6.4
6.5
6.5.1
6.5.2
6.5.3
6.6
6.7
6.8
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.10
6.10.1
6.10.2
6.10.3
6.10.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Optimized for automotive use cases. . . . . . . . . 1
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 7
System configuration . . . . . . . . . . . . . . . . . . . . 7
MII and RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signaling and encoding . . . . . . . . . . . . . . . . . . 7
RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signaling and encoding . . . . . . . . . . . . . . . . . . 8
Reverse MII . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System controller . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes . . . . . . . . . . . . . . . . . . . . . . 10
Power-off mode . . . . . . . . . . . . . . . . . . . . . . . 10
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disable mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sleep Request mode . . . . . . . . . . . . . . . . . . . 11
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transitions between operating modes . . . . . . 13
Wake-up request . . . . . . . . . . . . . . . . . . . . . . 14
Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 15
Local wake-up . . . . . . . . . . . . . . . . . . . . . . . . 15
Wake-up by data detection . . . . . . . . . . . . . . . 15
Autonomous operation . . . . . . . . . . . . . . . . . . 15
Autonomous power-down . . . . . . . . . . . . . . . . 15
Transmitter amplitude . . . . . . . . . . . . . . . . . . . 15
Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test mode 5 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Slave jitter test . . . . . . . . . . . . . . . . . . . . . . . . 16
Error diagnosis . . . . . . . . . . . . . . . . . . . . . . . . 17
Undervoltage detection. . . . . . . . . . . . . . . . . . 17
Cabling errors . . . . . . . . . . . . . . . . . . . . . . . . . 17
Link stability . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Link-fail counter . . . . . . . . . . . . . . . . . . . . . . . 18
6.10.5
6.10.6
6.10.7
6.10.8
6.10.8.1
6.10.8.2
6.10.8.3
6.11
6.12
6.12.1
7
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
17
17.1
17.2
17.3
17.4
18
19
Jabber detection . . . . . . . . . . . . . . . . . . . . . . 18
Polarity detection . . . . . . . . . . . . . . . . . . . . . . 18
Interleave detection . . . . . . . . . . . . . . . . . . . . 18
Loopback modes . . . . . . . . . . . . . . . . . . . . . . 18
Internal loopback . . . . . . . . . . . . . . . . . . . . . . 18
External loopback . . . . . . . . . . . . . . . . . . . . . 19
Remote loopback . . . . . . . . . . . . . . . . . . . . . . 19
Auto-configuration of the PHY during power-up
via pin strapping. . . . . . . . . . . . . . . . . . . . . . . 20
SMI registers . . . . . . . . . . . . . . . . . . . . . . . . . 20
SMI register mapping. . . . . . . . . . . . . . . . . . . 20
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34
Thermal characteristics . . . . . . . . . . . . . . . . . 35
Static characteristics . . . . . . . . . . . . . . . . . . . 35
Dynamic characteristics. . . . . . . . . . . . . . . . . 39
Application information . . . . . . . . . . . . . . . . . 45
Package information. . . . . . . . . . . . . . . . . . . . 46
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47
Soldering of SMD packages . . . . . . . . . . . . . . 48
Introduction to soldering. . . . . . . . . . . . . . . . . 48
Wave and reflow soldering. . . . . . . . . . . . . . . 48
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 48
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 49
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision history . . . . . . . . . . . . . . . . . . . . . . . 51
Legal information . . . . . . . . . . . . . . . . . . . . . . 53
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 53
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Contact information . . . . . . . . . . . . . . . . . . . . 54
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 May 2017
Document identifier: TJA1100
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