TJA1145
High-speed CAN transceiver for partial networking
Rev. 4 — 09 May 2018
Product data sheet
1. General description
The TJA1145 is a high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is designed for high-speed CAN applications in the automotive industry,
providing differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller.
The TJA1145 features very low power consumption in Standby and Sleep modes and
supports ISO 11898-2:2016 compliant CAN Partial Networking by means of a selective
wake-up function.
A dedicated implementation of the partial networking function has been embedded into
the TJA1145/FD variants TJA1145T/FD and TJA1145TK/FD (see Section 7.3.2 for further
details on CAN FD). This function is called ‘FD-passive’ and is the ability to ignore CAN
FD frames while waiting for a valid wake-up frame in Sleep/Standby mode. This additional
feature of partial networking is the perfect fit for networks that support both CAN FD and
standard CAN 2.0 communications. It allows normal CAN controllers that do not need to
communicate CAN FD messages to remain in partial networking Sleep/Standby mode
during CAN FD communication without generating bus errors.
Advanced power management regulates the supply throughout the node and supports
local and remote wake-up functionality. I/O levels are automatically adjusted to the I/O
levels of the controller, allowing the TJA1145 to interface directly with 3.3 V to 5 V
microcontrollers. An SPI interface is provided for transceiver control and for retrieving
status information. Bus connections are truly floating when power is off.
The TJA1145 implements the CAN physical layer as defined in ISO 11898-2:2016 and
SAE J2284-1 to SAE J2284-4. This implementation enables reliable communication in the
CAN FD fast phase at data rates up to 2 Mbit/s.
These features make the TJA1145 the ideal choice for high-speed CAN networks
containing nodes that are always connected to the battery supply line but, in order to
minimize current consumption, are only active when required by the application.
2. Features and benefits
2.1 General
ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-4 compliant
Timing guaranteed for data rates up to 2 Mbit/s
Autonomous bus biasing according to ISO 11898-2:2016
Optimized for in-vehicle high-speed CAN communication
No ‘false’ wake-ups due to CAN FD in TJA1145/FD variants
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on pins BAT and WAKE and on the
CAN bus pins
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against transients according to ISO 7637-3, test
pulses 1, 2a, 3a and 3b.
Suitable for use in 12 V and 24 V systems
Available in SO14 and leadless HVSON14 package (3 mm 4.5 mm) with improved
Automated Optical Inspection (AOI) capability
AEC-Q100 qualified
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.3 Advanced ECU power management system
Very low-current Standby and Sleep modes, with full wake-up capability
Entire node can be powered down via the inhibit output
Remote wake-up capability via standard CAN wake-up pattern or via
ISO 11898-2:2016 compliant selective wake-up frame detection
Local wake-up via the WAKE pin
Wake-up source recognition
Bit rates of 50 kbit/s, 100 kbit/s, 125 kbit/s, 250 kbit/s, 500 kbit/s and 1 Mbit/s
supported during selective wake-up'
Local and/or remote wake-up can be disabled to reduce current consumption
Transceiver disengages from the bus when the battery supply is removed
VIO input allows for direct interfacing with 3.3 V to 5 V microcontrollers
2.4 Protection and diagnosis
TJA1145
Product data sheet
16-, 24- or 32-bit SPI for configuration, control and diagnosis
Transmit Data (TXD) dominant time-out function with diagnosis
Overtemperature warning and shut-down
Undervoltage detection and recovery on pins VCC, VIO and BAT
Cold start diagnosis (via bits PO and NMS)
Advanced system and transceiver interrupt handling
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Rev. 4 — 09 May 2018
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
3. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
VBAT
Min
Typ Max
Unit
battery supply voltage
4.5
-
28
V
VCC
supply voltage
4.5
-
5.5
V
VIO
supply voltage on pin VIO
Vth(det)poff power-off detection threshold
voltage
Conditions
VBAT falling
Vuvd(VCC) undervoltage detection voltage
on pin VCC
2.85
-
5.5
V
2.8
-
3
V
4.5
-
4.75
V
Vuvd(VIO)
undervoltage detection voltage
on pin VIO
VBAT > 4.5 V
2.7
-
2.85
V
IBAT
battery supply current
Normal mode
-
1
1.5
mA
Sleep mode; CAN Offline mode;
40 C < Tvj < 85 C; VBAT = 7 V to 18 V
-
40
59
A
Standby mode; CAN Offline mode;
40 C < Tvj < 85 C; VBAT = 7 V to 18 V
-
44
68
A
ICC
IIO
supply current
supply current on pin VIO
CAN Active mode; CAN recessive; VTXD = VIO
-
3
6
mA
CAN Active mode; CAN dominant; VTXD = 0 V
-
45
65
mA
Standby/Normal mode; CAN inactive;
40 C < Tvj < 85 C
-
4.7
8.5
A
Sleep mode; CAN inactive; 40 C < Tvj < 85 C
-
3.8
7
A
Standby/Normal mode; 40 C < Tvj < 85 C
-
7.1
11
A
Sleep mode; 40 C < Tvj < 85 C
-
5
8
A
IEC 61000-4-2 on pins CANH, CANL
6
-
+6
kV
VESD
electrostatic discharge voltage
VCANH
voltage on pin CANH
58
-
+58
V
VCANL
voltage on pin CANL
58
-
+58
V
Tvj
virtual junction temperature
40
-
+150 C
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
4. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TJA1145T
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
TJA1145T/FD
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
TJA1145TK
HVSON14
plastic thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 4.5 0.85 mm
SOT1086-2
TJA1145TK/FD
HVSON14
plastic thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 4.5 0.85 mm
SOT1086-2
5. Block diagram
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Fig 1.
TJA1145
Product data sheet
Block diagram
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Rev. 4 — 09 May 2018
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TJA1145
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High-speed CAN transceiver for partial networking
6. Pinning information
6.1 Pinning
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Pin configuration diagram: SO14
Fig 3.
Pin configuration diagram: HVSON14
Transparent top view
6.2 Pin description
Table 3.
Symbol
Pin
Description
TXD
1
transmit data input
GND
2[1]
ground
VCC
3
5 V CAN transceiver supply voltage
RXD
4
receive data output; reads out data from the bus lines
VIO
5
supply voltage for I/O level adaptor
SDO
6
SPI data output
INH
7
inhibit output for switching external voltage regulators
SCK
8
SPI clock input
WAKE
9
local wake-up input
BAT
10
battery supply voltage
SDI
11
SPI data input
CANL
12
LOW-level CAN bus line
CANH
13
HIGH-level CAN bus line
SCSN
14
SPI chip select input
[1]
TJA1145
Product data sheet
Pin description
HVSON14 package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is
recommended that the exposed center pad also be soldered to board ground
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Rev. 4 — 09 May 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
5 of 57
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
7. Functional description
The TJA1145 is a stand-alone high-speed CAN transceiver containing a variety of fail-safe
and diagnostic features that offer enhanced system reliability and advanced power
management. The transceiver combines the functionality of the TJA1043 with
ISO 11898-2:2016 compliant CAN partial networking and autonomous bus biasing.
7.1 System controller
The system controller manages register configuration and controls the internal functions
of the TJA1145. Detailed device status information is collected and made available to the
microcontroller.
7.1.1 Operating modes
The system controller contains a state machine that supports five operating modes:
Normal, Standby, Sleep, Overtemp and Off. The state transitions are illustrated in
Figure 4.
7.1.1.1
Normal mode
Normal mode is the active operating mode. In this mode, the TJA1145 is fully operational.
All device hardware is available and can be activated (see Table 4).
Normal mode can be selected from Standby or Sleep mode via an SPI command
(MC = 111).
7.1.1.2
Standby mode
Standby mode is the first-level power-saving mode of the TJA1145, featuring low current
consumption. The transceiver is unable to transmit or receive data in Standby mode, but
the INH pin remains active so voltage regulators controlled by this pin will be active.
If remote CAN wake-up is enabled (CWE = 1; see Table 22), the receiver monitors bus
activity for a wake-up request. The bus pins are biased to GND (via Ri(cm)) when the bus is
inactive and at approximately 2.5 V when there is activity on the bus (autonomous
biasing). CAN wake-up can occur via a standard wake-up pattern or via a selective
wake-up frame (selective wake-up is enabled when CPNC = PNCOK = 1; otherwise
standard wake-up is enabled).
Pin RXD is forced LOW when any enabled wake-up or interrupt event is detected (see
Section 7.6).
The TJA1145 switches to Standby mode:
• from Off mode if the battery voltage rises above the power-on detection threshold,
Vth(det)pon.
• from Overtemp mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp.
• from Sleep mode on the occurrence of a wake-up or interrupt event (see Section 7.6)
• from Normal or Sleep mode via an SPI command (MC = 100)
• from Normal mode if Sleep mode is selected via an SPI command (MC = 001) while a
wake-up event is pending or all wake-up sources are disabled
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
6 of 57
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
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Fig 4.
TJA1145 system controller state diagram
7.1.1.3
Sleep mode
Sleep mode is the second-level power saving mode of the TJA1145. In Sleep mode, the
transceiver behaves as in Standby Mode with the exception that pin INH is set to a
high-ohmic state. Voltage regulators controlled by this pin will be switched off, and the
current into pin BAT will be reduced to a minimum.
Any enabled wake-up or interrupt event (except SPIF), or an SPI command (provided a
valid VIO voltage is connected), will wake up the transceiver from Sleep mode.
Sleep mode can be selected from Normal or Standby mode via an SPI command
(MC = 001). The TJA1145 will switch to Sleep mode on receipt of this command, provided
there are no pending wake-up events and at least one regular wake-up source (CAN bus
or WAKE pin; see Section 7.6) is enabled. Any attempt to enter Sleep mode while one of
these conditions has not been met will cause the TJA1145 to switch to Standby mode.
TJA1145
Product data sheet
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
The TJA1145 will also be forced to switch to Sleep mode if a VCC of VIO undervoltage
event is detected (VCC/VIO < VUVD(VCC)/VUVD(VIO) for longer than tdet(uv)(VCC)/tdet(uv)(VIO)). In
this event, all pending wake-up events will be cleared. CAN wake-up (CWE = 1) and local
wake-up via the WAKE pin (WPFE = WPRE = 1) are enabled in order to avoid a system
deadlock (see Section 7.11) and selective wake-up is disabled (CPNC = 0).
Status bit FSMS in the Main status register (Table 6) indicates whether a transition to
Sleep mode was selected via an SPI command (FSMS = 0) or was forced by an
undervoltage event on VCC or VIO (FSMS = 1). This bit can be read after the TJA1145
wakes up from Sleep mode to allow the settings of CWE, WPFE, WPRE and CPNC to be
re-adjusted if an undervoltage event forced the transition to Sleep mode (FSMS = 1).
7.1.1.4
Off mode
The TJA1145 will be in Off mode when the battery voltage is too low to supply the IC. This
is the default mode when the battery is first connected. The TJA1145 will switch to Off
mode from any mode if the battery voltage drops below the power-off threshold
(Vth(det)poff). In Off mode, the CAN pins and pin INH are in a high-ohmic state.
When the battery supply voltage rises above the power-on threshold (Vth(det)pon), the
TJA1145 starts to boot up, triggering an initialization procedure. The TJA1145 will switch
to Standby mode after tstartup.
7.1.1.5
Overtemp mode
Overtemp mode is provided to prevent TJA1145 being damaged by excessive
temperatures. The TJA1145 switches immediately to Overtemp mode from Normal mode
when the global chip temperature rises above the overtemperature protection activation
threshold, Tth(act)otp.
To help prevent the loss of data due to overheating, the TJA1145 issues a warning when
the IC temperature rises above the overtemperature warning threshold (Tth(warn)otp). When
this happens, status bit OTWS is set and an overtemperature interrupt is generated
(OTW = 1), if enabled (OTWE = 1).
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD.
The TJA1145 exits Overtemp mode:
• and switches to Standby mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
• if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
7.1.1.6
Table 4.
Hardware characterization for the TJA1145 operating modes
Hardware characterization by functional block
Block
Operating mode
Off
Standby
Normal
Sleep
Overtemp
SPI
disabled
active
active
active if VIO supplied[1]
disabled
INH
high-ohmic
VBAT level
VBAT level
high-ohmic
VBAT level
CAN
off
Offline
Active/ Offline/ Listen-only
(determined by bits CMC;
see Table 7)
Offline
off
RXD
VIO level
VIO level/LOW if
wake-up event detected
CAN bit stream if
VIO level/LOW if
VIO level/LOW if
CMC = 01/10/11; otherwise wake-up event detected wake-up pending
same as Standby/Sleep
[1]
SPI speed is limited in Sleep mode (see Table 35).
7.1.2 System control registers
The operating mode is selected via bits MC in the Mode control register. The Mode control
register is accessed via SPI address 0x01 (see Section 7.12).
Table 5.
Bit
Mode control register (address 01h)
Symbol
Access Value
7:3
reserved
R
2:0
MC
R/W
Description
mode control:
001
Sleep mode
100
Standby mode
111
Normal mode
The Main status register can be accessed to monitor the status of the overtemperature
warning flag and to determine whether the TJA1145 has entered Normal mode after initial
power-up. Bit FSMS indicates whether the most recent transition to Sleep mode was
triggered by an undervoltage event or by an SPI command.
Table 6.
Bit
Symbol
Access Value
Description
7
FSMS
R
Sleep mode transition status:
6
5
4:0
TJA1145
Product data sheet
Main status register (address 03h)
OTWS
NMS
reserved
0
transition to Sleep mode triggered by an SPI command
1
an undervoltage on VCC and/or VIO forced a transition to
Sleep mode
R
overtemperature warning status:
0
IC temperature below overtemperature warning threshold
1
IC temperature above overtemperature warning threshold
R
R
Normal mode status:
0
TJA1145 has entered Normal mode (after power-up)
1
TJA1145 has powered up but has not yet switched to
Normal mode
-
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TJA1145
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High-speed CAN transceiver for partial networking
7.2 High-speed CAN transceiver
The integrated high-speed CAN transceiver is designed for active communication at bit
rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol
controller. The transceiver is ISO 11898-2:2016 compliant (defining high-speed CAN with
selective wake-up functionality and autonomous bus biasing). The CAN transmitter is
supplied via pin VCC while the CAN receiver is supplied via pin BAT. The TJA1145
includes additional timing parameters on loop delay symmetry to ensure reliable
communication in fast phase at data rates up to 2 Mbit/s, as used in CAN FD networks.
The CAN transceiver supports autonomous CAN biasing, which helps to minimize RF
emissions. CANH and CANL are always biased to 2.5 V when the transceiver is in Active
or Listen-only modes (CMC = 01/10/11).
Autonomous biasing is active in CAN Offline mode - to 2.5 V if there is activity on the bus
(CAN Offline Bias mode) and to GND if there is no activity on the bus for t > tto(silence)
(CAN Offline mode).
This is useful when the node is disabled due to a malfunction in the microcontroller or
when CAN partial networking is enabled. The TJA1145 ensures that the CAN bus is
correctly biased to avoid disturbing ongoing communication between other nodes. The
autonomous CAN bias voltage is derived directly from VBAT.
7.2.1 CAN operating modes
The integrated CAN transceiver supports four operating modes: Active, Listen-only,
Offline and Offline Bias (see Figure 5). The CAN transceiver operating mode depends on
the TJA1145 operating mode and on the setting of bits CMC in the CAN control register
(Table 7).
When the TJA1145 is in Normal mode, the CAN transceiver operating mode (Offline,
Active or Listen-only) can be selected via bits CMC in the CAN control register (Table 7).
When the TJA1145 is in Standby or Sleep modes, the transceiver is forced to Offline or
Offline Bias mode (depending on bus activity).
7.2.1.1
CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
CAN Active mode is selected when CMC = 01 or 10. When CMC = 01, VCC undervoltage
detection is enabled and the transceiver switches to CAN Offline or CAN Offline Bias
mode when the voltage on VCC drops below the 90 % threshold. When CMC = 10, VCC
undervoltage detection is disabled. The transmitter will remain active until the TJA1145 is
forced into Sleep mode by the VCC undervoltage event; the transceiver will then switch to
CAN Offline or CAN Offline Bias mode.
The CAN transceiver is in Active mode when:
• the TJA1145 is in Normal mode (MC = 111) and the CAN transceiver has been
enabled by setting bits CMC in the CAN control register to 01 or 10 (see Table 7) and:
TJA1145
Product data sheet
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High-speed CAN transceiver for partial networking
– if CMC = 01, the voltage on pin VCC is above the VCC undervoltage detection
threshold (Vuvd(VCC))
If pin TXD is held LOW (e.g. by a short-circuit to GND) when CAN Active mode is selected
via bits CMC, the transceiver will not enter CAN Active mode but will switch to or remain in
CAN Listen-only mode. It will remain in Listen-only mode until pin TXD goes HIGH in
order to prevent a hardware and/or software application failure from driving the bus lines
to an unwanted dominant state.
In CAN Active mode, the CAN bias voltage is derived from VCC.
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(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode or CAN
Listen-only mode if pin TXD is held LOW (e.g. by a short-circuit to GND)
Fig 5.
CAN transceiver state machine
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
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TJA1145
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High-speed CAN transceiver for partial networking
The application can determine whether the CAN transceiver is ready to transmit/receive
data or is disabled by reading the CAN Transceiver Status (CTS) bit in the Transceiver
Status Register (Table 8).
7.2.1.2
CAN Listen-only mode
CAN Listen-only mode allows the TJA1145 to monitor bus activity while the transceiver is
inactive, without influencing bus levels. This facility could be used by development tools
that need to listen to the bus but do not need to transmit or receive data or for
software-driven selective wake-up. Dedicated microcontrollers could be used for selective
wake-up, providing an embedded low-power CAN engine designed to monitor the bus for
potential wake-up events.
In Listen-only mode the CAN transmitter is disabled, reducing current consumption. The
CAN receiver and CAN biasing remain active. This enables the host microcontroller to
switch to a low-power mode in which an embedded CAN protocol controller remains
active, waiting for a signal to wake up the microcontroller.
The CAN transceiver is in Listen-only mode when:
• the TJA1145 is in Normal mode and CMC = 11
The CAN transceiver will not leave Listen-only mode while TXD is LOW or CAN Active
mode is selected with CMC = 01 while the voltage on V1 is below the 90 % undervoltage
threshold.
7.2.1.3
CAN Offline and Offline Bias modes
In CAN Offline mode, the transceiver monitors the CAN bus for a wake-up event, provided
CAN wake-up detection is enabled (CWE = 1). CANH and CANL are biased to GND.
CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the CAN
bus is biased to 2.5 V. This mode is activated automatically when activity is detected on
the CAN bus while the transceiver is in CAN Offline mode. The transceiver will return to
CAN Offline mode if the CAN bus is silent (no CAN bus edges) for longer than tto(silence).
The CAN transceiver switches to CAN Offline mode from CAN Active mode or CAN
Listen-only mode if:
• the TJA1145 switches to Standby or Sleep mode OR
• the TJA1145 is in Normal mode and CMC = 00
provided the CAN-bus has been inactive for at least tto(silence). If the CAN-bus has been
inactive for less than tto(silence), the CAN transceiver switches first to CAN Offline Bias
mode and then to CAN Offline mode once the bus has been silent for tto(silence).
The CAN transceiver switches to CAN Offline/Offline Bias mode from CAN Active mode if
CMC = 01 and the voltage on VCC drops below the 90 % undervoltage threshold or if
CMC = 10 and the TJA1145 switches to Sleep mode in response to a VCC undervoltage
event.
The CAN transceiver switches to CAN Offline mode:
• from CAN Offline Bias mode if no activity is detected on the bus (no CAN edges) for
t > tto(silence) OR
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High-speed CAN transceiver for partial networking
• when the TJA1145 switches from Off or Overtemp mode to Standby mode
The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:
• a standard wake-up pattern (according to ISO 11898-2:2016) is detected on the CAN
bus OR
• the CAN transceiver is in Normal mode, CMC = 01 and VCC < 90 %
7.2.1.4
CAN Off mode
The CAN transceiver is switched off completely with the bus lines floating when:
• the TJA1145 switches to Off or Overtemp mode OR
• VBAT falls below the CAN receiver undervoltage detection threshold, Vuvd(CAN)
It will be switched on again on entering CAN Offline mode when VBAT rises above the
undervoltage recovery threshold (Vuvr(CAN)) and the CAN transceiver is no longer in
Off/Overtemp mode. CAN Off mode prevents reverse currents flowing from the bus when
the battery supply to the CAN transceiver is lost.
7.2.2 CAN standard wake-up (partial networking not enabled)
If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), but
CAN selective wake-up is disabled (CPNC = 0 or PNCOK = 0), the TJA1145 will monitor
the bus for a standard wake-up pattern.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. This filtering helps avoid spurious wake-up events. A
spurious wake-up sequence could be triggered by, for example, a dominant clamped bus
or by dominant phases due to noise or spikes on the bus.
The TJA1145 wakes up from Standby or Sleep mode when a dedicated wake-up pattern
(specified in ISO 11898-2:2016) is detected on the bus.
The wake-up pattern consists of:
• a dominant phase of at least twake(busdom) followed by
• a recessive phase of at least twake(busrec) followed by
• a dominant phase of at least twake(busdom)
Dominant or recessive bits between the above mentioned phases that are shorter than
twake(busdom) and twake(busrec) respectively are ignored.
The complete dominant-recessive-dominant pattern must be received within tto(wake)bus to
be recognized as a valid wake-up pattern (see Figure 6). Otherwise, the internal wake-up
logic is reset. The complete wake-up pattern will then need to be retransmitted to trigger a
wake-up event. Pin RXD remains HIGH until the wake-up event has been triggered.
When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the
Transceiver event status register is set (see Table 19) and pin RXD is driven LOW. If the
TJA1145 was in Sleep mode when the wake-up pattern was detected, it will switch pin
INH to VBAT to activate external voltage regulators (e.g. for supplying VCC and VIO) and
enter Standby mode.
TJA1145
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TJA1145
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High-speed CAN transceiver for partial networking
&$1+
92 GLI
&$1/
WZDNH EXVGRP
WZDNH EXVUHF
WZDNH EXVGRP
5;'
WWR ZDNH EXV
DDD
Fig 6.
CAN wake-up timing
7.2.3 CAN control and Transceiver status registers
Table 7.
CAN control register (address 20h)
Bit
Symbol
Access
Value
7
6
reserved
R
-
CFDC
R/W
Description
CAN FD tolerance (TJA1145T/FD and
TJA1145TK/FD only; otherwise ignored)
0
CAN FD tolerance disabled
1
5
PNCOK
R/W
CAN FD tolerance enabled
CAN partial networking configuration:
0
partial networking register configuration invalid
(wake-up via standard wake-up pattern only)
1
4
Product data sheet
R/W
3:2
reserved
R
1:0
CMC
R/W
Table 8.
TJA1145
CPNC
partial networking registers configured successfully
CAN selective wake-up; when enabled, node is part
of a partial network:
0
disable CAN selective wake-up
1
enable CAN selective wake-up
CAN transceiver operating mode selection:
00
Offline mode
01
Active mode (when the TJA1145 is in Normal
mode); VCC 90 % undervoltage detection active
10
Active mode (when the TJA1145 is in Normal
mode); VCC undervoltage detection inactive;
TJA1145 switches from Normal to Off mode when
VBAT < Vuvd(CAN)
11
Listen-only mode
Transceiver status register (address 22h)
Bit
Symbol
Access
7
CTS
R
Value
Description
CAN transceiver status:
0
CAN transceiver not in Active mode
1
CAN transceiver in Active mode
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High-speed CAN transceiver for partial networking
Table 8.
Bit
Symbol
Access
6
CPNERR
R
5
4
3
COSCS
CBSS
0
no CAN partial networking error detected
(PNFDE = 0 AND PNCOK = 1)
1
CAN partial networking error detected (PNFDE = 1
OR PNCOK = 0); wake-up via standard wake-up
pattern only
CAN partial networking status:
0
CAN partial networking configuration error
detected (PNCOK = 0)
1
CAN partial networking configuration OK
(PNCOK = 1)
CAN oscillator status:
0
CAN partial networking oscillator not running at
target frequency
1
CAN partial networking oscillator running at target
frequency
R
R
VCS[1]
R
Description
CAN partial networking error status:
R
reserved
CFS
Value
R
1
[1]
Product data sheet
CPNS
2
0
TJA1145
Transceiver status register (address 22h) …continued
CAN bus silence status:
0
CAN bus active (communication detected on bus)
1
CAN bus inactive (for longer than tto(silence)
VCC supply voltage status:
0
VCC is above the undervoltage detection threshold
(Vuvd(VCC))
1
VCC is below the undervoltage detection threshold
(Vuvd(VCC))
R
CAN failure status:
0
no TXD dominant time-out event detected
1
CAN transmitter disabled due to a TXD dominant
time-out event
Only active when CMC = 01.
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High-speed CAN transceiver for partial networking
7.3 CAN partial networking
Partial networking allows nodes in a CAN network to be selectively activated in response
to dedicated wake-up frames (WUF). Only nodes that are functionally required are active
on the bus while the other nodes remain in a low-power mode until needed.
If both CAN wake-up (CWE = 1) and CAN selective wake-up (CPNC = 1) are enabled,
and the partial networking registers are configured correctly (PNCOK = 1), the transceiver
monitors the bus for dedicated CAN wake-up frames.
7.3.1 Wake-up frame (WUF)
A wake-up frame is a CAN frame according to ISO 11898-1:2015, consisting of an
identifier field (ID), a Data Length Code (DLC), a data field and a Cyclic Redundancy
Check (CRC) code including the CRC delimiter.
The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via
bit IDE in the Frame control register (Table 12).
A valid WUF identifier is defined and stored in the ID registers (Table 10). An ID mask can
be defined to allow a group of identifiers to be recognized as valid by an individual node.
The identifier mask is defined in the mask registers (Table 11), where a 1 means ‘don’t
care’.
In the example illustrated in Figure 7, based on the standard frame format, the 11-bit
identifier is defined as 0x1A0. The identifier is stored in ID registers 2 (0x29) and
3 (0x2A). The three least significant bits of the ID mask, bits 2 to 4 of Mask register 2
(0x2D) are set to 1, which means that the corresponding identifier bits are ‘don’t care’.
This means that any of eight different identifiers will be recognized as valid in the received
WUF (from 0x1A0 to 0x1A7).
7-$63,6HWWLQJV
ELW,GHQWLILHUILHOG
[$VWRUHGLQ,'
UHJLVWHUVDQG
,'PDVN
[VWRUHGLQ0DVN
UHJLVWHUVDQG
[
[
[
9DOLG:DNH8S,GHQWLILHUV [$WR[$
DDD
Fig 7.
Evaluating the ID field in a selective wake-up frame
The data field indicates which nodes are to be woken up. Within the data field, groups of
nodes can be pre-defined and associated with bits in a data mask. By comparing the
incoming data field with the data mask, multiple groups of nodes can be woken up
simultaneously with a single wake-up message.
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High-speed CAN transceiver for partial networking
The data length code (bits DLC in the Frame control register; Table 12) determines the
number of data bytes (between 0 and 8) expected in the data field of a CAN wake-up
frame. If one or more data bytes are expected (DLC 0000), at least one bit in the data
field of the received wake-up frame must be set to 1 and at least one equivalent bit in the
associated data mask register in the transceiver (see Table 13) must also be set to 1 for a
successful wake-up. Each matching pair of 1s indicates a group of nodes to be activated
(since the data field is up to 8 byes long, up to 64 groups of nodes can be defined).
If DLC = 0000, a node will wake up if the WUF contains a valid identifier and the received
data length code is 0000, regardless of the values stored in the data mask. If DLC 0000
and all data mask bits are set to 0, the device cannot be woken up via the CAN bus (note
that all data mask bits are set to 1 by default; see Table 31). If a WUF contains a valid ID
but the DLCs (in the Frame control register and in the WUF) don’t match, the data field is
ignored and no nodes are woken up.
In the example illustrated in Figure 8, the data field consists of a single byte (DLC = 1).
This means that the data field in the incoming wake-up frame is evaluated against data
mask 7 (stored at address 6Fh; see Table 13 and Figure 9). Data mask 7 is defined as
10101000 in the example. This means that up to three groups of nodes could be woken
up (group 1, 3 and 5) if the respective bits in the data frame are also set to 1.
The received message shown in Figure 8 could, potentially, wake up four groups of
nodes: groups 2, 3, 4 and 5. Two matches are found (groups 3 and 5) when the message
data bits are compared with the configured data mask (DM7).
'/&
VWRUHG
YDOXHV
UHFHLYHG
PHVVDJH
'DWDPDVN
*URXSV
DDD
Fig 8.
Evaluating the Data field in a selective wake-up frame
Optionally, the data length code and the data field can be excluded from the evaluation of
the wake-up frame. If bit PNDM = 0, only the identifier field is evaluated to determine if the
frame contains a valid wake-up message. If PNDM = 1 (the default value), the data field is
included in the wake-up filtering.
When PNDM = 0, a valid wake-up message is detected and a wake-up event is captured
(and CW is set to 1) when:
• the identifier field in the received wake-up frame matches the pattern in the ID
registers after filtering AND
• the CRC field in the received frame (including a recessive CRC delimiter) was
received without error
When PNDM = 1, a valid wake-up message is detected when:
• the identifier field in the received wake-up frame matches the pattern in the ID
registers after filtering AND
• the frame is not a Remote frame AND
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High-speed CAN transceiver for partial networking
• the data length code in the received message matches the configured data length
code (bits DLC) AND
• if the data length code is greater than 0, at least one bit in the data field of the
received frame is set and the corresponding bit in the associated data mask register is
also set AND
• the CRC field in the received frame (including a recessive CRC delimiter) was
received without error
If the TJA1145 receives a CAN message containing errors (e.g. a ‘stuffing’ error)
transmitted in advance of the ACK field, an internal error counter is incremented. If a CAN
message is received without any errors appearing in front of the ACK field, the counter is
decremented. Data received after the CRC delimiter and before the next SOF is ignored
by the partial networking module. If the counter overflows (counter > 31), a frame detect
error is captured (PNFDE = 1) and the device wakes up; the counter is reset to zero when
the bias is switched off and partial networking is re-enabled.
Partial networking is assumed to be configured correctly when PNCOK is set to 1 by the
application software. The TJA1145 clears PNCOK after a write access to any of the CAN
partial networking configuration registers (see Section 7.3.3).
If selective wake-up is disabled (CPNC = 0) or partial networking is not configured
correctly (PNCOK = 0), and the CAN transceiver is in Offline mode with wake-up enabled
(CWE = 1), then any valid wake-up pattern (according to ISO 11898-2:2016) will trigger a
wake-up event.
If the CAN transceiver is not in Offline mode (CMC 00) or CAN wake-up is disabled
(CWE = 0), all wake-up patterns on the bus will be ignored.
CAN bit rates of 50 kbit/s, 100 kbit/s, 125 kbit/s, 250 kbit/s, 500 kbit/s and 1 Mbit/s are
supported during selective wake-up. The bit rate is selected via bits CDR (see Table 9).
7.3.2 CAN FD frames
CAN FD stands for ‘CAN with Flexible Data-Rate’. It is based on the CAN protocol as
specified in ISO 11898-1:2015.
CAN FD is being gradually introduced into the automotive market. In time, all CAN
controllers will be required to comply with the new standard (enabling ‘FD-active’ nodes)
or at least to tolerate CAN FD communication (enabling ‘FD-passive’ nodes). The
TJA1145x/FD variants support FD-passive features by means of a dedicated
implementation of the partial networking protocol.
These variants can be configured to recognize CAN FD frames as valid frames. When
CFDC = 1, the error counter is decremented every time the control field of a CAN FD
frame is received. The TJA1145x/FD remains in low-power mode (CAN FD-passive) with
partial networking enabled. CAN FD frames are never recognized as valid wake-up
frames, even if PNDM = 0 and the frame contains a valid ID. After receiving the control
field of a CAN FD frame, the TJA1145x/FD ignores further bus signals until idle is again
detected.
TJA1145
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TJA1145
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High-speed CAN transceiver for partial networking
CAN FD passive is supported up to a ratio of one-to-eight between arbitration and data bit
rates, without unwanted wake-ups. The CAN FD filter parameter defined in
ISO 11898-2:2016 and SAE J2284 is supported up to a ratio of one-to-four, with a
maximum supported bit data bit rate of 2 Mbit/s and a maximum arbitration speed of 500
kbit/s.
CAN FD frames are interpreted as frames with errors by the partial networking module in
the TJA1145, and in the TJA1145xFD variants when CFDC = 0. So the error counter is
incremented when a CAN FD frame is received. If the ratio of CAN FD frames to valid CAN
frames exceeds the threshold that triggers error counter overflow, bit PNFDE is set to 1
and the device wakes up.
7.3.3 CAN partial networking configuration registers
Dedicated registers are provided for configuring CAN partial networking.
Table 9.
Data rate register (address 26h)
Bit
Symbol
Access
Value
7:3
reserved
R
-
2:0
CDR
R/W
Table 10.
000
50 kbit/s
001
100 kbit/s
010
125 kbit/s
011
250 kbit/s
100
reserved (intended for future use; currently
selects 500 kbit/s)
101
500 kbit/s
110
reserved (intended for future use; currently
selects 500 kbit/s)
111
1000 kbit/s
ID registers 0 to 3 (addresses 27h to 2Ah)
Symbol
Access
Value
Description
27h
ID7:ID0
R/W
-
bits ID7 to ID0 of the extended frame format
7:0
28h
7:0
ID15:ID08
R/W
-
bits ID15 to ID8 of the extended frame format
29h
7:2
ID23:ID18
R/W
-
bits ID23 to ID18 of the extended frame format
bits ID5 to ID0 of the standard frame format
1:0
ID17:ID16
R/W
-
bits ID17 to ID16 of the extended frame format
7:5
reserved
R
-
4:0
ID28:ID24
R/W
-
Table 11.
Product data sheet
CAN data rate selection:
Addr. Bit
2Ah
TJA1145
Description
bits ID28 to ID24 of the extended frame format
bits ID10 to ID6 of the standard frame format
ID mask registers 0 to 3 (addresses 2Bh to 2Eh)
Addr. Bit
Symbol
Access Value
Description
2Bh
7:0
M7:M0
R/W
-
ID mask bits 7 to 0 of extended frame format
2Ch
7:0
M15:M8
R/W
-
ID mask bits 15 to 8 of extended frame format
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High-speed CAN transceiver for partial networking
Table 11.
Addr. Bit
Symbol
Access Value
Description
2Dh
7:2
M23:M18
R/W
-
ID mask bits 23 to 18 of extended frame format
ID mask bits 5 to 0 of standard frame format
1:0
M17:M16
R/W
-
ID mask bits 17 to 16 of extended frame format
2Eh
7:5
reserved
R
-
4:0
M28:M24
R/W
-
Table 12.
Product data sheet
ID mask bits 28 to 24 of extended frame format
ID mask. bits 10 to 6 of standard frame format
Frame control register (address 2Fh)
Bit
Symbol
Access
Value
Description
7
IDE
R/W
-
identifier format:
6
TJA1145
ID mask registers 0 to 3 (addresses 2Bh to 2Eh) …continued
PNDM
R/W
5:4
reserved
R
3:0
DLC
R/W
0
standard frame format (11-bit)
1
extended frame format (29-bit)
-
partial networking data mask:
0
data length code and data field are ‘don’t care’ for
wake-up
1
data length code and data field are evaluated at
wake-up
number of data bytes expected in a CAN frame:
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
1001 to
1111
tolerated, 8 bytes expected; DM0 ignored
Table 13.
Data mask registers (addresses 68h to 6Fh)
Addr.
Bit
Symbol
Access
Value
Description
68h
7:0
DM0
R/W
-
data mask 0 configuration
69h
7:0
DM1
R/W
-
data mask 1 configuration
6Ah
7:0
DM2
R/W
-
data mask 2 configuration
6Bh
7:0
DM3
R/W
-
data mask 3 configuration
6Ch
7:0
DM4
R/W
-
data mask 4 configuration
6Dh
7:0
DM5
R/W
-
data mask 5 configuration
6Eh
7:0
DM6
R/W
-
data mask 6 configuration
6Fh
7:0
DM7
R/W
-
data mask 7 configuration
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High-speed CAN transceiver for partial networking
'/&!
K
'0
'0
'0
'0
'0
'0
'0
'/&
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'0
'/&
'/&
'/&
'/&
'/&
'/&
'/&
'0
DDD
Fig 9.
Data mask register usage for different values of DLC
7.4 Fail-safe features
7.4.1 TXD dominant time-out
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in Active Mode. If the LOW state on pin TXD persists for longer than the
TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
When the TXD dominant time-out time is exceeded, a CAN failure interrupt is generated
(CF = 1; see Table 19), if enabled (CFE = 1; see Table 22). In addition, the status of the
TXD dominant time-out can be read via the CFS bit in the Transceiver status register
(Table 8) and bit CTS is set to 0.
7.4.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards VIO to ensure a safe defined recessive driver
state in case the pin is left floating.
7.4.3 VCC undervoltage event
An enabled CAN failure interrupt is generated (CF = 1) when the CAN transceiver supply
voltage on VCC falls below the undervoltage detection threshold (VUVD(VCC)), provided
CMC = 01. In addition, status bit VCS is set to 1.
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High-speed CAN transceiver for partial networking
7.4.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
7.5 Local wake-up via WAKE pin
Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture
enable register (see Table 23). A wake-up event is triggered by a LOW-to-HIGH (if
WPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This
arrangement allows for maximum flexibility when designing a local wake-up circuit. In
applications that don’t make use of the local wake-up facility, local wake-up should be
disabled and the WAKE pin connected to GND to ensure optimal EMI performance.
Table 14.
WAKE status register (address 4Bh)
Bit
Symbol
Access
Value
7:2
reserved
R
-
1
WPVS
R
0
reserved
R
Description
WAKE pin status:
0
voltage on WAKE pin below switching threshold (Vth(sw))
1
voltage on WAKE pin above switching threshold (Vth(sw))
-
While the TJA1145 is in Normal mode, the status of the voltage on pin WAKE can always
be read via bit WPVS. Otherwise, WPVS is only valid if local wake-up is enabled
(WPRE = 1 and/or WPFE = 1).
7.6 Wake-up and interrupt event diagnosis via pin RXD
Wake-up and interrupt event diagnosis in the TJA1145 is intended to provide the
microcontroller with information on the status of a range of features and functions. This
information is stored in the event status registers (Table 18 to Table 20) and is signaled on
pin RXD pin, if enabled.
A distinction is made between regular wake-up events and interrupt events (at least one
regular wake-up source must be enabled to allow the TJA1145 to switch to Sleep mode;
see Section 7.1.1.3).
TJA1145
Product data sheet
Table 15.
Regular wake-up events
Symbol
Event
Power-on Description
CW
CAN wake-up
disabled
a CAN wake-up event was detected while the
transceiver was in CAN Offline mode.
WPR
rising edge on WAKE
pin
disabled
a rising-edge wake-up was detected on pin WAKE
WPF
falling edge on WAKE disabled
pin
a falling-edge wake-up was detected on pin WAKE
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High-speed CAN transceiver for partial networking
Table 16.
Interrupt events
Symbol
Event
Power-on Description
PO
power-on
always
enabled
the TJA1145 has exited Off mode (after battery
power has been restored/connected)
OTW
overtemperature
warning
disabled
the IC temperature has exceeded the
overtemperature warning threshold (only detected
in Normal mode)
SPIF
SPI failure
disabled
SPI clock count error (only 16-, 24- and 32-bit
commands are valid), illegal MC code or
attempted write access to locked register (an SPI
failure event will not wake-up the TJA1145 from
PNFDE
PN frame detection
error
always
enabled
partial networking frame detection error
CBS
CAN bus silence
disabled
no activity on CAN bus for tto(silence) (detected only
when CBSE = 1 while bus active)
CF
CAN failure
disabled
one of the following CAN failure events detected
(not is Sleep mode):
Sleep mode)
- CAN transceiver deactivated due to a
dominant clamped TXD
- CAN transceiver deactivated due to a VCC
undervoltage event (if CMC = 01)
PO and PNFDE interrupts are always captured. Wake-up and interrupt detection can be
enabled/disabled for the remaining events individually via the event capture enable
registers (Table 21 to Table 23).
If an event occurs while the associated event capture function is enabled, the relevant
event status bit is set. If the transceiver is in CAN Offline mode, pin RXD is forced LOW to
indicate that a wake-up or interrupt event has been detected. If the TJA1145 is in Sleep
mode when an event (other than a SPIF interrupt) occurs, pin INH is forced HIGH and the
TJA1145 switches to Standby mode. If the TJA1145 is in Standby mode when the event
occurs, pin RXD is forced LOW to flag an interrupt/wake-up event. The detection of any
enabled wake-up or interrupt event will trigger a wake-up in Standby mode. The detection
of any enabled wake-up or interrupt event other than a SPIF interrupt will trigger a
wake-up in Sleep mode.
The microcontroller can monitor events via the event status registers. An extra status
register, the Global event status register (Table 17), is provided to help speed up software
polling routines. By polling the Global event status register, the microcontroller can quickly
determine the type of event captured (system, transceiver or WAKE) and then query the
relevant table (Table 18, Table 19 or Table 20 respectively).
After the event source has been identified, the status flag should be cleared (set to 0) by
writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be
cleared in a single write operation by writing 1 to all relevant bits.
It is strongly recommended to clear only the status bits that were set to 1 when the status
registers were last read. This precaution ensures that events triggered just before the
write access are not lost.
TJA1145
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High-speed CAN transceiver for partial networking
7.6.1 Interrupt/wake-up delay
If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline
mode, they can have a significant impact on the software processing time (because pin
RXD is repeatedly driven LOW, requiring a response from the microcontroller each time
an interrupt/wake-up is generated). The TJA1145 incorporates an interrupt/wake-up delay
timer to limit the disturbance to the software.
When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a
timer is started. If further events occur while the timer is running, the relevant status bits
are set. If one or more events are pending when the timer expires after td(event), pin RXD
goes LOW again to alert the microcontroller.
In this way, the microcontroller is interrupted once to process a number of events rather
than several times to process individual events. If all active event capture bits have been
cleared (by the microcontroller) when the timer expires after td(event), pin RXD remains
HIGH (since there are no pending events). The event capture registers can be read at any
time.
7.6.2 Sleep mode protection
It is very important that event detection is configured correctly when the TJA1145 switches
to Sleep mode to ensure it will respond to a wake-up event. For this reason, and to avoid
potential system deadlocks, at least one regular wake-up event must be enabled and all
event status bits must be cleared before the TJA1145 switches to Sleep mode. Otherwise
the TJA1145 will switch to Standby mode in response to a go-to-sleep command
(MC = 001).
7.6.3 Event status and event capture registers
After an event source has been identified, the status flag should be cleared (set to
0) by writing 1 to the relevant status bit (writing 0 will have no effect).
Table 17.
Bit
Symbol
Access
Value
7:4
reserved
R
-
3
WPE
R
2
TJA1145
Product data sheet
Global event status register (address 60h)
TRXE
WAKE pin event:
0
no pending WAKE pin event
1
WAKE pin event pending at address 0x64
R
1
reserved
R
0
SYSE
R
Description
transceiver event:
0
no pending transceiver event
1
transceiver event pending at address 0x63
system event:
0
no pending system event
1
system event pending at address 0x61
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Table 18.
Bit
Symbol
Access
Value
7:5
reserved
R
-
4
PO[1]
R/W
3
reserved
R
2
OTW
R/W
1
0
[1]
SPIF
reserved
no recent battery power-on
1
the TJA1145 has left Off mode after battery power-on
overtemperature warning:
0
overtemperature not detected
1
the global chip temperature has exceeded the
overtemperature warning threshold (Tth(warn)otp)
R/W
SPI failure:
R
0
no SPI failure detected
1
SPI failure detected
-
Transceiver event status register (address 63h)
Symbol
Access
Value
7:6
reserved
R
-
5
PNFDE
R/W
CBS
reserved
R
1
CF[1]
R/W
[1]
CW
Description
partial networking frame detection error:
0
no partial networking frame detection error
detected
1
partial networking frame detection error detected
R/W
3:2
0
CAN-bus status:
0
CAN-bus active
1
no activity on CAN-bus for tto(silence)
CAN failure:
0
no CAN failure detected
1
CAN failure event detected
R/W
CAN wake-up:
0
no CAN wake-up event detected
1
CAN wake-up event detected
CF is only enabled in Normal mode while the transceiver is in CAN Active mode and is triggered if TXD is
clamped dominant OR a VCC undervoltage is detected (when CMC = 01).
Table 20.
Product data sheet
power-on:
0
Bit
4
Description
PO is cleared when the TJA1145 is forced to Sleep mode due to an undervoltage event. The information
stored in PO could be lost if the transition to Sleep mode was forced by an undervoltage event. Bit NMS,
which is set to 0 when the TJA1145 switches to Normal mode after power-on, compensates for this.
Table 19.
TJA1145
System event status register (address 61h)
WAKE pin event status register (address 64h)
Bit
Symbol
Access
Value
7:2
reserved
R
-
Description
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Table 20.
WAKE pin event status register (address 64h)
Bit
Symbol
Access
1
WPR
R/W
0
WPF
Table 21.
Value
WAKE pin rising edge:
0
no rising edge detected on WAKE pin
1
rising edge detected on WAKE pin
R/W
WAKE pin falling edge:
0
no falling edge detected on WAKE pin
1
falling edge detected on WAKE pin
System event capture enable register (address 04h)
Bit
Symbol
Access
Value
7:3
reserved
R
-
2
OTWE
R/W
1
0
SPIFE
reserved
Table 22.
Description
overtemperature warning enable:
0
overtemperature warning disabled
1
overtemperature warning enabled
R/W
R
Description
SPI failure enable:
0
SPI failure detection disabled
1
SPI failure detection enabled
-
Transceiver event capture enable register (address 23h)
Bit
Symbol
Access
Value
7:5
reserved
R
-
4
CBSE
R/W
3:2
reserved
R
1
CFE
R/W
Description
CAN-bus silence enable:
0
CAN-bus silence detection disabled
1
CAN-bus silence detection enabled
CAN failure enable:
0
CAN failure detection disabled
1
0
CWE
Table 23.
Product data sheet
CAN failure detection enabled
CAN wake-up enable:
0
CAN wake-up detection disabled
1
CAN wake-up detection enabled
WAKE pin event capture enable register (address 4Ch)
Bit
Symbol
Access
Value
7:2
reserved
R
-
1
WPRE
R/W
0
TJA1145
R/W
WPFE
Description
WAKE pin rising-edge enable:
0
rising-edge detection on WAKE pin disabled
1
rising-edge detection on WAKE pin enabled
R/W
WAKE pin falling-edge enable:
0
falling-edge detection on WAKE pin disabled
1
falling-edge detection on WAKE pin enabled
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7.7 Device ID
A byte is reserved at address 0x7E for a TJA1145 identification code.
Table 24.
Identification register (address 7Eh)
Bit
Symbol
Access
7:0
IDS[7:0]
R
Value
Description
device identification code
70h
TJA1145T, TJA1145TK
74h
TJA1145T/FD, TJA1145TK/FD
7.8 Lock control register
Sections of the register address area can be write-protected to protect against unintended
modifications. Note that this facility only protects locked bits from being modified via the
SPI and will not prevent the TJA1145 updating status registers etc.
Table 25.
Lock control register (address 0Ah)
Bit
Symbol
Access
Value
Description
7
reserved
R
-
cleared for future use
6
LK6C
R/W
5
4
3
2
1
LK5C
LK4C
LK3C
LK2C
LK1C
lock control 6: address area 0x68 to 0x6F - partial
networking data byte registers
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 5: address area 0x50 to 0x5F
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 4: address area 0x40 to 0x4F - WAKE pin
configuration
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 3: address area 0x30 to 0x3F
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 2: address area 0x20 to 0x2F transceiver control and partial networking
0
SPI write-access enabled
1
SPI write-access disabled
R/W
lock control 1: address area 0x10 to 0x1F
0
1
0
TJA1145
Product data sheet
LK0C
R/W
SPI write-access enabled
SPI write-access disabled
lock control 0: address area 0x06 to 0x09 - general
purpose memory
0
SPI write-access enabled
1
SPI write-access disabled
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High-speed CAN transceiver for partial networking
7.9 General-purpose memory
TJA1145 allocates 4 bytes of memory for general-purpose registers used to store user
information. The general purpose registers can be accessed via the SPI at address 0x06
to 0x09 (see Table 26).
7.10 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage. This will cause the
signal levels of the TXD, RXD and the SPI interface pins to be adjusted to the I/O levels of
the microcontroller, enabling direct interfacing without the need for glue logic.
7.11 VCC/VIO undervoltage protection
If an undervoltage is detected on pins VCC or VIO, and it remains valid for longer than the
undervoltage detection delay time, td(uvd), the TJA1145 is forced to Sleep mode (see
Figure 4). A number of preventative measures are taken when the TJA1145 is forced to
Sleep mode to avoid deadlock and unpredictable states:
• All previously captured events (address range 0x61 to 0x64) are cleared before the
TJA1145 switches to Sleep Mode to avoid repeated attempts to wake up while an
undervoltage is present.
• Both CAN wake-up (CWE = 1) and local wake-up via the WAKE pin (WPFE =
WPRE = 1) are enabled in order to avoid a deadlock situation where the TJA1145
cannot be woken up after entering Sleep mode.
• Partial Networking is disabled (CPNC = 0) to ensure immediate wake-up in response
to bus traffic after the TJA1145 has recovered from an undervoltage event.
• The Partial Networking Configuration bit is cleared (CPNOK = 0) to indicate that
partial networking might not have been configured correctly when the TJA1145
switched to Sleep mode.
Status bit FSMS is set to 1 when a transition to Sleep mode is forced by an undervoltage
event (see Table 6). This bit can be sampled after the TJA1145 wakes up from Sleep
mode to allow the settings of CWE, WPFE, WPRE and CPNC to be re-adjusted if an
undervoltage event forced the transition to Sleep mode (FSMS = 1).
TJA1145
Product data sheet
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TJA1145
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High-speed CAN transceiver for partial networking
7.12 SPI
7.12.1 Introduction
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave operations. The SPI is configured for full duplex
data transfer, so status information is returned when new control data is shifted in. The
interface also offers a read-only access option, allowing registers to be read back by the
application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
• SCSN: SPI chip select; active LOW; default level is HIGH (pull-up)
• SCK: SPI clock; default level is LOW due to internal pull-down
• SDI: SPI data input (floating input; may need external pull-up or pull-down if not
available in the host controller)
• SDO: SPI data output; floating when pin SCSN is HIGH (may need external pull-up or
pull-down if not available in the host controller)
Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the
rising edge, as illustrated in Figure 10.
6&61
6&.
1
1
VDPSOHG
6',
6'2
;
IORDWLQJ
;
06%
06%
06%
06%
/6%
06%
06%
06%
06%
/6%
;
IORDWLQJ
DDD
Fig 10. SPI timing protocol
The SPI data in the TJA1145 is stored in a number of dedicated 8-bit registers. Each
register is assigned a unique 7-bit address. Two bytes (16 bits) must be transmitted to the
TJA1145 for a single register read or write operation. The first byte contains the 7-bit
address along with a ‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a
write operation (if this bit is 1, a read operation is assumed and any data on the SDI pin is
ignored). The second byte contains the data to be written to the register.
24- and 32-bit read and write operations are also supported. The register address is
automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as
illustrated in Figure 11.
TJA1145
Product data sheet
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
7-$5HJLVWHU$GGUHVV5DQJH
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Fig 11. SPI data structure for a write operation (16-, 24- or 32-bit)
During an SPI data read or write operation, the contents of the addressed register(s) is
returned via pin SDO.
The TJA1145 tolerates attempts to write to registers that don't exist. If the available
address space is exceeded during a write operation, the data above the valid address
range is ignored (without generating an SPI failure event).
During a write operation, the TJA1145 monitors the number of SPI bits transmitted. If the
number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure
event is captured (SPIF = 1).
If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on
SDI is reflected on SDO from bit 33 onwards.
7.12.2 Register map
The addressable register space contains 128 registers with addresses from 0x00 to 0x7F.
An overview of the register mapping is provided in Table 26 to Table 30. The functionality
of the individual bits is discussed in more detail in relevant sections of the data sheet.
Table 26.
Address
Overview of primary control registers
Register Name
Bit:
7
6
0x01
Mode control
0x03
Main status
FSMS
0x04
System event enable
reserved
0x06
Memory 0
GPM[7:0]
0x07
Memory 1
GPM[15:8]
TJA1145
Product data sheet
5
4
3
reserved
2
1
0
SPIFE
reserved
MC
OTWS
NMS
reserved
OTWE
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High-speed CAN transceiver for partial networking
Table 26.
Address
Overview of primary control registers
Register Name
Bit:
7
6
0x08
Memory 2
GPM[23:16]
0x09
Memory 3
GPM[31:24]
0x0A
Lock control
reserved LK6C
Table 27.
Address
5
4
3
2
1
0
LK5C
LK4C
LK3C
LK2C
LK1C
LK0C
2
1
0
Overview of transceiver control and partial networking registers
Register Name
Bit:
7
6
5
4
3
0x20
CAN control
reserved
CFDC
PNCOK
CPNC
reserved
0x22
Transceiver status
CTS
CPNERR
CPNS
COSCS
CBSS
0x23
Transceiver event
enable
reserved
CBSE
reserved
0x26
Data rate
reserved
0x27
Identifier 0
ID[7:0]
0x28
Identifier 1
ID[15:8]
0x29
Identifier 2
ID[23:16]
0x2A
Identifier 3
reserved
0x2B
Mask 0
M[7:0]
0x2C
Mask 1
M[15:8]
0x2D
Mask 2
M[23:16]
0x2E
Mask 3
reserved
0x2F
Frame control
IDE
0x68
Data mask 0
DM0[7:0]
0x69
Data mask 1
DM1[7:0]
0x6A
Data mask 2
DM2[7:0]
0x6B
Data mask 3
DM3[7:0]
0x6C
Data mask 4
DM4[7:0]
0x6D
Data mask 5
DM5[7:0]
0x6E
Data mask 6
DM6[7:0]
0x6F
Data mask 7
DM7[7:0]
Table 28.
CMC
reserved VCS
CFE
CFS
CWE
CDR
ID[28:24]
M[28:24]
PNDM
reserved
DLC
Overview of WAKE pin control and status registers
Address
Register Name
Bit:
1
0
0x4B
WAKE pin status
reserved
WPVS
reserved
0x4C
WAKE pin enable
reserved
WPRE
WPFE
7
TJA1145
Product data sheet
6
5
4
3
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High-speed CAN transceiver for partial networking
Table 29.
Overview of Event Capture registers
Address
Register Name
Bit:
7
6
0x60
Event capture status
reserved
0x61
System event status
reserved
0x63
Transceiver event status
reserved
0x64
WAKE pin event status
reserved
Table 30.
Overview of Identification register
Address
Register Name
Identification
TJA1145
Product data sheet
PNFDE
4
3
2
1
0
WPE
TRXE
reserved SYSE
PO
reserved OTW
SPIF
reserved
CBS
reserved
CF
CW
WPR
WPF
1
0
Bit:
7
0x7E
5
6
5
4
3
2
IDS[7:0]
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7.12.3 Register configuration in TJA1145 operating modes
A number of register bits may change state automatically when the TJA1145 switches
from one operating mode to another. This is particularly evident when the TJA1145
switches to Off mode or when an undervoltage event forces a transition to Sleep mode.
These changes are summarized in Table 31. If an SPI transmission is in progress when
the TJA1145 changes state, the transmission is ignored (automatic state changes have
priority).
Table 31.
Register bit settings in TJA1145 operating modes
Symbol
Off (reset values)
Standby
Normal
Sleep
Overtemp
Forced Sleep (uv)
CBS
0
no change
no change
no change
no change
0
CBSE
0
no change
no change
no change
no change
no change
CBSS
1
actual state
actual state
actual state
actual state
actual state
CDR
101
no change
no change
no change
no change
no change
CF
0
no change
no change
no change
no change
0
CFDC
0
no change
no change
no change
no change
no change
CFE
0
no change
no change
no change
no change
no change
CFS
0
actual state
actual state
actual state
actual state
actual state
CMC
00
no change
no change
no change
no change
no change
COSCS
0
actual state
actual state
actual state
actual state
actual state
CPNC
0
no change
no change
no change
no change
0
CPNERR
1
actual state
actual state
actual state
actual state
actual state
CPNS
0
actual state
actual state
actual state
actual state
actual state
CTS
0
0
actual state
0
0
0
CW
0
no change
no change
no change
no change
0
CWE
0
no change
no change
no change
no change
1
DMn
11111111
no change
no change
no change
no change
no change
DLC
0000
no change
no change
no change
no change
no change
FSMS
0
no change
no change
0
no change
1
GPMn
00000000
no change
no change
no change
no change
no change
IDn
00000000
no change
no change
no change
no change
no change
IDE
0
no change
no change
no change
no change
no change
IDS
01110000 (T, TK)
01110100 (T/FD, TK/FD)
no change
no change
no change
no change
no change
LKnC
0
no change
no change
no change
no change
no change
Mn
00000000
no change
no change
no change
no change
no change
MC
100
100
111
001
don’t care
001
NMS
1
no change
0
no change
no change
no change
OTW
0
no change
no change
no change
no change
0
OTWE
0
no change
no change
no change
no change
no change
OTWS
0
actual state
actual state
actual state
actual state
actual state
PNCOK
0
no change
no change
no change
no change
0
PNDM
1
no change
no change
no change
no change
no change
PNFDE
0
no change
no change
no change
no change
0
TJA1145
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Table 31.
Register bit settings in TJA1145 operating modes …continued
Symbol
Off (reset values)
Standby
Normal
Sleep
Overtemp
Forced Sleep (uv)
PO
1
no change
no change
no change
no change
0
SPIF
0
no change
no change
no change
no change
0
SPIFE
0
no change
no change
no change
no change
no change
SYSE
1
no change
no change
no change
no change
0
TRXE
0
no change
no change
no change
no change
0
VCS
0
actual state
actual state
actual state
actual state
actual state
WPE
0
no change
no change
no change
no change
0
WPF
0
no change
no change
no change
no change
0
WPFE
0
no change
no change
no change
no change
1
WPR
0
no change
no change
no change
no change
0
WPRE
0
no change
no change
no change
no change
1
WPVS
0
no change
no change
no change
no change
no change
TJA1145
Product data sheet
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8. Limiting values
Table 32. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
voltage on pin
Vx
Conditions
x[1]
V(CANH-CANL)
voltage between pin CANH
and pin CANL
Vtrt
transient voltage
Min
Max
Unit
pins VCC, VIO
[2]
0.2
+6
V
pins TXD, RXD, SDI, SDO, SCK, SCSN
[3]
0.2
VIO + 0.2
V
pins WAKE, INH
18
+40
V
pin BAT
0.2
+40
V
pins CANH and CANL with respect to any
other pin
58
+58
V
40
+40
V
pulse 1
100
-
V
pulse 2a
-
75
V
pulse 3a
150
-
V
-
100
V
6
+6
kV
8
+8
kV
4
+4
kV
2
+2
kV
100
+100
V
750
+750
V
500
+500
V
40
+150
C
55
+150
C
on pins
[4]
BAT via reverse polarity diode and
capacitor to ground
CANL, CANH, WAKE
pulse 3b
VESD
IEC 61000-4-2 (150 pF, 330 )
electrostatic discharge
voltage
[5]
on pins CANH and CANL; pin BAT with
100 nF capacitor; pin WAKE with 10 nF
capacitor and 10 k resistor
Human Body Model (HBM); 100 pF, 1.5 k
on pins CANH, CANL
[6]
[7]
on pins BAT, WAKE
on any other pin
Machine Model (MM); 200 pF, 0.75 H, 10
[8]
on any pin
Charged Device Model (CDM); field Induced
charge; 4 pF
[9]
on corner pins
on any other pin
Tvj
virtual junction temperature
Tstg
storage temperature
[10]
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2]
When the device is not powered up, IVCC(max) = 25 mA.
[3]
Maximum voltage should never exceed 6 V.
[4]
According to IEC TS 62228 (2007), Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2: 2004-06.
[5]
According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[6]
According to AEC-Q100-002.
[7]
VCC, VIO and BAT connected to GND, emulating the application circuit.
TJA1145
Product data sheet
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TJA1145
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High-speed CAN transceiver for partial networking
[8]
According to AEC-Q100-003.
[9]
According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[10] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(j-a), where Rth(j-a) is a
fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
9. Thermal characteristics
Table 33.
Thermal characteristics
Symbol
Parameter
Rth(vj-a)
thermal resistance from virtual junction to ambient SO14
Conditions
HVSON14
[1]
[1]
Typ
Unit
106
K/W
60
K/W
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 µm) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
10. Static characteristics
Table 34. Static characteristics
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin BAT
Vth(det)pon
power-on detection threshold VBAT rising
voltage
4.2
-
4.55
V
Vth(det)poff
power-off detection threshold VBAT falling
voltage
2.8
-
3
V
Vuvr(CAN)
CAN undervoltage recovery
voltage
VBAT rising
4.5
-
5
V
Vuvd(CAN)
CAN undervoltage detection
voltage
VBAT falling
4.2
-
4.55
V
IBAT
battery supply current
Sleep mode; MC = 001; CWE = 1;
CAN Offline mode;
40 C < Tvj < 85 C;
VBAT = 7 V to 18 V
-
40
59
A
Standby mode; MC = 100; CWE = 1;
CAN Offline mode;
40 C < Tvj < 85 C;
VBAT = 7 V to 18 V
-
44
68
A
additional current in CAN Offline Bias
mode; 40 C < Tvj < 85 C
-
46
63
A
additional current in CAN Offline Bias
mode with active partial networking
decoder; Standby or Sleep mode;
40 C < Tvj < 85 C
0.4
0.65
mA
additional current from WAKE input;
WPRE = WPFE = 1; 40 C <
Tvj < 85 C
2
3
A
-
1
1.5
mA
4.5
-
4.75
V
CAN Active mode; CAN recessive;
VTXD = VIO
-
3
6
mA
CAN Active mode; CAN dominant;
VTXD = 0 V
-
45
65
mA
Standby/Normal mode; CAN inactive;
40 C < Tvj < 85 C
-
4.7
8.5
A
Sleep mode; CAN inactive;
40 C < Tvj < 85 C
-
3.8
7
A
short circuit on bus lines; CAN
dominant; VTXD = 0 V;
3 V < (VCANH = VCANL) < +18 V
-
55
65
mA
Normal mode; MC = 111
Supply; pin VCC
Vuvd(VCC)
undervoltage detection
voltage on pin VCC
ICC
supply current
TJA1145
Product data sheet
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TJA1145
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High-speed CAN transceiver for partial networking
Table 34. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.7
-
2.85
V
Supply; pin VIO
Vuvd(VIO)
undervoltage detection
voltage on pin VIO
VBAT > 4.5 V
IIO
supply current on pin VIO
40 C < Tvj < 85 C
Standby/Normal mode
-
7.1
11
A
Sleep mode
-
5
8
A
Serial peripheral interface inputs; pins SDI, SCK and SCSN
Vth(sw)
switching threshold voltage
VIO = 2.97 V to 5.5 V
0.25VIO
-
0.75VIO
V
Vth(sw)hys
switching threshold voltage
hysteresis
VIO = 2.97 V to 5.5 V
0.05VIO
-
-
V
Rpd(SCK)
pull-down resistance on pin
SCK
40
60
80
k
Rpu(SCSN)
pull-up resistance on pin
SCSN
40
60
80
k
ILI(SDI)
input leakage current on pin
SDI
5
-
+5
A
Serial peripheral interface data output; pin SDO
VOH
HIGH-level output voltage
IOH = 4 mA
VIO 0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
ILO(off)
off-state output leakage
current
VSCSN = VIO; VO = 0 V to VIO
5
-
+5
A
Inhibit output: pin INH
VO
output voltage
IINH = 180 A
VBAT 0.8 -
VBAT
V
Rpd
pull-down resistance
Sleep mode
3
4
5
M
VIO = 2.97 V to 5.5 V
0.25VIO
-
0.75VIO
V
40
60
80
k
CAN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
Rpu
pull-up resistance
CAN receive data output; pin RXD
VOH
HIGH-level output voltage
IOH = 4 mA
VIO 0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
Rpu
pull-up resistance
CAN Offline mode
40
60
80
k
Local wake input; pin WAKE
Vth(sw)r
rising switching threshold
voltage
2.8
-
4.1
V
Vth(sw)f
falling switching threshold
voltage
2.4
-
3.75
V
Vhys(i)
input hysteresis voltage
250
-
800
mV
Ii
input current
-
-
1.5
A
TJA1145
Product data sheet
40 C < Tvj < 85 C
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 34. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pin CANH; RL = 50 to 65
2.75
3.5
4.5
V
pin CANL; RL = 50 to 65
0.5
1.5
2.25
V
400
-
+400
mV
0.9VCC
-
1.1VCC
V
RL = 45 to 70
1.5
-
3
V
RL = 2240
1.5
-
5
V
CAN Active/Listen-only/Offline Bias
mode; VTXD = VIO
50
-
+50
mV
CAN Offline mode
0.2
-
+0.2
V
CAN Active mode; VTXD = VIO
2
0.5VCC 3
V
CAN Offline mode
0.1
-
+0.1
V
CAN Offline Bias/Listen-only
modes; VCC = 0 V
2
2.5
3
V
50
-
-
mA
High-speed CAN bus lines; pins CANH and CANL
VO(dom)
dominant output voltage
CAN Active mode; VTXD = 0 V;
t < tto(dom)TXD
Vdom(TX)sym
transmitter dominant voltage Vdom(TX)sym = VCC VCANH VCANL;
symmetry
VCC = 5 V
VTXsym
transmitter voltage symmetry VTXsym = VCANH + VCANL;
fTXD = 250 kHz or 1 MHz;
VCC = 4.75 V to 5.25 V;
CSPLIT = 4.7 nF
VO(dif)
differential output voltage
[2]
[3]
dominant; Normal mode; VTXD = 0 V;
CAN Active mode; t < tto(dom)TXD; VCC
= 4.75 V to 5.5 V
recessive; no load
VO(rec)
IO(sc)dom
recessive output voltage
R(CANH-CANL) = no load
dominant short-circuit output CAN Active mode;
current
VTXD = 0 V; VCC = 5 V
pin CANH; VCANH = 15 V to +27 V
pin CANL; VCANL = 15 V to +27 V
-
-
52
mA
3
-
+3
mA
CAN Active/Listen-only modes
0.5
0.7
0.9
V
CAN Offline mode
0.4
0.7
1.15
V
CAN Active/Listen-only modes
4
-
0.5
V
CAN Offline mode
4
-
0.4
V
IO(sc)rec
recessive short-circuit output VCANL = VCANH = 27 V to +32 V;
current
VTXD = VIO
Vth(RX)dif
differential receiver threshold 12 V VCANL +12 V;
voltage
12 V VCANH +12 V
Vrec(RX)
receiver recessive voltage
TJA1145
Product data sheet
12 V VCANL +12 V;
12 V VCANH +12 V
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TJA1145
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High-speed CAN transceiver for partial networking
Table 34. Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified[1].
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vdom(RX)
receiver dominant voltage
12 V VCANL +12 V;
12 V VCANH +12 V
CAN Active/Listen-only modes
0.9
-
9.0
V
CAN Offline mode
1.15
-
9.0
V
Vhys(RX)dif
differential receiver
hysteresis voltage
CAN Active/Listen-only modes;
12 V VCANL +12 V;
12 V VCANH +12 V
50
200
400
mV
Ri
input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
9
15
28
k
Ri
input resistance deviation
0 V VCANL +5 V;
0 V VCANH +5 V
1
-
+1
%
Ri(dif)
differential input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
19
30
52
k
Ci(cm)
common-mode input
capacitance
[2]
-
-
20
pF
Ci(dif)
differential input capacitance
[2]
-
-
10
pF
IL
leakage current
5
-
+5
A
VBAT = VCC = 0 V or VBAT = VCC =
shorted to ground via 47 k;
VCANH = VCANL = 5 V
Temperature protection
Tth(act)otp
overtemperature protection
activation threshold
temperature
167
177
187
C
Tth(rel)otp
overtemperature protection
release threshold
temperature
127
137
147
C
Tth(warn)otp
overtemperature protection
warning threshold
temperature
127
137
147
C
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
Not tested in production; guaranteed by design.
[3]
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 17.
TJA1145
Product data sheet
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TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
11. Dynamic characteristics
Table 35. Dynamic characteristics
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
from VBAT exceeding the
power-on detection threshold
until INH active
-
2.8
4.7
ms
6
-
54
s
200
-
400
ms
Voltage sources; pins BAT, VCC and VIO
tstartup
start-up time
td(uvd)
undervoltage detection delay time
td(uvd-sleep)
delay time from undervoltage
detection to sleep mode
from undervoltage detection on
VCC and/or VIO until TJA1145
forced to Sleep mode
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO in Normal, Standby and Sleep modes
tcy(clk)
tSPILEAD
tSPILAG
tclk(H)
tclk(L)
tsu(D)
th(D)
tv(Q)
tWH(S)
td(SCKL-SCSNL)
clock cycle time
SPI enable lead time
SPI enable lag time
clock HIGH time
clock LOW time
data input set-up time
data input hold time
data output valid time
chip select pulse width HIGH
Normal/Standby modes
250
-
-
ns
Sleep mode
1
-
-
s
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
Normal/Standby modes
100
-
-
ns
Sleep mode
475
-
-
ns
Normal/Standby modes
100
-
-
ns
Sleep mode
475
-
-
ns
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
Normal/Standby modes
50
-
-
ns
Sleep mode
200
-
-
ns
pin SDO; CL = 20 pF;
Normal/Standby modes
-
-
50
ns
pin SDO; CL = 20 pF; Sleep mode
-
-
200
ns
pin SCSN; Normal/Standby
modes
250
-
-
ns
pin SCSN; Sleep mode
1
-
-
s
50
-
-
ns
delay time from SCK LOW to
SCSN LOW
CAN transceiver timing; pins CANH, CANL, TXD and RXD
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
30 % VTXD to 30 % VRXD;
RL = 60 ; CL = 100 pF;
CRXD = 15 pF;
fTXD = 250 kHz
-
-
255
ns
td(TXDH-RXDH)
delay time from TXD HIGH to RXD
HIGH
70 % VTXD to 70 % VRXD;
RL = 60 ; CL = 100 pF;
CRXD = 15 pF;
fTXD = 250 kHz
-
-
255
ns
TJA1145
Product data sheet
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41 of 57
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 35. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td(TXD-busdom)
delay time from TXD to bus dominant
-
80
-
ns
td(TXD-busrec)
delay time from TXD to bus
recessive
-
80
-
ns
td(busdom-RXD)
delay time from bus dominant to
RXD
CRXD = 15 pF
-
105
-
ns
td(busrec-RXD)
delay time from bus recessive to
RXD
CRXD = 15 pF
-
120
-
ns
tbit(bus)
transmitted recessive bit width
tbit(TXD) = 500 ns
[2]
435
-
530
ns
[2]
tbit(RXD)
bit time on pin RXD
tbit(TXD) = 500 ns
400
-
550
ns
trec
receiver timing symmetry
tbit(TXD) = 500 ns
65
-
+40
ns
twake(busdom)
bus dominant wake-up time
first pulse (after first recessive) for
wake-up on pins CANH and
CANL; CAN Offline mode
0.5
-
3.0
s
second pulse for wake-up on pins
CANH and CANL
0.5
-
3.0
s
first pulse for wake-up on pins
CANH and CANL;
CAN Offline mode
0.5
-
3.0
s
second pulse (after first
dominant) for wake-up on pins
CANH and CANL
0.5
-
3.0
s
between first and second
dominant pulses; CAN Offline
mode
570
-
1200
s
twake(busrec)
bus recessive wake-up time
tto(wake)bus
bus wake-up time-out time
tto(dom)TXD
TXD dominant time-out time
CAN Active mode; VTXD = 0 V
2.7
-
3.3
ms
tto(silence)
bus silence time-out time
recessive time measurement
started in all CAN modes; RL =
120
0.95
-
1.17
s
td(busact-bias)
delay time from bus active to bias
-
-
200
s
tstartup(CAN)
CAN start-up time
when switching to Active mode
(CTS = 1)
-
-
220
s
tfltr(wake)bus
bus wake-up filter time
CAN Offline mode
0.5
-
3
s
6
-
10
-
5
-
17.5
%
CAN partial networking
Nbit(idle)
number of idle bits
before a new SOF is accepted;
CFDC = 1
tfltr(bit)dom
dominant bit filter time
arbitration data rate 500 kbit/s;
CFDC = 1
[3]
Pin RXD: interrupt/wake-up event timing (valid in CAN Offline mode only) change to interrupt response time
td(event)
event capture delay time
CAN Offline mode
0.9
-
1.1
ms
tblank
blanking time
when switching from Offline to
Active/Listen-only mode
-
-
25
s
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
42 of 57
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
Table 35. Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; VCC = 4.5 V to 5.5 V; R(CANH-CANL) = 60 ; all voltages
are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise
specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
50
-
-
s
-
-
100
s
Pin WAKE
twake
wake-up time
Pin INH
td(buswake-INHH) delay time from bus wake-up to INH
HIGH
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 14.
[3]
Up to 2 Mbit/s data speed.
+,*+
7;'
/2:
&$1+
&$1/
GRPLQDQW
9
92 GLI
9
UHFHVVLYH
+,*+
5;'
/2:
WG 7;'EXVGRP
WG 7;'EXVUHF
WG EXVGRP5;'
WG 7;'/5;'/
WG EXVUHF5;'
WG 7;'+5;'+
DDD
Fig 12. CAN transceiver timing diagram
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
43 of 57
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
6&61
W63,/($'
W:+ 6
WFON + WFON /
WG 6&./6&61/
6&.
W63,/$*
WF\ FON
;
WK '
WVX '
6',
;
6'2
WK '
WY 4
06%
;
/6%
06%
;
/6%
;
WLPH
DDD
Fig 13. SPI timing diagram
7;'
[WELW 7;'
WELW 7;'
9
92 GLI
9
WELW EXV
5;'
WELW 5;'
DDD
Fig 14. CAN FD timing definitions according to ISO 11898-2:2016
TJA1145
Product data sheet
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Rev. 4 — 09 May 2018
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44 of 57
TJA1145
NXP Semiconductors
High-speed CAN transceiver for partial networking
12. Application information
12.1 Application diagram
9
%$7
)
9
9%$7
Nȍ
,1+
9&&
9,2
9&&
:$.(
Q)
7-$
*1'
6&61
6&.
57
VWDQGDUG
&SRUWV
6',
5;'
7;'
5;'
7;'
966
&$1+
0,&52
&21752//(5
6'2
&$1/
57
DDD
(1) Optional, depends on regulator.
(2) For bus line end nodes, RT = 60 in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’
termination of e.g. RT = 1.3 k can be used, if required by the OEM.
Fig 15. Typical application using the TJA1145
12.2 Application hints
Further information on the application of the TJA1145 can be found in the NXP application
hints document TR1309 Application Hints - High speed CAN transceiver for partial
networking TJA1145.
TJA1145
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 09 May 2018
© NXP Semiconductors N.V. 2018. All rights reserved.
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High-speed CAN transceiver for partial networking
13. Test information
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13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
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14. Package outline
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15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 36 and 37
Table 36.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 37.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
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maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17. Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
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18. Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 38.
ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)dom
Absolute current on CAN_L
ICAN_L
dominant short-circuit output
current
VO(rec)
recessive output voltage
HS-PMA dominant output characteristics
Differential voltage on effective resistance during
arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
Differential output voltage
VDiff
VO(dif)
differential output voltage
tdom
tto(dom)TXD
TXD dominant time-out time
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
Dominant state differential input voltage range
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
Ri
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to
RXD LOW
HS-PMA implementation loop delay requirement
Loop delay
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
tRec
trec
receiver timing symmetry
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Table 38.
ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
Maximum rating VDiff
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
General maximum rating VCAN_H and VCAN_L
VCAN_H
VCAN_L
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Optional: Extended maximum rating VCAN_H and
VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
Nbit(idle)
number of idle bits
Number of recessive bits before next SOF
Number of recessive bits before a new SOF shall be NBits_idle
accepted
Bitfiter in CAN FD data phase
CAN FD data phase bitfilter (option 1)
pBitfilteroption1 tfltr(bit)dom
dominant bit filter time
HS-PMA bus biasing control timings
CAN activity filter time, long
tFilter
twake(busdom)[1] bus dominant wake-up time
twake(busrec)[1]
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
Timeout for bus inactivity
tSilence
tto(silence)
bus silence time-out time
Bus Bias reaction time
tBias
td(busact-bias)
delay time from bus active to bias
CAN activity filter time, short
Wake-up timeout, short
Wake-up timeout, long
[1]
tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
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19. Revision history
Table 39.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJA1145 v.4
20180509
Product data sheet
-
TJA1145 v.3.1
Modifications:
•
Updated to comply with ISO 11898-2:2016 and SAE J22884-1 through SAE J2284-4 specifications:
– Section 1: text amended (2nd last paragraph)
– Section 2.1: text amended (1st entry)
– Table 34: values changed and/or measurements conditions amended/added for parameters ICC,
IBAT, VTXsym, IO(sc)dom,, Vrec(RX), Vdom(RX), Ri, Ri and Ri(dif)
– Table 35: parameters added - Nbit(idle), tfltr(bit)dom, td(SCKL-SCSNL); values changed and/or
measurements conditions amended for tclk(H), tclk(L) and tfltrwake)bus; SPI parameters apply in
Normal, Standby and Sleep modes
– Table 35: Table note 3 added
– Table 38: ISO/NXP parameters added: NBits_idle/Nbit(idle) and pBitfilteroption1/tfltr(bit)dom
– Figure 14: title changed
•
•
•
•
•
•
Figure 5: Figure note 1 amended (‘or CAN Listen-only mode’ added)
Table 7: description for symbol CPNC and CMC changed
Table 8: description for symbol CPNERR changed; Table note 1 added
Table 16: description for symbol CBS changed
Section 7.2, Section 7.2.1.2, Section 7.3.1, Section 7.3.2 and Table 16: text amended
Amended Figure 12, Figure 13, Figure 15 and Figure 17
TJA1145 v.3.01 20160608
Product data sheet
-
TJA1145 v.2
TJA1145 v.2
20140418
Product data sheet
-
TJA1145 v.1
TJA1145 v.1
20130927
Product data sheet
-
-
TJA1145
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20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
TJA1145
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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22. Contents
1
2
2.1
2.2
2.3
2.4
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.1.1
7.1.1.2
7.1.1.3
7.1.1.4
7.1.1.5
7.1.1.6
7.1.2
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.4
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.6
7.6.1
7.6.2
7.6.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Designed for automotive applications. . . . . . . . 2
Advanced ECU power management system . . 2
Protection and diagnosis . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 3
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
System controller . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware characterization for the TJA1145
operating modes . . . . . . . . . . . . . . . . . . . . . . . . 9
System control registers . . . . . . . . . . . . . . . . . . 9
High-speed CAN transceiver . . . . . . . . . . . . . 10
CAN operating modes . . . . . . . . . . . . . . . . . . 10
CAN Active mode . . . . . . . . . . . . . . . . . . . . . . 10
CAN Listen-only mode . . . . . . . . . . . . . . . . . . 12
CAN Offline and Offline Bias modes. . . . . . . . 12
CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 13
CAN standard wake-up (partial networking not
enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CAN control and Transceiver status registers 14
CAN partial networking . . . . . . . . . . . . . . . . . . 16
Wake-up frame (WUF) . . . . . . . . . . . . . . . . . . 16
CAN FD frames . . . . . . . . . . . . . . . . . . . . . . . 18
CAN partial networking configuration registers 19
Fail-safe features . . . . . . . . . . . . . . . . . . . . . . 21
TXD dominant time-out. . . . . . . . . . . . . . . . . . 21
Pull-up on TXD pin . . . . . . . . . . . . . . . . . . . . . 21
VCC undervoltage event . . . . . . . . . . . . . . . . . 21
Loss of power at pin BAT . . . . . . . . . . . . . . . . 22
Local wake-up via WAKE pin . . . . . . . . . . . . . 22
Wake-up and interrupt event diagnosis via pin
RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupt/wake-up delay . . . . . . . . . . . . . . . . . 24
Sleep mode protection . . . . . . . . . . . . . . . . . . 24
Event status and event capture registers . . . . 24
7.7
7.8
7.9
7.10
7.11
7.12
7.12.1
7.12.2
7.12.3
8
9
10
11
12
12.1
12.2
13
13.1
14
15
16
16.1
16.2
16.3
16.4
17
18
19
20
20.1
20.2
20.3
20.4
21
22
Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock control register. . . . . . . . . . . . . . . . . . . .
General-purpose memory . . . . . . . . . . . . . . .
VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . .
VCC/VIO undervoltage protection . . . . . . . . . .
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Register map . . . . . . . . . . . . . . . . . . . . . . . . .
Register configuration in TJA1145 operating
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics. . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Application diagram . . . . . . . . . . . . . . . . . . . .
Application hints . . . . . . . . . . . . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering of HVSON packages . . . . . . . . . . .
Appendix: ISO 11898-2:2016 parameter
cross-reference list . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
28
28
28
29
29
30
33
35
36
36
41
45
45
45
46
46
47
49
49
49
49
49
50
51
52
54
55
55
55
55
56
56
57
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 09 May 2018
Document identifier: TJA1145
工商网监
湘ICP备2023018690号
