TJR1448
Dual high-speed CAN transceiver with Standby mode
Rev. 2 — 15 October 2021
1
Product data sheet
General description
The TJR1448 is a member of the TJR144x family of transceivers that provide an
interface between a Controller Area Network (CAN) or CAN FD (Flexible Data rate)
protocol controller and the physical two-wire CAN bus. TJR144x transceivers implement
the CAN physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE
J2284-5, and are fully interoperable with high-speed Classical CAN and CAN FD
transceivers. All TJR144x variants enable reliable communication in the CAN FD fast
phase at data rates up to 5 Mbit/s and are qualified to AEC-Q100 Grade 0, supporting
operation at 150 °C ambient temperature.
The TJR1448 is intended as a simple replacement for dual high-speed Classical CAN
and CAN FD transceivers, such as the TJA1059 from NXP. It offers pin compatibility and
is designed to avoid changes to hardware and software design, allowing the TJR1448 to
be easily retrofitted to existing applications.
An AEC-Q100 Grade 1 variant, the TJA1448, is available to support operation at 125 °C
ambient temperature.
1.1 TJR1448 variants
The TJR1448 comes in three variants. The TJR1448A and TJR1448B are available in
SO14 and HVSON14 packages. The TJR1448C comes in a HVSON14 package:
• The TJR1448A is a dual high-speed CAN transceiver with Normal and Standby modes
and a VIO supply pin. The VIO pin allows for direct interfacing with 3.3 V and 5 Vsupplied microcontrollers.
• The TJR1448B is a high-speed CAN transceiver with Normal and Standby modes.
• The TJR1448C is a dual high-speed CAN transceiver with Normal and Standby modes,
a VIO supply pin and RXD latching. The VIO pin allows for direct interfacing with 3.3 V
and 5 V-supplied microcontrollers.
2
Features and benefits
2.1 General
•
•
•
•
•
•
ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant
Standard CAN and CAN FD data bit rates up to 5 Mbit/s
Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI)
Qualified according to AEC-Q100 Grade 0
TJR1448A/C only: VIO input for interfacing with 3.3 V to 5 V microcontrollers
Fully independent control of two transceivers combined monolithically in a single
package
TJR1448
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
• All variants are available in a leadless HVSON14 (3.0 mm x 4.5 mm) package with
improved Automated Optical Inspection (AOI) capability; TJR1448A/B available in an
SO14 package.
• Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.2 Predictable and fail-safe behavior
• Undervoltage detection with defined handling on all supply pins
• Full functionality guaranteed from the undervoltage detection thresholds up to the
maximum limiting voltage values
• Defined behavior below the undervoltage detection thresholds
• Transceiver disengages from the bus (high-ohmic) when the supply voltage drops
below the Off mode threshold
• Internal biasing of TXD and mode selection input pins, to enable defined fail-safe
behavior
2.3 Low-power management
• Very low-current Standby mode with host and bus wake-up capability
• TJR1448A/C only: CAN wake-up receiver powered by VIO allowing VCC to be shut
down
• CAN wake-up pattern filter time of 0.5 μs to 1.8 μs meeting Classical CAN and CAN FD
requirements
• TJR1448C variant offers RXD wake-up latching to enable wake-up source readout in
gateway applications
2.4 Protection
•
•
•
•
TJR1448
Product data sheet
High ESD handling capability on the bus pins (8 kV IEC and HBM)
Bus pins protected against transients in automotive environments
Transmit Data (TXD) dominant time-out function
Thermally protected
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
3
Quick reference data
Table 1. Quick reference data
Symbol
Parameter
VCC
supply voltage
ICC
supply current
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
both channels recessive
-
8
14
mA
one channel dominant
-
42
67
mA
both channels dominant
-
77
120
mA
TJR1448A/C
-
-
2
μA
TJR1448B
-
11
18
μA
Normal mode
both channels in Standby mode
Vuvd(stb)(VCC)
standby undervoltage detection
voltage on pin VCC
4
-
4.5
V
Vuvhys(stb)(VCC)
standby undervoltage hysteresis
voltage on pin VCC
50
-
-
mV
Vuvd(swoff)(VCC)
switch-off undervoltage detection TJR1448B
voltage on pin VCC
2.65
-
2.95
V
VIO
supply voltage on pin VIO
2.95
-
5.5
V
IIO
supply current on pin VIO
both channels recessive
-
270
750
μA
one channel dominant
-
360
1000
μA
both channels dominant
-
450
1250
μA
both channels in Standby mode
-
11
16
μA
2.65
-
2.95
V
Normal mode
Vuvd(swoff)(VIO)
switch-off undervoltage detection
voltage on pin VIO
VESD
electrostatic discharge voltage
IEC 61000-4-2 on pins CANHx and
CANLx
-8
-
+8
kV
VCANH
voltage on pin CANH
pins CANH1 and CANH2; limiting value
according to IEC 60134
-36
-
+40
V
VCANL
voltage on pin CANL
pins CANL1 and CANL2; limiting value
according to IEC 60134
-36
-
+40
V
Tvj
virtual junction temperature
-40
-
+175
°C
TJR1448
Product data sheet
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
4
Ordering information
Table 2. Ordering information
Type number
TJR1448AT
Package
Name
Description
Version
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
HVSON14
plastic thermal enhanced very thin small outline package; no
leads; 14 terminals; body 3 × 4.5 × 0.85 mm
SOT1086-2
TJR1448BT
TJR1448ATK
TJR1448BTK
TJR1448CTK
Table 3. TJR1448 feature overview
See Section 19 for a feature overview of the complete TJx144x/TJx146x/TJF1441 family.
Data rate
Additional features
●
●
●
[1]
[2]
[3]
[4]
[5]
●
●
●
●
●
●
●
[5]
TXD dominant timeout
TJR1448C
●
Single supply pin wake-up
●
Short WUP support [0.5 - 1.8 µs]
●
[2]
[3]
●
Wake-up source recognition
TJR1448B
Signal improvement
●
Up to 8 Mbit/s CAN FD
●
Up to 5 Mbit/s CAN FD
VIO pin
●
VBAT pin
VCC pin
Selectable Off
Silent/Listen-only
Standby
●
[1]
Sleep
Normal
TJR1448A
Device
●
●
Local diagnostics via ERR_N pin
Supplies
[4]
Modes
●
●
●
TJR1448 is AEC-Q100 Grade 0.
CAN FD Signal Improvement Capability (SIC) according to CiA 601-4:2019.
RXD is held LOW after wake-up request, enabling wake-up source recognition.
WUP = wake-up pattern according ISO11898-2:2016.
Only VBAT supply needed for wake-up.
TJR1448
Product data sheet
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
5
Block diagrams
VIO
VCC
11
STB1
1
TIME-OUT
SLOPE
CONTROL
AND
DRIVER
VIO
STB2
12
CANH1
CANL1
normal
receiver
MUX AND
DRIVER
4
6
WAKE-UP
FILTER
low-power
receiver
MODE
CONTROL
VIO
TXD2
13
14
VIO
RXD1
TJR1448A/C
TEMPERATURE
PROTECTION
VIO
TXD1
3
TIME-OUT
VIO
SLOPE
CONTROL
AND
DRIVER
10
9
CANH2
CANL2
normal
receiver
8
VIO
RXD2
7
MUX AND
DRIVER
WAKE-UP
FILTER
low-power
receiver
2,5
GND
aaa-039105
Figure 1. Block diagram: TJR1448A/C
TJR1448
Product data sheet
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
VCC
3
TEMPERATURE
PROTECTION
VCC
TXD1
STB1
TJR1448B
1
TIME-OUT
SLOPE
CONTROL
AND
DRIVER
VCC
STB2
CANH1
CANL1
normal
receiver
MUX AND
DRIVER
4
WAKE-UP
FILTER
low-power
receiver
MODE
CONTROL
VCC
TXD2
12
14
VCC
RXD1
13
5
TIME-OUT
VCC
SLOPE
CONTROL
AND
DRIVER
10
9
CANH2
CANL2
normal
receiver
11
VCC
RXD2
MUX AND
DRIVER
8
WAKE-UP
FILTER
7
low-power
receiver
2,6
n.c.
GND
aaa-039106
Figure 2. Block diagram: TJR1448B
TJR1448
Product data sheet
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
6
Pinning information
6.1 Pinning
TXD1
1
14 STB1
TXD1
1
14 STB1
GND
2
13 CANH1
GND
2
13 CANH1
VCC
3
12 CANL1
VCC
3
12 CANL1
RXD1
4
11 VIO
RXD1
4
11 STB2
GND
5
10 CANH2
TXD2
5
10 CANH2
TXD2
6
9
CANL2
GND
6
9
CANL2
RXD2
7
8
STB2
n.c.
7
8
RXD2
aaa-038133
aaa-038135
TJR1448AT: SO14
TJR1448BT: SO14
terminal 1
index area
terminal 1
index area
TXD1
1
14 STB1
13 CANH1
GND
2
13 CANH1
3
12 CANL1
VCC
3
12 CANL1
RXD1
4
11 VIO
RXD1
4
11 STB2
GND
5
10 CANH2
TXD2
5
10 CANH2
TXD2
6
9
CANL2
GND
6
9
CANL2
RXD2
7
8
STB2
n.c.
7
8
RXD2
TXD1
1
14 STB1
GND
2
VCC
aaa-038134
aaa-038136
TJR1448ATK/CTK: HVSON14
TJR1448BTK: HVSON14
Figure 3. Pin configuration diagrams
TJR1448
Product data sheet
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
6.2 Pin description
Table 4. Pin description: TJR1448A/C
[1]
Symbol
Pin
Type
TXD1
1
I
transmit data input 1; inputs data (from the CAN controller) to be written to CANH1/CANL1
bus lines
2
G
ground
VCC
3
P
5 V supply voltage input
RXD1
4
O
receive data output 1; outputs data read from bus lines CANH1/CANL1 (to the CAN
controller)
5
G
ground
TXD2
6
I
transmit data input 2; inputs data (from the CAN controller) to be written to CANH1/CANL1
bus lines
RXD2
7
O
receive data output 2; outputs data read from bus lines CANH2/CANL2 (to the CAN
controller)
STB2
8
I
Standby mode control input 2 (HIGH: Standby mode; LOW: Normal mode)
CANL2
9
AIO
LOW-level CAN bus line 2
CANH2
10
AIO
HIGH-level CAN bus line 2
VIO
11
P
supply voltage input for I/O level adapter
CANL1
12
AIO
LOW-level CAN bus line 1
CANH1
13
AIO
HIGH-level CAN bus line 1
STB1
14
I
Standby mode control input 1 (HIGH: Standby mode; LOW: Normal mode)
GND
GND
[1]
[2]
[2]
[2]
Description
I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.
HVSON package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For
enhanced thermal and electrical performance, it is also recommended to solder the exposed center pad to board ground.
TJR1448
Product data sheet
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
Table 5. Pin description: TJR1448B
[1]
Symbol
Pin
Type
TXD1
1
I
transmit data input 1; inputs data (from the CAN controller) to be written to CANH1/CANL1
bus lines
2
G
ground
VCC
3
P
5 V supply voltage input
RXD1
4
O
receive data output 1; outputs data read from bus lines CANH1/CANL1 (to the CAN
controller)
TXD2
5
I
transmit data input 2; inputs data (from the CAN controller) to be written to CANH2/CANL2
bus lines
6
G
ground
n.c.
7
-
not connected
RXD2
8
O
receive data output 2; outputs data read from bus lines CANH2/CANL2 (to the CAN
controller)
CANL2
9
AIO
LOW-level CAN bus line 2
CANH2
10
AIO
HIGH-level CAN bus line 2
STB2
11
I
Standby mode control input 2 (HIGH: Standby mode; LOW: Normal mode)
CANL1
12
AIO
LOW-level CAN bus line 1
CANH1
13
AIO
HIGH-level CAN bus line 1
STB1
14
I
Standby mode control input 1 (HIGH: Standby mode; LOW: Normal mode)
GND
GND
[1]
[2]
[2]
[2]
Description
I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.
HVSON package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For
enhanced thermal and electrical performance, it is also recommended to solder the exposed center pad to board ground.
TJR1448
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
7
Functional description
7.1 Operating modes
The TJR1448 supports three operating modes per transceiver, Normal, Standby and
Off. The operating mode is selected independently for each transceiver via pins STB1
and STB2. See Table 6 for a description of the operating modes under normal supply
conditions. Mode changes are completed after transition time tt(moch).
Table 6. Operating modes
Mode
Inputs
Outputs
Pin STB1/STB2 Pin TXD1/TXD2 CAN1/CAN2 driver Pin RXD1/RXD2
Normal
LOW
LOW
dominant
LOW
HIGH
recessive
LOW when bus dominant
HIGH when bus recessive
Standby
HIGH
X
biased to ground
TJR1448A/B: follows BUS when wake-up detected
TJR1448C: LOW when wake-up detected
HIGH when no wake-up detected
Off
[1]
[1]
X
X
high-ohmic state
high-ohmic state
Off mode is entered when the voltage on pin VIO (TJR1448A/C) or pin VCC (TJR1448B) is below the switch-off undervoltage detection threshold.
TJR1448
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
from any mode when
VIO < Vuvd(swoff)(VIO) for t > t uvd(swoff)
OFF
(CANx BIAS =
high-ohmic)
VIO > Vuvd(swoff)(VIO) for t > tstartup
STANDBY
(CANx BIAS =
0 V)
STBx = HIGH
OR (VCC < Vuvd(stb)(VCC) for t > tdet(uv))
STBx = LOW
AND (VCC > Vuvd(stb)(VCC) for t > t rec(uv))
NORMAL
(CANx BIAS =
VCC /2)
aaa-031273
Figure 4. TJR1448A/C state diagram (per channel)
TJR1448
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
from any mode when
VCC < Vuvd(swoff)(VCC) for t > t uvd(swoff)
OFF
(CANx BIAS =
high-ohmic)
VCC > Vuvd(swoff)(VCC) for t > t startup
STANDBY
(CANx BIAS =
0 V)
STBx = HIGH
OR (VCC < Vuvd(stb)(VCC) for t > tdet(uv))
STBx = LOW
AND (VCC > Vuvd(stb)(VCC) for t > t rec(uv))
NORMAL
(CANx BIAS
= VCC/2)
aaa-031274
Figure 5. TJR1448B state diagram (per channel)
7.1.1 Off mode
The TJR1448 switches to Off mode from any mode when the supply voltage (on pin
VIO in TJR1448A/C and VCC in TJR1448B) falls below the switch-off undervoltage
threshold (Vuvd(swoff)(VCC) or Vuvd(swoff)(VIO)). This is the default mode when the supply is
first connected.
In Off mode, the CAN pins and RXDx pins are in a high-ohmic state.
7.1.2 Standby mode
When the supply voltage (VIO for TJR1448A/C or VCC for TJR1448B) rises above the
switch-off undervoltage detection threshold, the TJR1448 starts to boot up, triggering an
initialization procedure. The TJR1448 switches to the selected mode after tstartup.
Standby mode is selected when pin STBx goes HIGH. In this mode, the transceiver
is unable to transmit or receive data and a low-power receiver is activated to monitor
the bus for a wake-up pattern. The transmitter and Normal-mode receiver blocks are
switched off and the bus pins are biased to ground to minimize system supply current.
Pin RXDx in the TJR1448A/B follows the bus after a wake-up request has been detected.
In the TJR1448C, RXDx is forced LOW when a wake-up request is detected.
A transition to Normal mode is triggered when STBx is forced LOW (provided VCC >
Vuvd(stb)(VCC) and VIO > Vuvd(swoff)(VIO) in the TJR1448A/C).
TJR1448
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Dual high-speed CAN transceiver with Standby mode
If VCC is below Vuvd(stb)(VCC) when STBx goes LOW (with VIO > Vuvd(swoff)(VIO) in
TJR1448A/C and VCC > Vuvd(swoff)(VCC) in TJR1448B), the TJR1448 will remain in
Standby mode. Pending wake-up events will be cleared and differential data on the bus
pins converted to digital data via the low-power receiver and output on pin RXDx.
In the TJR1448A/C, the low-power receiver is supplied from VIO and can detect CAN bus
activity when VIO is above Vuvd(swoff)(VIO) (even if VIO is the only available supply voltage).
7.1.3 Normal mode
A LOW level on pin STBx selects Normal mode, provided the supply voltage on pin VCC
is above the standby undervoltage detection threshold, Vuvd(stb)(VCC).
In this mode, the transceiver can transmit and receive data via bus lines CANHx and
CANLx. Pin TXDx must be HIGH at least once in Normal Mode before transmission can
begin. The differential receiver converts the analog data on the bus lines into digital data
on pin RXDx. The slopes of the output signals on the bus lines are controlled internally
and are optimized in a way that guarantees the lowest possible EME. In recessive state,
the output voltage on the bus pins is VCC/2.
7.1.4 Operating modes and gap-free operation
Gap-free operation guarantees defined behavior at all voltage levels. Supply voltage-tooperating mode mapping is detailed in Figure 6 and in the state diagrams (Figure 4 and
Figure 5).
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
TJR1448A/C
TJR1448B
Fully functional [2][3]
Fully functional [2] OR
Standby OR Off [4]
Standby OR Off [4]
-0.3 V - 2.65 V
-0.3 V - 4 V
Voltage range on VCC
Off
Fully functional [2] OR
Standby [4]
Standby
VIO operating range
(2.95 V - 5.5 V)
Vuvd(stb)(VCC) range [6]
Fully functional[2] AND
characteristics
guaranteed[5]
5.5 V - 6 V[1]
Fully functional [2][3]
VCC operating range
(4.5 V - 5.5 V)
Fully functional[2] AND
characteristics
guaranteed[5]
Vuvd(stb)(VCC) range
Fully functional[2] OR
Standby [4]
2.95 V - 4 V
Standby
Vuvd(swoff)(VCC) range
Standby OR Off [4]
-0.3 V - 2.65 V
Off
5.5 V - 6 V[1]
Fully functional [2][3] OR
Off [4]
VCC operating range
(4.5 V - 5.5 V)
Vuvd(swoff)(VIO) range [6]
Voltage range on VCC
5.5 V - 6 V[1]
Voltage range on VIO
[1] 6 V is the IEC 60134 Absolute Maximum Rating (AMR) for VCC and VIO (see Limiting values table). Above the AMR, irreversible changes in
characteristics, functionality or performance may occur. Returning from above AMR to the operating range, datasheet characteristics and
functionality cannot be guaranteed.
[2] Target transceiver functionality as described in this datasheet is applicable.
[3] Prolonged operation of the device outside the operating range may impact reliability over lifetime. Returning to the operating range, datasheet
characteristics are guaranteed provided the AMR has not been exceeded.
[4] For a given value of VCC (and VIO in TJR1448A/C), a specific device will be in a single defined state determined by its undervoltage detection
thresholds (Vuvd(stb)(VCC), Vuvd(swoff)(VIO) and Vuvd(swoff)(VCC)). The actual thresholds can vary between devices (within the ranges specified
in this data sheet). To guarantee the device will be in a specific state, VIO and VCC must be either above the maximum or below the
minimum thresholds specified for these undervoltage detection ranges.
[5] Datasheet characteristics are guaranteed within the VCC and VIO operating ranges. Exceptions are described in the Static and Dynamic
characteristics tables.
[6] The following applies to TJR1448A/C:
- If both VCC and VIO are above the undervoltage threshold, the device is fully functional.
- If VCC is below and VIO above the undervoltage threshold, the device is in Standby mode.
- If VIO is below the undervoltage threshold, the device is in Off mode, regardless of VCC.
aaa-039107
Figure 6. TJR1448 supply voltage ranges and gap-free operation
7.2 Remote wake-up (via the CAN bus)
In Standby mode, the TJR1448 wakes up when a dedicated wake-up pattern (specified in
ISO 11898-2: 2016) is detected on the bus.
The wake-up pattern consists of:
• a dominant phase of at least twake(busdom) followed by
• a recessive phase of at least twake(busrec) followed by
• a dominant phase of at least twake(busdom)
Dominant or recessive bits between the above mentioned phases that are shorter than
twake(busdom) and twake(busrec) respectively are ignored.
The complete dominant-recessive-dominant pattern must be received within tto(wake)bus to
be recognized as a valid wake-up pattern (see Figure 7 for TJR1448A/B wake-up timing
TJR1448
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
and Figure 8 for TJR1448C wake-up timing). Otherwise, the internal wake-up logic is
reset. The complete wake-up pattern then needs to be retransmitted to trigger a wake-up
event. Pin RXDx remains HIGH until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJR1448A/B remains in Standby
mode with the bus signals reflected on RXDx after tstartup(RXD). Note that dominant or
recessive phases lasting less than tfltr(wake)bus will not be detected by the low-power
differential receiver and will not be reflected on RXDx in Standby mode (see Figure 7).
The TJR1448C also remains in Standby mode after a wake-up sequence has been
detected, but pin RXDx switches LOW after tstartup(RXD) (see Figure 8).
A wake-up event is not flagged on RXDx if any of the following events occurs while a
valid wake-up pattern is being received:
• The device switches to Normal mode
• The complete wake-up pattern was not received within tto(wake)bus
• A VCC or VIO switch-off undervoltage is detected (VCC < Vuvd(swoff)(VCC) or VIO <
Vuvd(swoff)(VIO); see Section 7.3.3)
CANH
VO(dif)
CANL
twake(busrec)
tfltr(wake)bus tfltr(wake)bus
twake(busdom)
twake(busdom)
RXD
wake-up
pattern detected
tfltr(wake)bus tfltr(wake)bus
t < tfltr(wake)bus
t < tfltr(wake)bus
tfltr(wake)bus
tfltr(wake)bus
tstartup(RXD)(1)
t ≤ tto(wake)bus
aaa-031221
(1) During tstartup(RXD), the low-power receiver is on but pin RXDx is not active (i.e. HIGH/recessive). The first dominant
pulse of width ≥ tfltr(wake)bus that ends after tstartup(RXD) will trigger RXDx to go LOW/dominant.
Figure 7. TJR1448A/B wake-up timing
CANH
VO(dif)
CANL
twake(busdom)
twake(busrec)
twake(busdom)
wake-up
pattern detected
RXD
≤ tto(wake)bus
tstartup(RXD)
aaa-031220
Figure 8. TJR1448C wake-up timing
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7.3 Fail-safe features
7.3.1 TXD dominant timeout function
A hardware and/or software application failure in Normal mode that caused pin TXDx
to be held LOW would drive the bus lines to a permanent dominant state (blocking all
network communications). The TXD dominant time-out function prevents such a network
lock-up. A 'TXD dominant timeout' timer is started when pin TXDx goes LOW. If the LOW
state on this pin persists for longer than tto(dom)TXD, the transmitter is disabled, releasing
the bus lines to recessive state. The TXD dominant time-out timer is reset when pin
TXDx is set HIGH.
7.3.2 Internal biasing of TXDx and STBx input pins
Pins TXDx and STBx have internal pull-ups to VCC/VIO to ensure a safe, defined state in
case one, or both, of these pins is left or becomes floating. Pull-up resistors are active
on these pins in all states; they should be held at the VCC/VIO level in Standby mode to
minimize supply current.
7.3.3 Undervoltage detection on pins VCC and VIO
If VCC drops below the standby undervoltage detection threshold (Vuvd(stb)(VCC)) for tdet(uv),
both transceivers switch to Standby mode. The logic state of pin STBx is ignored until
VCC has recovered.
In the TJR1448A/C, if VIO drops below the switch-off undervoltage detection threshold
(Vuvd(swoff)(VIO)) for tuvd(swoff), both transceiver switch to Off mode and disengage from the
bus (high-ohmic) until VIO has recovered.
In the TJR1448B, if VCC drops below the switch-off undervoltage detection threshold
(Vuvd(swoff)(VCC)) for tuvd(swoff), both transceivers switch to Off mode and disengage from
the bus (high-ohmic) until VCC has recovered.
7.3.4 Overtemperature protection
The device is protected against overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature, Tj(sd), the CAN bus drivers are disabled.
When the junction temperature drops below Tj(sd)rel, the CAN bus drivers recover once
TXDx has been reset to HIGH and Normal mode is selected (waiting for TXDx to go
HIGH prevents output driver oscillation due to small variations in temperature).
7.3.5 I/O levels
Pin VIO on the TJR1448A/C should be connected to the same supply voltage used to
supply the microcontroller (see Figure 1). This adjusts the signal levels on pins TXDx,
RXDx and STBx to the I/O levels of the microcontroller, allowing for direct interfacing
without additional glue logic. Pin VIO also provides the internal supply voltage for the lowpower differential receiver. For applications running in low-power mode, this allows the
bus lines to be monitored for activity even if there is no supply voltage on pin VCC.
All I/O levels are related to VCC in the TJR1448B and are, therefore, compatible with 5 V
microcontrollers. Spurious signals from the microcontroller on pins STB1 and STB2 are
filtered out with a filter time of tfltr(IO).
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Dual high-speed CAN transceiver with Standby mode
8
Limiting values
Table 7. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to pin GND, unless
otherwise specified.
Symbol
Vx
Parameter
[1]
voltage on pin x
Conditions
Min
Max
Unit
pins VCC, VIO (TJR1448A), TXDx, STBx
-0.3
+6
V
pins CANHx, CANLx
[2]
-
+7
V
-36
+40
-0.3
VIO+0.3
V
pin RXDx
TJR1448A/C
TJR1448B
V
VCC+0.3
V
-40
+40
V
pulse 1
-100
-
V
pulse 2a
-
+75
V
pulse 3a
-150
-
V
-
+100
V
-8
+8
kV
voltage between pin
CANH and pin CANL
between pins CANH1 and CANL1 and between
CANH2 and CANL2
Vtrt
transient voltage
on pins CANHx, CANLx
[4]
pulse 3b
electrostatic discharge
voltage
[3]
-0.3
V(CANH-CANL)
VESD
[3]
IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)
[5]
on pins CANHx, CANLx
Human Body Model (HBM)
on any pin
[6]
-4
+4
kV
on pins CANHx, CANLx
[7]
-8
+8
kV
Charged Device Model (CDM)
[8]
-750
+750
V
on corner pins
on any other pin
Tvj
virtual junction
temperature
Tstg
storage temperature
-500
+500
V
[9]
-40
+175
°C
[10]
-55
+150
°C
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
[2] The device can withstand voltages between 6 V and 7 V for a total of 20 s over the product lifetime.
[3] Subject to the qualifications detailed in Table notes 1 and 2 above for pins VCC, VIO, TXDx and STBx.
[4] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.
[5] Verified by an external test house according to IEC TS 62228, Section 4.3.
[6] According to AEC-Q100-002.
[7] Pins stressed to reference group containing all ground and supply pins, emulating the application circuits (Figure 1 and Figure 2). HBM pulse as specified
in AEC-Q100-002 used.
[8] According to AEC-Q100-011.
[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value used in
the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
[10] Tstg in application according to IEC61360-4. For component transport and storage conditions, see instead IEC61760-2.
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9
Thermal characteristics
Table 8. Thermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from junction to ambient
[2]
[1]
Typ
Unit
SO14
62
K/W
HVSON14
42
K/W
Rth(j-c)
thermal resistance from junction to case
HVSON14
10
K/W
Ѱj-top
thermal characterization parameter from junction to top of package
SO14
8
K/W
HVSON14
4
K/W
[1]
[2]
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).
Case temperature refers to the center of the heatsink at the bottom of the package.
10 Static characteristics
Table 9. Static characteristics
Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1448A/C); RL = 60 Ω unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
4
-
4.5
V
50
-
-
mV
2.65
-
2.95
V
both channels recessive;
[3]
VTXDx = VIO
-
8
14
mA
one channel dominant; one channel
recessive; t < tto(dom)TXD
-
42
67
mA
both channels dominant;
VTXDx = 0 V; t < tto(dom)TXD
-
77
120
mA
both channels dominant;
VTXDx = 0 V;
short circuit on bus lines;
-3 V < (VCANHx = VCANLx) < +40 V
-
-
250
mA
TJR1448A,C; Tvj < 85 °C
-
-
2
μA
TJR1448B; Tvj < 85 °C
-
11
18
μA
2.95
-
5.5
V
Supply; pin VCC
VCC
supply voltage
[2]
Vuvd(stb)
standby undervoltage
detection voltage
Vuvhys(stb)
standby undervoltage
hysteresis voltage
Vuvd(swoff)
switch-off undervoltage
detection voltage
TJR1448B
ICC
supply current
Normal mode
[2]
Standby mode
I/O level adapter supply; pin VIO (TJR1448A/C)
VIO
supply voltage
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Table 9. Static characteristics...continued
Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1448A/C); RL = 60 Ω unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Vuvd(swoff)
switch-off undervoltage
detection voltage
IIO
supply current
Conditions
Min
Typ
Max
Unit
2.65
-
2.95
V
both channels recessive;
VTXDx = VIO
-
270
750
μA
one channel dominant; one channel
recessive
-
360
1000
μA
both channels dominant;
VTXDx = 0 V
-
450
1250
μA
-
11
16
μA
-
-
V
V
[2]
Normal mode
Standby mode; Tvj < 85 °C
CAN transmit data input; pins TXD1 and TXD2
VIH
[3]
HIGH-level input voltage
0.7VIO
VIL
LOW-level input voltage
-
-
[3]
0.3VIO
Vhys(TXD)
hysteresis voltage on pin
TXD
50
-
-
mV
Rpu
pull-up resistance
20
-
80
kΩ
-
-
10
pF
-10
-
-1
mA
1
-
10
mA
V
Ci
[4]
input capacitance
CAN receive data output; pins RXD1 and RXD2
[3]
IOH
HIGH-level output current
VRXDx = VIO
- 0.4 V
IOL
LOW-level output current
VRXDx = 0.4 V; bus dominant
Standby control input; pins STB1 and STB2
[3]
VIH
HIGH-level input voltage
0.7VIO
-
-
VIL
LOW-level input voltage
-
-
0.3VIO
V
Vhys
hysteresis voltage
50
-
-
mV
Rpu
pull-up resistance
20
-
80
kΩ
-
-
10
pF
2.75
3.5
4.5
V
0.5
1.5
2.25
V
0.9VCC
-
1.1VCC
V
-150
-
+150
mV
Ci
[4]
input capacitance
[3]
Bus lines; pins CANH1, CANH2, CANL1 and CANL2
VO(dom)
VTXD = 0 V; t < tto(dom)TXD;
VCC ≥ 4.75 V; RL = 50 Ω to 65 Ω
dominant output voltage
pin CANHx
pin CANLx
VTXsym
transmitter voltage
symmetry
VTXsym = VCANHx + VCANLx;
CSPLIT = 4.7 nF;
fTXD = 250 kHz, 1 MHz or 2.5 MHz
Vcm(step)
common mode voltage step
[4]
[5]
[4]
[5]
[6]
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Table 9. Static characteristics...continued
Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1448A/C); RL = 60 Ω unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Vcm(p-p)
VO(dif)
Parameter
Conditions
Min
Typ
Max
Unit
-300
-
+300
mV
RL = 50 Ω to 65 Ω
1.5
-
3
V
RL = 45 Ω to 70 Ω
1.4
-
3.3
V
1.5
-
5
V
Normal mode; VTXDx = VIO
-50
-
+50
mV
Standby mode
-0.2
-
+0.2
V
2
2.5
3
V
-0.1
-
+0.1
V
Normal mode
0.5
-
0.9
V
Standby mode
0.4
-
1.1
V
Normal mode
-4
-
+0.5
V
Standby mode
-4
-
+0.4
V
Normal mode
0.9
-
9
V
Standby mode
1.1
-
9
V
[4]
peak-to-peak common mode
voltage
[5]
[6]
dominant; Normal mode; VTXDx = 0 V;
t < tto(dom)TXD; VCC ≥ 4.75 V
differential output voltage
[4]
RL = 2240 Ω
recessive; no load
[3]
VO(rec)
Normal mode; VTXDx =
recessive output voltage
[3]
VIO ;
no load
Standby mode; no load
Vth(RX)dif
Vrec(RX)
Vdom(RX)
-12 V ≤ VCANHx ≤ +12 V;
-12 V ≤ VCAxNL ≤ +12 V
differential receiver
threshold voltage
-12 V ≤ VCANHx ≤ +12 V;
-12 V ≤ VCANLx ≤ +12 V
receiver recessive voltage
-12 V ≤ VCANHx ≤ +12 V;
-12 V ≤ VCANLx ≤ +12 V
receiver dominant voltage
Vhys(RX)dif
differential receiver
hysteresis voltage
-12 V ≤ VCANHx ≤ +12 V;
-12 V ≤ VCANLx ≤ +12 V; Normal mode
50
-
-
mV
IO(sc)
short-circuit output current
-15 V ≤ VCANHx ≤ +40 V;
-15 V ≤ VCANLx ≤ +40 V
-
-
115
mA
IO(sc)rec
recessive short-circuit output -27 V ≤ VCANHx ≤ +32 V;
current
-27 V ≤ VCANLx ≤ +32 V; Normal mode;
[3]
VTXD = VIO
-3
-
+3
mA
IL
leakage current
VCC = VIO = 0 V or pins shorted to GND
via 47 KΩ; VCANHx = VCANLx = 5 V
-10
-
+10
µA
Ri
input resistance
-2 V ≤ VCANLx ≤ +7 V;
-2 V ≤ VCANHx ≤ +7 V
25
40
50
kΩ
ΔRi
input resistance deviation
0 V ≤ VCANLx ≤ +5 V;
0 V ≤ VCANHx ≤ +5 V
-3
-
+3
%
Ri(dif)
differential input resistance
-2 V ≤ VCANL ≤ +7 V;
-2 V ≤ VCANH ≤ +7 V
50
80
100
kΩ
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Table 9. Static characteristics...continued
Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1448A/C); RL = 60 Ω unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
20
pF
Ci(cm)
common-mode input
capacitance
[4]
Ci(dif)
differential input capacitance
[4]
-
-
10
pF
Temperature detection
Tj(sd)
shutdown junction
temperature
[4]
180
-
200
°C
Tj(sd)rel
release shutdown junction
temperature
[4]
175
-
195
°C
[1]
[2]
[3]
[4]
[5]
[6]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected
above max value.
VCC in TJR1448B
Not tested in production; guaranteed by design.
The test circuit used to measure the bus output voltage symmetry and the common-mode voltages (which includes CSPLIT) is shown in Figure 15.
See Figure 11
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11 Dynamic characteristics
Table 10. Dynamic characteristics
Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1448A/C); RL = 60 Ω unless specified otherwise; all
[1]
voltages are defined with respect to ground.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CAN timing characteristics; tbit(TXD) ≥ 200 ns; see Figure 9, Figure 10 and Figure 14
td(TXD-busdom)
delay time from TXD to bus dominant
Normal mode
-
-
102.5 ns
td(TXD-busrec)
delay time from TXD to bus recessive
Normal mode
-
-
102.5 ns
td(busdom-RXD) delay time from bus dominant to RXD
Normal mode
-
-
127.5 ns
td(busrec-RXD)
delay time from bus recessive to RXD
Normal mode
-
-
127.5 ns
td(TXDL-RXDL)
delay time from TXD LOW to RXD LOW
Normal mode
-
-
230
ns
td(TXDH-RXDH)
delay time from TXD HIGH to RXD HIGH
Normal mode
-
-
230
ns
tbit(TXD) = 500 ns
435
-
530
ns
tbit(TXD) = 200 ns
155
-
210
ns
tbit(TXD) = 500 ns
-65
-
+40
ns
tbit(TXD) = 200 ns
-45
-
+15
ns
tbit(TXD) = 500 ns
400
-
550
ns
tbit(TXD) = 200 ns
120
-
220
ns
0.8
-
9
ms
0.5
-
1.8
µs
0.5
-
1.8
µs
0.8
-
9
ms
CAN FD timing characteristics according to ISO 11898-2:2016; see Figure 10 and Figure 14
tbit(bus)
Δtrec
tbit(RXD)
transmitted recessive bit width
receiver timing symmetry
bit time on pin RXD
Dominant time-out time; pins TXD1 and TXD2
tto(dom)TXD
TXD dominant time-out time
VTXD = 0 V; Normal mode
[2]
[3]
Bus wake-up times; pins CANH1, CANH2 and CANL1, CANL2; see Figure 7 and Figure 8
twake(busdom)
bus dominant wake-up time
Standby mode
[2]
twake(busrec)
bus recessive wake-up time
Standby mode
[2]
tto(wake)bus
bus wake-up time-out time
Standby mode
[2]
tfltr(wake)bus
bus wake-up filter time
TJR1448A/B; Standby mode
[2]
-
-
1.8
µs
mode change transition time
[2]
-
-
50
µs
start-up time
[2]
-
-
1
ms
RXD start-up time
[2]
4
-
20
µs
[6]
1
-
5
µs
on pin VCC
[2]
-
-
30
µs
on pin VCC; TJR1448B
[2]
-
-
30
µs
[4]
[4]
[3]
Mode transitions
tt(moch)
tstartup
tstartup(RXD)
after wake-up detected
[5]
IO filter; pins STB1 and STB2
tfltr(IO)
IO filter time
Undervoltage detection; see Figure 4 and Figure 5
tdet(uv)
tuvd(swoff)
undervoltage detection time
switch-off undervoltage detection time
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Table 10. Dynamic characteristics...continued
Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJR1448A/C); RL = 60 Ω unless specified otherwise; all
[1]
voltages are defined with respect to ground.
Symbol
trec(uv)
[1]
[2]
[3]
[4]
[5]
[6]
Parameter
Conditions
undervoltage recovery time
Min
on pin VIO; TJR1448A/C
[2]
on pin VCC
[2]
-
Typ
-
Max
Unit
30
µs
50
µs
All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
Not tested in production; guaranteed by design.
Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the
max value.
A dominant/recessive phase shorter than the min value is guaranteed not be seen as a dominant/recessive bit; a dominant/recessive phase longer than
the max value is guaranteed to be seen as a dominant/recessive bit.
When a wake-up is detected, RXD start-up time is between the min and max values. RXD cannot be relied on below the min value; RXD can be relied on
above the max value; see Figure 7 and Figure 8.
Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed.
TXD
HIGH
70 %
30 %
LOW
CANH
CANL
dominant
0.9 V
VO(dif)
0.5 V
recessive
RXD
70 %
30 %
HIGH
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
aaa-029311
Figure 9. CAN transceiver timing diagram
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70 %
TXD
30 %
30 %
td(TXDL-RXDL)
5 x tbit(TXD)
tbit(TXD)
0.9 V
VO(dif)
0.5 V
tbit(bus)
70 %
RXD
30 %
td(TXDH-RXDH)
tbit(RXD)
aaa-029312
Figure 10. CAN FD timing definitions according to ISO 11898-2:2016
CANH
CANL
Vcm(step)
VCANH + VCANL
Vcm(p-p)
aaa-037830
Figure 11. CAN bus common-mode voltage
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12 Application information
12.1 Application diagrams
3.3 V
BAT
(1)
on/off control
5V
(1)
VCC
3
VIO
11
CANH1 13
Pxx
14
8
1
4
CANL1 12
CANH2 10
6
7
2
5
STB1
STB2
TXD1
RXD1
TXD2
RXD2
VDD
Pyy
Pzz
TX0
MICROCONTROLLER
RX0
TX1
RX1
GND
GND
GND
CANL2 9
aaa-038145
(1) Optional, depends on regulator.
Figure 12. Typical TJR1448A/C application with a 3.3 V microcontroller
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5V
BAT
(1)
VCC
3
CANH1
13
14
11
1
CANL1
CANH2
4
12
10
5
8
2
6
CANL2
STB1
STB2
TXD1
RXD1
TXD2
RXD2
Pxx
VDD
Pyy
TX0
RX0
MICROCONTROLLER
TX1
RX1
GND
GND
GND
9
aaa-038146
(1) Optional, depends on regulator.
Figure 13. Typical TJR1448B application with a 5 V microcontroller
12.2 Application hints
Further information on the application of the TJR1448 can be found in NXP application
hints AH2002 'TJx144x/TJx146x Application Hints', available on request from NXP
Semiconductors.
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13 Test information
TXD
CANH
RL
60 Ω
RXD
CL
100 pF
CANL
15 pF
aaa-030850
Figure 14. CAN transceiver timing test circuit
TXD
CANH
30 Ω
fTXD
CSPLIT
4.7 nF
RXD
30 Ω
CANL
aaa-030851
Figure 15. Test circuit for measuring transceiver driver symmetry
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
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14 Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
A2
Q
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Figure 16. Package outline SOT108-1 (SO14)
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HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
B
D
A
E
A
A1
c
terminal 1
index area
detail X
e1
terminal 1
index area
e
v
w
b
1
7
C
C A B
C
y1 C
y
L
k
Eh
14
8
Dh
0
2.5
scale
Dimensions
Unit
mm
5 mm
A
A1
b
max 1.00 0.05 0.35
nom 0.85 0.03 0.32
min 0.80 0.00 0.29
c
D
Dh
E
0.2
4.6
4.5
4.4
4.25
4.20
4.15
3.1
3.0
2.9
Eh
e
e1
1.65
1.60 0.65
1.55
3.9
k
L
0.35 0.45
0.30 0.40
0.25 0.35
v
0.1
w
y
0.05 0.05
y1
0.1
sot1086-2
References
Outline
version
IEC
JEDEC
JEITA
SOT1086-2
---
MO-229
---
European
projection
Issue date
10-07-14
10-07-15
Figure 17. Package outline SOT1086-2 (HVSON14)
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15 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 11 and Table 12
Table 11. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 12. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
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Dual high-speed CAN transceiver with Standby mode
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
17 Soldering of HVSON packages
Section 16 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can be found in the following application note:
• AN10365 “Surface mount reflow soldering description”
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18 Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 13. ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)
short-circuit output current
Absolute current on CAN_L
ICAN_L
HS-PMA dominant output characteristics
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
Differential output voltage
VO(rec)
recessive output voltage
VDiff
VO(dif)
differential output voltage
tdom
tto(dom)TXD
TXD dominant time-out time
Optional HS-PMA transmit dominant time-out
Transmit dominant time-out, long
Transmit dominant time-out, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
Dominant state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
ΔRi
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to
RXD LOW
HS-PMA implementation loop delay requirement
Loop delay
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Table 13. ISO 11898-2:2016 to NXP data sheet parameter conversion...continued
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2
Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
ΔtRec
Δtrec
receiver timing symmetry
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
General maximum rating VCAN_H and VCAN_L
VCAN_H
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
tFilter
twake(busdom)
twake(busrec)
bus dominant wake-up time
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
HS-PMA bus biasing control timings
CAN activity filter time, long
CAN activity filter time, short
Wake-up time-out, short
[1]
Wake-up time-out, long
[1]
tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
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19 Appendix: TJx144x/TJx146x/TJF1441 family overview
Table 14. Feature overview of the complete TJx144x/TJx146x/TJF1441 family
Data rate
Additional features
TXD dominant timeout
[6]
Single supply pin wake-up
Short WUP support [0.5 - 1.8 µs]
[4]
Wake-up source recognition
Signal improvement
[3]
[2]
Up to 8 Mbit/s CAN FD
Up to 5 Mbit/s CAN FD
VBAT pin
VIO pin
●
●
●
●
●
●
●
●
●
●
TJx1441D
●
●
●
●
●
TJF1441A
●
●
[7]
TJx1442A
●
●
TJx1442B
●
●
TJx1443A
●
●
TJx1448A
●
TJx1448B
[1]
Sleep
VCC pin
Selectable Off
Silent/Listen-only
Standby
●
TJx1441B
Normal
TJx1441A
Device
●
●
●
●
●
●
●
●
●
●
●
●
●
●
TJx1448C
●
●
●
●
●
TJx1462A
●
●
●
●
●
●
TJx1462B
●
●
●
●
●
TJx1463A
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
[1]
[2]
[3]
[4]
[5]
[6]
[7]
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Local diagnostics via ERR_N pin
Supplies
[5]
Modes
●
●
●
●
●
TJx: TJA14xxx is AEC-Q100 Grade 1; TJR14xxx is AEC-Q100 Grade 0; TJF1441A is non-automotive grade.
Only guaranteed for TJA146x, AEC-Q100 Grade 1.
CAN FD Signal Improvement Capability (SIC) according to CiA 601-4:2019.
RXD is held LOW after wake-up request, enabling wake-up source recognition.
WUP = wake-up pattern according ISO11898-2:2016.
Only VIO supply needed for wake-up in TJA1442A, TJA1448A, TJA1448C, TJA1462A; only VBAT supply needed for wake-up in TJA1443A, TJA1463A.
Not having TXD dominant timeout allows for very low data rates in non-automotive grade applications.
20 Revision history
Table 15. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJR1448 v.2
20211015
Product data sheet
-
TJR1448 v.1
Modifications
•
•
•
•
TJR1448 v.1
20200907
TJR1448
Product data sheet
Added device (Table 3) and family (Section 19) feature overviews
Table 7: table note 10 added
Section 11: measurement conditions for parameter tstartup(RXD) revised
Section 21: Suitability for use in Automotive applications and Security disclaimers revised
Product data sheet
-
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-
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21 Legal information
21.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
21.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
TJR1448
Product data sheet
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP product has
been qualified for use in automotive applications. If this product is used
by customer in the development of, or for incorporation into, products or
services (a) used in safety critical applications or (b) in which failure could
lead to death, personal injury, or severe physical or environmental damage
(such products and services hereinafter referred to as “Critical Applications”),
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TJR1448
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Dual high-speed CAN transceiver with Standby mode
then customer makes the ultimate design decisions regarding its products
and is solely responsible for compliance with all legal, regulatory, safety,
and security related requirements concerning its products, regardless of
any information or support that may be provided by NXP. As such, customer
assumes all risk related to use of any products in Critical Applications and
NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any
claims, liabilities, damages and associated costs and expenses (including
attorneys’ fees) that NXP may incur related to customer’s incorporation of
any product in a Critical Application.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
for the design and operation of its applications and products throughout
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
21.4 Trademarks
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
TJR1448
Product data sheet
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 October 2021
© NXP B.V. 2021. All rights reserved.
37 / 38
TJR1448
NXP Semiconductors
Dual high-speed CAN transceiver with Standby mode
Contents
1
1.1
2
2.1
2.2
2.3
2.4
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
8
9
10
11
12
12.1
12.2
13
13.1
14
15
16
16.1
16.2
16.3
16.4
17
18
19
20
21
General description ............................................ 1
TJR1448 variants .............................................. 1
Features and benefits .........................................1
General .............................................................. 1
Predictable and fail-safe behavior ..................... 2
Low-power management ................................... 2
Protection ...........................................................2
Quick reference data .......................................... 3
Ordering information .......................................... 4
Block diagrams ................................................... 5
Pinning information ............................................ 7
Pinning ............................................................... 7
Pin description ................................................... 8
Functional description ......................................10
Operating modes ............................................. 10
Off mode ..........................................................12
Standby mode ................................................. 12
Normal mode ................................................... 13
Operating modes and gap-free operation ........ 13
Remote wake-up (via the CAN bus) ................ 14
Fail-safe features ............................................. 16
TXD dominant timeout function ....................... 16
Internal biasing of TXDx and STBx input
pins .................................................................. 16
Undervoltage detection on pins VCC and
VIO ...................................................................16
Overtemperature protection ............................. 16
I/O levels ..........................................................16
Limiting values .................................................. 17
Thermal characteristics ....................................18
Static characteristics ........................................ 18
Dynamic characteristics ...................................22
Application information .................................... 25
Application diagrams ....................................... 25
Application hints .............................................. 26
Test information ................................................ 27
Quality information ...........................................27
Package outline .................................................28
Handling information ........................................ 30
Soldering of SMD packages .............................30
Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
Soldering of HVSON packages ........................ 32
Appendix: ISO 11898-2:2016 parameter
cross-reference list ........................................... 33
Appendix: TJx144x/TJx146x/TJF1441
family overview ................................................. 35
Revision history ................................................ 35
Legal information .............................................. 36
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 October 2021
Document identifier: TJR1448
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