TJF1441
High-speed CAN transceiver
Rev. 2 — 15 October 2021
1
Product data sheet
General description
The TJF1441 is a member of the TJA144x family of transceivers that provide an interface
between a Controller Area Network (CAN) or CAN FD (Flexible Data rate) protocol
controller and the physical two-wire CAN bus. TJA144x transceivers implement the CAN
physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5, and
are fully interoperable with high-speed Classical CAN and CAN FD transceivers. All
TJA144x variants enable reliable communication in the CAN FD fast phase at data rates
up to 5 Mbit/s.
The TJF1441 is designed for CAN industrial applications allowing networks to run at
very low bit rates up to 5 Mbit/s CAN-FD. A VIO supply input allows for direct interfacing
with 3.3 V and 5 V-supplied microcontrollers. It is intended as a replacement for highspeed Classical CAN and CAN FD transceivers, such as the TJF1051 from NXP. It offers
pin compatibility and is designed to avoid changes to hardware and software design,
allowing the TJF1441 to be easily retrofitted to existing applications.
A variant intended for high-speed CAN applications in the automotive industry, the
TJA1441, is also available.
2
Features and benefits
2.1 General
•
•
•
•
•
•
•
•
ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant
Standard CAN and CAN FD data bit rates up to 5 Mbit/s
Optimized for industrial applications
Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI)
Silent mode for node diagnosis and failure containment
VIO input for interfacing with 3.3 V to 5 V microcontrollers
Available in SO8 package
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.2 Predictable and fail-safe behavior
• Undervoltage detection with defined handling on all supply pins
• Full functionality guaranteed from the undervoltage detection thresholds up to the
maximum limiting voltage values
• Defined behavior below the undervoltage detection thresholds
• Transceiver disengages from the bus (high-ohmic) when the supply voltage drops
below the Off mode threshold
• Internal biasing of TXD and mode selection input pin, to enable defined fail-safe
behavior
TJF1441
NXP Semiconductors
High-speed CAN transceiver
2.3 Protection
• High ESD handling capability on the bus pins (8 kV IEC and HBM)
• Thermally protected
3
Quick reference data
Table 1. Quick reference data
Symbol
Parameter
VCC
supply voltage
ICC
supply current
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
Normal mode, dominant
-
38
60
mA
Normal mode, recessive
-
4
7
mA
Silent mode
-
3
6
mA
Vuvd(VCC)
undervoltage detection voltage
on pin VCC
4
-
4.5
V
Vuvhys(VCC)
undervoltage hysteresis voltage
on pin VCC
50
-
-
mV
VIO
supply voltage on pin VIO
2.95
-
5.5
V
IIO
supply current on pin VIO
Normal mode, dominant; VTXD = 0 V
-
250
760
µA
Normal mode, recessive; VTXD = VIO
-
150
460
µA
Silent mode; VTXD = VIO
-
70
200
µA
2.65
-
2.95
V
Vuvd(swoff)(VIO)
switch-off undervoltage detection
voltage on pin VIO
VESD
electrostatic discharge voltage
IEC 61000-4-2 on pins CANH and CANL -8
-
+8
kV
VCANH
voltage on pin CANH
limiting value according to IEC 60134
-36
-
+40
V
VCANL
voltage on pin CANL
limiting value according to IEC 60134
-36
-
+40
V
Tvj
virtual junction temperature
-40
-
+150
°C
4
Ordering information
Table 2. Ordering information
Type number
TJF1441AT
TJF1441
Product data sheet
Package
Name
Description
Version
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
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High-speed CAN transceiver
Table 3. TJF1441 feature overview
See Section 18 for a feature overview of the complete TJx144x/TJx146x/TJF1441 family.
Data rate
Additional features
●
TXD dominant timeout
Single supply pin wake-up
Short WUP support [0.5 - 1.8 µs]
Wake-up source recognition
[2]
Signal improvement
Up to 8 Mbit/s CAN FD
●
Up to 5 Mbit/s CAN FD
●
VBAT pin
VIO pin
●
Selectable Off
Silent/Listen-only
Sleep
[3]
[1]
[2]
[3]
[4]
[5]
●
VCC pin
TJF1441A
Standby
[1]
Normal
Device
Local diagnostics via ERR_N pin
Supplies
[4]
Modes
[5]
TJF1441 is AEC-Q100 Grade 1.
CAN FD Signal Improvement Capability (SIC) according to CiA 601-4:2019.
RXD is held LOW after wake-up request, enabling wake-up source recognition.
WUP = wake-up pattern according ISO11898-2:2016.
Not having TXD dominant timeout allows for very low data rates in non-automotive grade applications.
TJF1441
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High-speed CAN transceiver
5
Block diagram
VIO
VIO
VCC
5
3
TJF1441
TEMPERATURE
PROTECTION
7
CANH
TRANSMITTER
TXD
1
6
CANL
VIO
S
MODE
CONTROL
8
VIO
RXD
differential
receiver
MUX
AND
DRIVER
4
2
GND
aaa-030976
Figure 1. Block diagram
TJF1441
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6
Pinning information
6.1 Pinning
TXD
1
8
S
GND
2
7
CANH
VCC
3
6
CANL
RXD
4
5
VIO
aaa-030469
Figure 2. Pin configuration diagram
6.2 Pin description
Table 4. Pin description
[1]
Symbol
Pin
Type
TXD
1
I
transmit data input; inputs data (from the CAN controller) to be written to the bus lines
GND
2
G
ground
VCC
3
P
5 V supply voltage input
RXD
4
O
receive data output; outputs data read from the bus lines (to the CAN controller).
VIO
5
P
supply voltage for I/O level adapter
CANL
6
AIO
LOW-level CAN bus line
CANH
7
AIO
HIGH-level CAN bus line
S
8
I
Silent mode control input
[1]
Description
I: digital input; O: digital output; AIO: analog input/output; P: power supply; G: ground.
TJF1441
Product data sheet
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High-speed CAN transceiver
7
Functional description
7.1 Operating modes
The TJF1441 supports three operating modes, Normal, Silent, and Off. The operating
mode is selected via pin S. See Table 5 for a description of the operating modes under
normal supply conditions. Mode changes are completed after transition time tt(moch).
Table 5. Operating modes
Mode
Inputs
Normal
Outputs
Pin S
Pin TXD
CAN driver
Pin RXD
LOW
LOW
dominant
LOW
HIGH
recessive
LOW when bus dominant
HIGH when bus recessive
Silent
HIGH
X
LOW when bus dominant
biased to VCC/2
HIGH when bus recessive
Off
[1]
[1]
X
X
high-ohmic state
high-ohmic state
Off mode is only entered when the voltage on pin VCC is below Vuvd(VCC) or the voltage on pin VIO is below Vuvd(swoff)VIO
(see Figure 3 ).
from any mode when
VIO < Vuvd(swoff)(VIO) for t > tuvd(swoff)
OFF
(CAN BIAS
= highohmic)
S = LOW
AND VCC > Vuvd(VCC) for t > t rec(uv)
AND VIO > Vuvd(swoff)(VIO) for t > t startup
VCC < Vuvd(VCC) for t > tdet(uv)
VCC < Vuvd(VCC) for t > t det(uv)
S = HIGH
AND VCC > Vuvd(VCC) for t > t rec(uv)
AND VIO > Vuvd(swoff)(VIO) for t > t startup
SILENT
(CAN BIAS
= VCC/2)
S = LOW AND
NOT(VCC < Vuvd(VCC) for t > t det(uv))
S = HIGH AND
NOT(VCC < Vuvd(VCC) for t > tdet(uv))
NORMAL
(CAN BIAS
= VCC/2)
aaa-031270
Figure 3. TJF1441 state diagram
TJF1441
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7.1.1 Off mode
The TJF1441 switches to Off mode from any mode when the supply voltage on pin VIO
falls below the switch-off undervoltage detection threshold (Vuvd(swoff)(VIO)) or when VCC
drops below Vuvd(VCC). This is the default mode when the supply is first connected.
The CAN pins and pin RXD are in a high-ohmic state in Off mode.
When the supply voltage rises above the switch-off undervoltage detection threshold,
the TJF1441 starts to boot up, triggering an initialization procedure. It switches to the
selected mode after tstartup, provided VCC > Vuvd(VCC).
7.1.2 Silent mode
A HIGH level on pin S selects Silent mode. The transmitter is disabled in Silent mode,
releasing the bus pins to VCC/2. All other IC functions, including the receiver, continue to
operate as in Normal mode. Silent mode can be used to prevent a faulty CAN controller
disrupting network communications.
7.1.3 Normal mode
A LOW level on pin S selects Normal mode. In Normal mode, the transceiver can
transmit and receive data via bus lines CANH and CANL. Pin TXD must be HIGH at
least once in Normal mode before transmission can begin. The differential receiver
converts the analog data on the bus lines into digital data on pin RXD. The slopes of the
output signals on the bus lines are controlled internally and are optimized in a way that
guarantees the lowest possible EME. In recessive state, the output voltage on the bus
pins is VCC/2.
TJF1441
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TJF1441
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High-speed CAN transceiver
7.1.4 Operating modes and gap-free operation
Gap-free operation guarantees defined behavior at all voltage levels. Supply voltage-tooperating mode mapping is detailed in Figure 4 and in the state diagram (Figure 3).
Fully functional [2][3]
Off
Fully functional [2] OR
Off [4]
Fully functional[2] OR
Off [4]
Off [4]
Off
-0.3 V - 2.65 V
-0.3 V - 4 V
VIO operating range
(2.95 V - 5.5 V)
Vuvd(VCC) range[6]
Fully functional [2] and
characteristics
guaranteed[5]
5.5 V - 6 V[1]
Fully functional[2][3] OR
Off [4]
VCC operating range
(4.5 V - 5.5 V)
Vuvd(swoff)(VIO) range [6]
Voltage range on VCC
5.5 V - 6 V[1]
Voltage range on VIO
[1] 6 V is the IEC 60134 Absolute Maximum Rating (AMR) for VCC and VIO (see Limiting values table). Above the AMR, irreversible changes in
characteristics, functionality or performance may occur. Returning from above AMR to the operating range, datasheet characteristics and
functionality cannot be guaranteed.
[2] Target transceiver functionality as described in this datasheet is applicable.
[3] Prolonged operation of the device outside the operating range may impact reliability over lifetime. Returning to the operating range, datasheet
characteristics are guaranteed provided the AMR has not been exceeded.
[4] For a given value of VCC or VIO, a specific device will be in a single defined state determined by its undervoltage detection thresholds
(Vuvd(VCC) and Vuvd(swoff)(VIO)). The actual thresholds can vary between devices (within the ranges specified in this data sheet). To guarantee
the device will be in a specific state, VIO and VCC must be either above the maximum or below the minimum thresholds specified for these
undervoltage detection ranges.
[5] Datasheet characteristics are guaranteed within the VCC and VIO operating ranges. Exceptions are described in the Static and Dynamic
characteristics tables.
[6] The device is fully functional when both VCC and VIO are above the undervoltage threshold.
If VCC or VIO falls below any undervoltage threshold, the device switches to Off mode.
aaa-038711
Figure 4. Supply voltage ranges and gap-free operation
7.2 Fail-safe features
7.2.1 Internal biasing of TXD and S input pins
Pins TXD and S have internal pull-ups to VIO to ensure a safe, defined state in case one
or more of these pins is left open or become floating. Pull-up resistors are active on these
pins in all states; they should be held at the VIO level in Silent mode to minimize supply
current.
TJF1441
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TJF1441
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High-speed CAN transceiver
7.2.2 Undervoltage detection on pins VCC and VIO
If VCC or VIO drops below the undervoltage detection threshold (Vuvd(VCC) or Vuvd(swoff)VIO)
the transceiver switches to Off mode and disengages from the bus (zero load; bus pins
high-ohmic) until the supply voltage has recovered. If Normal mode is selected, the
output drivers are enabled once both VCC and VIO are again within their operating ranges
and TXD has been reset to HIGH.
7.2.3 Overtemperature protection
The device is protected against overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature, Tj(sd), the CAN bus drivers are disabled.
When the junction temperature drops below Tj(sd)rel, the CAN bus drivers recover once
TXD has been reset to HIGH and Normal mode is selected (waiting for TXD to go HIGH
prevents output driver oscillation due to small variations in temperature).
7.2.4 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage (see Figure 8). This
adjusts the signal levels on pins TXD, RXD and S to the I/O levels of the microcontroller,
allowing for direct interfacing without additional glue logic. Spurious signals from the
microcontroller on pin S are filtered out with a filter time of tfltr(IO).
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8
Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to pin GND, unless
otherwise specified.
Symbol
Vx
Parameter
[1]
voltage on pin x
Conditions
Min
Max
Unit
on pins VCC, VIO, TXD, S
-0.3
+6
V
on pins CANH, CANL
on pins RXD
transient voltage
electrostatic discharge
voltage
+7
-36
+40
V
[3]
VIO+0.3
-40
+40
V
pulse 1
-100
-
V
pulse 2a
-
+75
V
pulse 3a
-150
-
V
-
+100
V
-8
+8
kV
on pins CANH, CANL
[4]
pulse 3b
VESD
-0.3
V(CANH-CANL) voltage between pin CANH
and pin CANL
Vtrt
[2]
IEC 61000-4-2 (150 pF, 330 Ω discharge circuit)
[5]
on pins CANH, CANL
Human Body Model (HBM)
on any pin
[6]
-4
+4
kV
on pins CANH, CANL
[7]
-8
+8
kV
-750
+750
V
Charged Device Model (CDM)
[8]
on corner pins
on any other pin
Tvj
Tstg
virtual junction temperature
storage temperature
-500
+500
V
[9]
-40
+150
°C
[10]
-55
+150
°C
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these
values.
[2] The device can withstand voltages between 6 V and 7 V for a total of 20 s over the product lifetime.
[3] Subject to the qualifications detailed in Table notes 1 and 2 above for pins VCC, VIO, TXD, and S.
[4] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637.
[5] Verified by an external test house according to IEC TS 62228, Section 4.3.
[6] According to AEC-Q100-002.
[7] Pins stressed to reference group containing all ground and supply pins, emulating the application circuit (Figure 8). HBM pulse as specified in AECQ100-002 used.
[8] According to AEC-Q100-011.
[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P # Rth(j-a), where Rth(j-a) is a fixed value used in
the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).
[10] Tstg in application according to IEC61360-4. For component transport and storage conditions, see instead IEC61760-2.
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9
Thermal characteristics
Table 7. Thermal characteristics
Value determined for free convection conditions on a JEDEC 2S2P board.
Symbol
Parameter
Rth(j-a)
Ѱj-top
[1]
Conditions
[1]
Typ
Unit
thermal resistance from junction to ambient
96
K/W
thermal characterization parameter from junction to top of package
9
K/W
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm)
and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm).
10 Static characteristics
Table 8. Static characteristics
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJF1441A); RL = 60 Ω; unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
4.5
-
5.5
V
4
-
4.5
V
50
-
-
mV
dominant; VTXD = 0 V
-
38
60
mA
dominant; VTXD = 0 V;
short circuit on bus lines;
-3 V < (VCANH = VCANL) < +40 V
-
-
125
mA
recessive; VTXD = VIO
-
4
7
mA
-
3
6
mA
2.95
-
5.5
V
2.65
-
2.95
V
Normal mode; dominant; VTXD = 0 V
-
250
760
µA
Normal mode; recessive; VTXD = VIO
-
150
460
µA
Silent mode; VTXD = VIO
-
70
200
µA
Supply; pin VCC
VCC
supply voltage
Vuvd
undervoltage detection
voltage
Vuvhys
undervoltage hysteresis
voltage
ICC
supply current
[2]
Normal mode
Silent mode; VTXD = VIO
I/O level adapter supply; pin VIO
VIO
supply voltage
Vuvd(swoff)
switch-off undervoltage
detection voltage
IIO
supply current
[2]
CAN transmit data input; pin TXD
VIH
HIGH-level input voltage
0.7VIO
-
-
V
VIL
LOW-level input voltage
-
-
0.3VIO
V
Vhys(TXD)
hysteresis voltage on pin
TXD
50
-
-
mV
Rpu
pull-up resistance
20
-
80
kΩ
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Table 8. Static characteristics...continued
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJF1441A); RL = 60 Ω; unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Ci
Parameter
Conditions
[3]
input capacitance
Min
Typ
Max
Unit
-
-
10
pF
CAN receive data output; pin RXD
IOH
HIGH-level output current
VRXD = VIO - 0.4 V
-10
-
-1
mA
IOL
LOW-level output current
VRXD = 0.4 V
+1
-
+10
mA
Silent control inputs; pins S
VIH
HIGH-level input voltage
0.7VIO
-
-
V
VIL
LOW-level input voltage
-
-
0.3VIO
V
Vhys
hysteresis voltage
50
-
-
mV
Rpu
pull-up resistance
20
-
80
kΩ
-
-
10
pF
2.75
3.5
4.5
V
0.5
1.5
2.25
V
0.9VCC
-
1.1VCC
V
-150
-
+150
mV
-300
-
+300
mV
RL = 50 Ω to 65 Ω
1.5
-
3
V
RL = 45 Ω to 70 Ω
1.4
-
3.3
V
1.5
-
5
V
-50
-
+50
mV
Ci
[3]
input capacitance
Bus lines; pins CANH and CANL
VO(dom)
VTXD = 0 V; VCC ≥ 4.75 V
dominant output voltage
pin CANH; RL = 50 Ω to 65 Ω
pin CANL; RL = 50 Ω to 65 Ω
VTXsym
transmitter voltage
symmetry
VTXsym = VCANH + VCANL;
CSPLIT = 4.7 nF;
fTXD = 250 kHz, 1 MHz or 2.5 MHz
Vcm(step)
common mode voltage step
[3]
[4]
[3]
[4]
[5]
Vcm(p-p)
VO(dif)
[3]
peak-to-peak common mode
voltage
differential output voltage
[4]
[5]
dominant; Normal mode; VTXD = 0 V;
VCC ≥ 4.75 V
RL = 2240 Ω
[3]
recessive; no load
Normal or Silent mode; VTXD = VIO
VO(rec)
recessive output voltage
Normal or Silent mode; VTXD = VIO; no
load
2
2.5
3
V
Vth(RX)dif
differential receiver
threshold voltage
Normal or Silent mode;
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
0.5
-
0.9
V
Vrec(RX)
receiver recessive voltage
Normal or Silent mode;
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
-4
-
0.5
V
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Table 8. Static characteristics...continued
Tvj = -40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJF1441A); RL = 60 Ω; unless specified otherwise; all
[1]
voltages are defined with respect to ground; positive currents flow into the IC.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vdom(RX)
receiver dominant voltage
Normal or Silent mode;
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
0.9
-
9
V
Vhys(RX)dif
differential receiver
hysteresis voltage
Normal or Silent mode;
-12 V ≤ VCANH ≤ +12 V;
-12 V ≤ VCANL ≤ +12 V
50
-
-
mV
IO(sc)
short-circuit output current
-15 V ≤ VCANH ≤ +40 V;
-15 V ≤ VCANL ≤ +40 V
-
-
115
mA
IO(sc)rec
recessive short-circuit output Normal mode; VTXD = VIO;
current
-27 V ≤ VCANH ≤ +32 V;
-27 V ≤ VCANL ≤ +32 V
-3
-
+3
mA
IL
leakage current
VCC = VIO = 0 V or pins shorted to GND
via 47 KΩ; VCANH = VCANL = 5 V;
-10
-
+10
µA
Ri
input resistance
-2 V ≤ VCANL ≤ +7 V;
-2 V ≤ VCANH ≤ +7 V
25
40
50
kΩ
ΔRi
input resistance deviation
0 V ≤ VCANL ≤ +5 V; 0 V ≤ VCANH ≤ +5 V
-3
-
+3
%
Ri(dif)
differential input resistance
-2 V ≤ VCANL ≤ +7 V;
-2 V ≤ VCANH ≤ +7 V
50
80
100
kΩ
Ci(cm)
common-mode input
capacitance
[3]
-
-
20
pF
Ci(dif)
differential input capacitance
[3]
-
-
10
pF
Temperature detection
Tj(sd)
shutdown junction
temperature
180
-
200
°C
Tj(sd)rel
release shutdown junction
temperature
175
-
195
°C
[1]
[2]
[3]
[4]
[5]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected
above max value.
Not tested in production; guaranteed by design.
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 9.
See Figure 7
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11 Dynamic characteristics
Table 9. Dynamic characteristics
Tvj = −40 °C to +150 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V (TJF1441A); RL = 60 Ω; unless specified otherwise; all
[1]
voltages are defined with respect to ground.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CAN timing characteristics; tbit(TXD) ≥ 200 ns; see Figure 5, Figure 6 and Figure 9
td(TXD-busdom)
delay time from TXD to bus dominant
Normal mode
-
-
102.5 ns
td(TXD-busrec)
delay time from TXD to bus recessive
Normal mode
-
-
102.5 ns
td(busdom-RXD) delay time from bus dominant to RXD
Normal or Silent mode
-
-
115
ns
td(busrec-RXD)
delay time from bus recessive to RXD
Normal or Silent mode
-
-
115
ns
td(TXDL-RXDL)
delay time from TXD LOW to RXD LOW
Normal mode
-
-
215
ns
td(TXDH-RXDH)
delay time from TXD HIGH to RXD HIGH Normal mode
-
-
215
ns
tbit(TXD) = 500 ns
435
-
530
ns
tbit(TXD) = 200 ns
155
-
210
ns
tbit(TXD) = 500 ns
400
-
550
ns
tbit(TXD) = 200 ns
120
-
220
ns
tbit(TXD) = 500 ns
-65
-
40
ns
tbit(TXD) = 200 ns
-45
-
15
ns
CAN FD timing characteristics; see Figure 6 and Figure 9
tbit(bus)
tbit(RXD)
Δtrec
transmitted recessive bit width
bit time on pin RXD
receiver timing symmetry
Mode transitions
tt(moch)
tstartup
mode change transition time
[2]
-
-
50
µs
start-up time
[2]
-
-
1
ms
I/O filter time
[3]
1
-
5
µs
on pin VCC
[2]
-
-
30
µs
on pin VIO
[2]
-
-
30
µs
on pin VCC
[2]
-
-
50
µs
IO filter; pins S
tfltr(IO)
Undervoltage detection; see Figure 3
tdet(uv)
tuvd(swoff)
trec(uv)
[1]
[2]
[3]
undervoltage detection time
switch-off undervoltage detection time
undervoltage recovery time
All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified
temperature and power supply voltage ranges.
Not tested in production; guaranteed by design.
Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed.
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TXD
HIGH
70 %
30 %
LOW
CANH
CANL
dominant
0.9 V
VO(dif)
0.5 V
recessive
RXD
HIGH
70 %
30 %
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
aaa-029311
Figure 5. CAN transceiver timing diagram
70 %
TXD
30 %
30 %
td(TXDL-RXDL)
5 x tbit(TXD)
tbit(TXD)
0.9 V
VO(dif)
0.5 V
tbit(bus)
70 %
RXD
30 %
td(TXDH-RXDH)
tbit(RXD)
aaa-029312
Figure 6. CAN FD timing definitions according to ISO 11898-2:2016
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CANH
CANL
Vcm(step)
VCANH + VCANL
Vcm(p-p)
aaa-037830
Figure 7. CAN bus common-mode voltage
12 Application information
12.1 Application diagram
BAT
3.3 V
(1)
on/off control
5V
(1)
CANH
VCC
VIO
Pxx
S
TJF1441A
CANL
TXD
RXD
Pyy
TX0
RX0
GND
VDD
µC + CAN
CONTROLLER
GND
aaa-030781
Figure 8. Typical application
12.2 Application hints
Further information on the application of the TJF1441 can be found in NXP application
hints AH2002 'TJx144x/TJx146x Application Hints', available on request from NXP
Semiconductors.
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13 Test information
TXD
CANH
RL
60 Ω
RXD
CL
100 pF
CANL
15 pF
aaa-030850
Figure 9. CAN transceiver timing test circuit
TXD
CANH
30 Ω
fTXD
CSPLIT
4.7 nF
RXD
30 Ω
CANL
aaa-030851
Figure 10. Test circuit for measuring transceiver driver symmetry
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14 Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
A2
Q
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.20
0.014 0.0075 0.19
0.16
0.15
inches
0.010 0.057
0.069
0.004 0.049
0.05
0.244
0.039 0.028
0.041
0.228
0.016 0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Figure 11. Package outline SOT96-1 (SO8)
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15 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
16 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and Table 11
Table 10. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 11. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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17 Appendix: ISO 11898-2:2016 parameter cross-reference list
Table 12. ISO 11898-2:2016 to NXP data sheet parameter conversion
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)dom
Absolute current on CAN_L
ICAN_L
dominant short-circuit output
current
HS-PMA dominant output characteristics
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
Differential output voltage
VDiff
VO(rec)
recessive output voltage
VO(dif)
differential output voltage
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
Dominant state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
ΔRi
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to
RXD LOW
HS-PMA implementation loop delay requirement
Loop delay
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2
Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
ΔtRec
Δtrec
receiver timing symmetry
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Table 12. ISO 11898-2:2016 to NXP data sheet parameter conversion...continued
ISO 11898-2:2016
NXP data sheet
Parameter
Notation
Symbol
Parameter
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
General maximum rating VCAN_H and VCAN_L
VCAN_H
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
TJF1441
Product data sheet
ICAN_H
ICAN_L
IL
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18 Appendix: TJx144x/TJx146x/TJF1441 family overview
Table 13. Feature overview of the complete TJx144x/TJx146x/TJF1441 family
Data rate
Additional features
TXD dominant timeout
[6]
Single supply pin wake-up
Short WUP support [0.5 - 1.8 µs]
[4]
Wake-up source recognition
Signal improvement
[3]
[2]
Up to 8 Mbit/s CAN FD
Up to 5 Mbit/s CAN FD
VBAT pin
VIO pin
●
●
●
●
●
●
●
●
●
●
TJx1441D
●
●
●
●
●
TJF1441A
●
●
[7]
TJx1442A
●
●
TJx1442B
●
●
TJx1443A
●
●
TJx1448A
●
TJx1448B
Sleep
VCC pin
Selectable Off
Silent/Listen-only
Standby
●
TJx1441B
[1]
Normal
TJx1441A
Device
●
●
●
●
●
●
●
●
●
●
●
●
●
●
TJx1448C
●
●
●
●
●
TJx1462A
●
●
●
●
●
●
TJx1462B
●
●
●
●
●
TJx1463A
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
[1]
[2]
[3]
[4]
[5]
[6]
[7]
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Local diagnostics via ERR_N pin
Supplies
[5]
Modes
●
●
●
●
●
TJx: TJA14xxx is AEC-Q100 Grade 1; TJR14xxx is AEC-Q100 Grade 0; TJF1441A is non-automotive grade.
Only guaranteed for TJA146x, AEC-Q100 Grade 1.
CAN FD Signal Improvement Capability (SIC) according to CiA 601-4:2019.
RXD is held LOW after wake-up request, enabling wake-up source recognition.
WUP = wake-up pattern according ISO11898-2:2016.
Only VIO supply needed for wake-up in TJA1442A, TJA1448A, TJA1448C, TJA1462A; only VBAT supply needed for wake-up in TJA1443A, TJA1463A.
Not having TXD dominant timeout allows for very low data rates in non-automotive grade applications.
19 Revision history
Table 14. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TJF1441 v.2
20211015
Product data sheet
-
TJF1441 v.1
Modifications
• Added device (Table 3) and family (Section 18) feature overviews
• Table 6: table note 10 added
• Table 9: CAN delay timing characteristics revised
TJF1441 v.1
20200812
TJF1441
Product data sheet
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-
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-
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20 Legal information
20.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
20.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
TJF1441
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
TJF1441
Product data sheet
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 October 2021
© NXP B.V. 2021. All rights reserved.
26 / 27
TJF1441
NXP Semiconductors
High-speed CAN transceiver
Contents
1
2
2.1
2.2
2.3
3
4
5
6
6.1
6.2
7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.2
7.2.3
7.2.4
8
9
10
11
12
12.1
12.2
13
14
15
16
16.1
16.2
16.3
16.4
17
18
19
20
General description ............................................ 1
Features and benefits .........................................1
General .............................................................. 1
Predictable and fail-safe behavior ..................... 1
Protection ...........................................................2
Quick reference data .......................................... 2
Ordering information .......................................... 2
Block diagram ..................................................... 4
Pinning information ............................................ 5
Pinning ............................................................... 5
Pin description ................................................... 5
Functional description ........................................6
Operating modes ............................................... 6
Off mode ............................................................7
Silent mode ........................................................7
Normal mode ..................................................... 7
Operating modes and gap-free operation .......... 8
Fail-safe features ............................................... 8
Internal biasing of TXD and S input pins ........... 8
Undervoltage detection on pins VCC and
VIO .....................................................................9
Overtemperature protection ............................... 9
VIO supply pin ................................................... 9
Limiting values .................................................. 10
Thermal characteristics ....................................11
Static characteristics ........................................ 11
Dynamic characteristics ...................................14
Application information .................................... 16
Application diagram ......................................... 16
Application hints .............................................. 16
Test information ................................................ 17
Package outline .................................................18
Handling information ........................................ 19
Soldering of SMD packages .............................19
Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
Appendix: ISO 11898-2:2016 parameter
cross-reference list ........................................... 22
Appendix: TJx144x/TJx146x/TJF1441
family overview ................................................. 24
Revision history ................................................ 24
Legal information .............................................. 25
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 October 2021
Document identifier: TJF1441
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