TJR1443ATK/0Z

TJR1443 High-speed CAN transceiver with Sleep mode Rev. 2 — 15 October 2021 1 Product data sheet General description The TJR1443 is a member of the TJR144x family of transceivers that provide an interface between a Controller Area Network (CAN) or CAN FD (Flexible Data rate) protocol controller and the physical two-wire CAN bus. TJR144x transceivers implement the CAN physical layer as defined in ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5, and are fully interoperable with high-speed Classical CAN and CAN FD transceivers. All TJR144x variants enable reliable communication in the CAN FD fast phase at data rates up to 5 Mbit/s and are qualified to AEC-Q100 Grade 0, supporting operation at 150 °C ambient temperature. The TJR1443 is intended as a simple replacement for high-speed Classical CAN and CAN FD transceivers, such as the TJA1043 from NXP. It offers pin compatibility and is designed to avoid changes to hardware and software design, allowing the TJR1443 to be easily retrofitted to existing applications. An AEC-Q100 Grade 1 variant, the TJA1443, is available to support operation at 125 °C ambient temperature. 2 Features and benefits 2.1 General • • • • • • • ISO 11898-2:2016, SAE J2284-1 to SAE J2284-5 and SAE J1939-14 compliant Standard CAN and CAN FD data bit rates up to 5 Mbit/s Low Electromagnetic Emission (EME) and high Electromagnetic Immunity (EMI) Qualified according to AEC-Q100 Grade 0 VIO input for interfacing with 3.3 V to 5 V microcontrollers Listen-only mode for node diagnosis and failure containment Available in SO14 and leadless HVSON14 (3.0 mm x 4.5 mm) packages; HVSON14 with improved Automated Optical Inspection (AOI) capability. • Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant) 2.2 Predictable and fail-safe behavior • Undervoltage detection with defined handling on all supply pins • Full functionality guaranteed from the undervoltage detection thresholds up to the maximum limiting voltage values • Defined behavior below the undervoltage detection thresholds • Transceiver disengages from the bus (high-ohmic) when the battery voltage drops below the Off mode threshold • Internal biasing of TXD and mode selection input pins, to enable defined fail-safe behavior TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 2.3 Low-power management • Very low-current Standby and Sleep modes, with host, local and bus wake-up capability • Entire node with TJR1443 can be powered down while still supporting local, bus and host wake-up • CAN wake-up receiver powered by VBAT allowing VIO and VCC to be shut down • CAN wake-up pattern filter time of 0.5 μs to 1.8 μs, meeting Classical CAN and CAN FD requirements 2.4 Diagnosis & Protection • Overtemperature diagnosis • Transmit Data (TXD) dominant time-out and TXD-to-RXD short-circuit handler with diagnosis • Bus dominant clamping diagnosis • Cold start diagnosis (first battery connection) • High ESD handling capability on the bus pins (8 kV IEC and HBM) • Bus pins and VBAT protected against transients in automotive environments • Thermally protected TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 2 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 3 Quick reference data Table 1. Quick reference data Symbol Parameter VBAT battery supply voltage IBAT battery supply current Conditions Min Typ Max Unit 4.5 - 28 V Normal or Listen-only mode - 80 300 µA Standby or Sleep mode - 13 20 µA Vuvd(VBAT) undervoltage detection voltage on pin VBAT 4 - 4.5 V VCC supply voltage 4.5 - 5.5 V ICC supply current Normal mode, dominant - 38 60 mA Normal mode, recessive - 4 7 mA Listen-only mode - 3 5 mA Standby or Sleep mode - - 2 μA Vuvd(VCC) undervoltage detection voltage VBAT > 4.5 V on pin VCC 4 - 4.5 V Vuvhys(VCC) undervoltage hysteresis voltage on pin VCC 50 - - mV VIO supply voltage on pin VIO 2.95 - 5.5 V IIO supply current on pin VIO Normal mode, dominant; VTXD = 0 V - 90 250 µA Normal mode, recessive; all other modes; VTXD = VIO - - 2 µA Vuvd(VIO) undervoltage detection voltage VBAT > 4.5 V on pin VIO 2.65 - 2.95 V Vuvhys(VIO) undervoltage hysteresis voltage on pin VIO 50 - - mV VESD electrostatic discharge voltage IEC 61000-4-2 on pins CANH and CANL -8 - +8 kV VCANH voltage on pin CANH limiting value according to IEC 60134 -36 - +40 V VCANL voltage on pin CANL limiting value according to IEC 60134 -36 - +40 V Tvj virtual junction temperature -40 - +175 °C 4 Ordering information Table 2. Ordering information Type number Package Name Description Version TJR1443AT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 TJR1443ATK HVSON14 plastic thermal enhanced very thin small outline package; no leads; 14 terminals; body 3 × 4.5 × 0.85 mm SOT1086-2 TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 3 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 3. TJR1443 feature overview See Section 19 for a feature overview of the complete TJx144x/TJx146x/TJF1441 family. Supplies Data rate Additional features [1] [2] [3] [4] [5] ● ● ● [5] ● Local diagnostics via ERR_N pin ● TXD dominant timeout ● [2] ● Signal improvement ● Up to 8 Mbit/s CAN FD Up to 5 Mbit/s CAN FD ● VBAT pin ● VIO pin ● VCC pin Silent/Listen-only ● Selectable Off Sleep TJR1443A Standby [1] Normal Device Single supply pin wake-up Short WUP support [0.5 - 1.8 µs] ● [3] Wake-up source recognition [4] Modes TJR1443 is AEC-Q100 Grade 0. CAN FD Signal Improvement Capability (SIC) according to CiA 601-4:2019. RXD is held LOW after wake-up request, enabling wake-up source recognition. WUP = wake-up pattern according ISO11898-2:2016. Only VBAT supply needed for wake-up. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 4 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 5 Block diagram VIO VIO VCC VBAT 5 3 10 TEMPERATURE PROTECTION 13 CANH TRANSMITTER TXD 1 12 TIME-OUT CANL VBAT 5V WAKE 9 VIO ERR_N STB_N EN 8 14 MODE CONTROL AND WAKE-UP CONTROL AND LOCAL FAILURE DETECTION VBAT 7 6 normal receiver VIO RXD INH MUX AND DRIVER 4 WAKE-UP FILTER 11 low-power receiver 2 n.c. GND aaa-038098 Figure 1. TJR1443 block diagram TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 5 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 6 Pinning information 6.1 Pinning terminal 1 index area TXD 1 14 STB_N GND 2 13 CANH VCC 3 12 CANL RXD 4 11 n.c. VIO 5 10 VBAT EN 6 9 WAKE INH 7 8 ERR_N TXD 1 14 STB_N GND 2 13 CANH VCC 3 12 CANL RXD 4 11 n.c. VIO 5 10 VBAT EN 6 9 WAKE INH 7 8 ERR_N aaa-038083 Transparent top view aaa-038082 TJR1443AT: SO14 TJR1443ATK: HVSON14 Figure 2. Pin configuration diagrams 6.2 Pin description Table 4. Pin description [1] Symbol Pin Type TXD 1 I transmit data input; inputs data (from the CAN controller) to be written to the bus lines 2 G ground VCC 3 P 5 V supply voltage input RXD 4 O receive data output; outputs data read from the bus lines (to the CAN controller) VIO 5 P supply voltage input for I/O level adapter EN 6 I enable control input INH 7 AO inhibit output for switching external voltage regulators ERR_N 8 O local failure detection; wake-up source recognition and power-on indication output (active-LOW) WAKE 9 AI local wake-up input VBAT 10 P battery supply voltage input n.c. 11 - not connected CANL 12 AIO LOW-level CAN bus line CANH 13 AIO HIGH-level CAN bus line STB_N 14 I Standby mode control input (active-LOW) GND [1] [2] [2] Description I: digital input; O: digital output; AI: analog input; AO: analog output; AIO: analog input/output; P: power supply; G: ground HVSON14 package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is also recommended to solder the exposed center pad to board ground. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 6 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 7 Functional description 7.1 Operating modes The TJR1443 contains two independent state machines, a system state machine and a CAN state machine. Two state machines are needed to secure flag handling during undervoltage conditions. These state machines support a number of interdependent operating modes. The system state machine controls the CAN state machine, but both state machines are independently affected by the VCC undervoltage status. For both state machines, undervoltage detection is defined as Vx < Vuvd(x) for t > tdet(uv) and undervoltage recovery is defined as Vx > Vuvd(x) for t > trec(uv). 7.1.1 System operating modes The system state machine in the TJR1443 supports five system operating modes. Control pins STB_N and EN are used to select the operating mode. Figure 3 describes how to switch between operating modes. Mode changes are completed after transition time tt(moch). Fail-safe diagnostic information, as described in Section 7.2, is available on pin ERR_N with a delay of td(moch-ERR_N) after a mode change. from any mode when VBAT < Vuvd(VBAT) for t > tdet(uv)BAT Off (INH = highohmic) from Standby, Normal or Listen-only when VCC < Vuvd(VCC) for t > t det(uv)long VBAT > Vuvd(VBAT) for t > t startup Wake flag set OR (rising edge on STB_N AND VIO > Vuvd(VIO) for t > t rec(uv)VIO) OR [VCC > Vuvd(VCC) for t > t rec(uv)VCC AND STB_N = HIGH AND VIO > Vuvd(VIO) for t > t rec(uv)VIO] Sleep (INH = highohmic) STB_N = HIGH AND EN = HIGH AND VIO > Vuvd(VIO) for t > t rec(uv)VIO Standby (INH = HIGH) STB_N = LOW OR V IO < Vuvd(VIO) for t > t det(uv)VIO (STB_N = LOW AND EN = HIGH for t > th(gotosleep) AND Wake flag not set AND V IO > Vuvd(VIO) for t > t rec(uv)VIO) OR V IO < Vuvd(VIO) for t > t det(uv)long Normal (INH = HIGH) STB_N = HIGH AND EN = HIGH AND VIO > Vuvd(VIO) for t > t rec(uv)VIO STB_N = HIGH AND EN = LOW AND VIO > Vuvd(VIO) for t > trec(uv)VIO STB_N = LOW OR VIO < Vuvd(VIO) for t > tdet(uv)VIO STB_N = HIGH AND EN = LOW AND VIO > Vuvd(VIO) for t > t rec(uv)VIO Listen-only (INH = HIGH) aaa-037553 Figure 3. TJR1443 system state diagram 7.1.1.1 Off mode The TJR1443 switches to Off mode from any mode mode when the battery voltage falls below the undervoltage detection threshold, Vuvd(VBAT). The device starts up in Off mode TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 7 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode when the battery is connected for the first time (cold start). Pins INH and ERR_N are in a high-ohmic state in Off mode. 7.1.1.2 Standby mode Standby mode is the first-level power-saving mode of the TJR1443. When VBAT rises above the undervoltage detection threshold, Vuvd(VBAT), the TJR1443 starts to boot up, triggering an initialization procedure. It switches to Standby mode after tstartup, resulting in a HIGH level on pin INH. When VIO rises above the undervoltage detection threshold, Vuvd(VIO), the TJR1443 switches to Normal mode if pins STB_N and EN are HIGH, and to Listen-only mode if STB_N is HIGH and EN is LOW. It will remain in Standby mode if STB_N is LOW. The TJR1443 will switch to Sleep mode if VIO remains below Vuvd(VIO) for tdet(uv)long and/or VCC remains below Vuvd(VCC) for tdet(uv)long. A transition from Standby mode to Sleep mode can also be triggered by holding STB_N LOW and EN HIGH for th(gotosleep) (also known as a 'go-to-sleep' command). This 'go-to-sleep' command is overruled if the Wake flag is set, in which case the device remains in Standby mode. 7.1.1.3 Normal mode HIGH levels on pin STB_N and pin EN selects Normal mode, provided the battery supply voltage, VBAT, and VIO are present. Pin INH remains HIGH, so voltage regulators controlled by pin INH will also be active (see Figure 10). 7.1.1.4 Listen-only mode A HIGH level on pin STB_N and a LOW level on pin EN selects Listen-only mode, provided VBAT and VIO are present. Pin INH remains HIGH, so voltage regulators controlled by pin INH will also be active. In Listen-only mode the receiver is enabled, but the transmitter is disabled. 7.1.1.5 Sleep mode Sleep mode is the second-level power-saving mode of the TJR1443. Sleep mode is entered in a number of ways: • via Standby mode, in response to a 'go-to-sleep' command • via Standby mode as a result of a VIO undervoltage longer than tdet(uv)long • via all other modes, except Off mode, as a result of a VCC undervoltage longer than tdet(uv)long In Sleep mode, the transceiver behaves as described for Standby mode, with the exception that pin INH is set high-ohmic. Voltage regulators controlled by this pin are switched off and the current into pin VBAT is reduced to a minimum. A number of events will cause the TJR1443 to exit Sleep mode, switching to Standby mode: • setting the Wake flag • a rising edge on pin STB_N (if VIO > Vuvd(VIO)) • VCC > Vuvd(VCC), VIO > Vuvd(VIO) and the ‘go-to-sleep’ command has not been activated. After entering Standby mode, the TJR1443 will enter Normal or Listen-Only if STB_N is HIGH. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 8 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 7.1.1.6 System operating modes and gap-free operation Gap-free operation guarantees defined behavior at all voltage levels. Supply voltage-tooperating mode mapping is detailed in Figure 4. VBAT > 4.5 V[1][2] Fully functional [3][4] Fully functional[3] AND characteristics guaranteed[5] VCC operating range (4.5 - 5.5 V) Fully functional [3] OR Standby OR Sleep [6] Vuvd(vcc) range[7] -0.3 V - 4 V 5.5 - 6 V[2] Vuvd(VIO) range [7] -0.3 V - 2.65 V Sleep VIO operating range (2.95 - 5.5 V) Voltage range on VCC 5.5 - 6 V[2] Voltage range on VIO [1] VBAT operating range is 4.5 V - 28 V and the undervoltage detection threshold range, Vuvd(BAT), is 4 V - 4.5 V. For VBAT < 4 V, the device is in Off state. For 4 V ≤ VBAT ≤ 4.5 V the device is either in Off state (if a VBAT undervoltage has been triggered) or in the state as shown in this diagram (if a VBAT undervoltage has not been triggered). For 28 V < VBAT < 40 V this diagram applies, with the single exception that the datasheet characteristics are not guaranteed. [2] 6 V is the IEC 60134 Absolute Maximum Rating (AMR) for VCC and VIO, 40 V the AMR for VBAT (see Limiting values table). Above the AMR, irreversible changes in characteristics, functionality or performance may occur. Returning from above AMR to the operating range, datasheet characteristics and functionality cannot be guaranteed. [3] Target transceiver functionality as described in the datasheet is applicable. [4] Prolonged operation of the device outside the operating range may impact reliability over lifetime. Returning to the operating range, datasheet characteristics are guaranteed provided the AMR has not been exceeded. [5] Datasheet characteristics are guaranteed within the VBAT, VCC and VIO operating ranges. Exceptions are described in the Static and Dynamic characteristics tables. [6] For a given value of VCC and VIO, a specific device will be in a single defined state, determined by its undervoltage detection thresholds Vuvd(VCC) and Vuvd(VIO). The actual thresholds can vary between devices (within the ranges specified in this datasheet). To guarantee the device will be in a specific state, VCC and VIO must be either above the maximum or below the minimum thresholds specified for these undervoltage detection ranges. [7] The device is fully functional when both VCC and VIO are above the undervoltage threshold. If VCC or VIO is below the undervoltage threshold, the device will be in Standby or Sleep mode. aaa-037492 Figure 4. TJR1443 supply voltage ranges and gap-free operation TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 9 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 7.1.2 CAN operating modes The CAN state machine supports six operating modes. from any mode Off CAN Off (CAN Bias = high-ohmic) Standby OR Sleep (Standby OR Sleep) AND Wake flag set CAN Offline (CAN Bias = 0 V) Standby OR Sleep Standby OR Sleep Listen-only AND VCC > Vuvd(VCC) for t > trec(uv)VCC (Standby OR Sleep) AND Wake flag not set Normal OR Listen-only Standby OR Sleep CAN Pass-through (CAN Bias = 0 V) Normal AND VCC > Vuvd(VCC) for t > trec(uv)VCC VCC < Vuvd(VCC) for t > tdet(uv)VCC VCC < Vuvd(VCC) for t > tdet(uv)VCC) CAN Listen-only (CAN Bias = VCC/2) Listen-only AND VCC > Vuvd(VCC) for t > trec(uv)VCC CAN Wake (CAN Bias = 0 V) Normal AND VCC > Vuvd(VCC) for t > trec(uv)VCC CAN Active (CAN Bias = VCC/2) Normal AND VCC > Vuvd(VCC) for t > trec(uv)VCC Listen-only AND VCC > Vuvd(VCC) for t > trec(uv)VCC aaa-037828 Figure 5. TJR1443 CAN state diagram 7.1.2.1 CAN Off mode When the TJR1443 system state machine is in Off mode, the CAN state machine will be in CAN Off mode, with the bus pins and pin RXD in a high-ohmic state. 7.1.2.2 CAN Offline mode When the TJR1443 system state machine is in Sleep or Standby mode and the Wake flag has not been set, the CAN state machine will be in CAN Offline mode. The bus pins are biased to ground. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 10 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode The transceiver is unable to transmit or receive data and the low-power receiver is activated to monitor the bus for a wake-up pattern. Pin RXD is HIGH. 7.1.2.3 CAN Wake mode When the TJR1443 system state machine is in Sleep or Standby mode and the wake flag has been set, the CAN state machine will be in CAN Wake mode. Pin RXD will be LOW, reflecting the active wake-up request. The bus pins are biased to ground. 7.1.2.4 CAN Pass-through mode When the TJR1443 system state machine is in Normal or Listen-only mode and VCC is below the undervoltage detection threshold, Vuvd(VCC), the CAN state machine will be in CAN Pass-through mode. The transceiver cannot transmit data via the bus lines in this mode. The output voltage on the bus pins is biased to ground. Differential data on the bus pins is converted to digital data via the low-power receiver and the results are output on pin RXD. 7.1.2.5 CAN Active mode When the TJR1443 system state machine is in Normal mode and VCC is above the undervoltage detection threshold, Vuvd(VCC), the CAN state machine will be in CAN Active mode. The transceiver can transmit and receive data via bus lines CANH and CANL. Pin TXD must be HIGH at least once in CAN Active mode before the first transmission can begin. The differential receiver converts the analog data on the bus lines into digital data on pin RXD. In recessive state, the output voltage on the bus pins is VCC/2. 7.1.2.6 CAN Listen-only mode When the TJR1443 system state machine is in Listen-only mode and VCC is above the undervoltage detection threshold, Vuvd(VCC), the CAN state machine will be in CAN Listen-only mode. The transmitter is disabled. The differential receiver converts the analog data on the bus lines into digital data on pin RXD. As in CAN Active mode, the bus pins are biased to VCC/2. 7.2 Internal flags The device makes use of four internal flags for fail-safe fallback control and system diagnosis. These flags can be polled by the controller via pin ERR_N while VIO is active. Which flag is available on pin ERR_N at any time depends on the current system operating mode; see Table 5. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 11 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 5. Accessing internal flags via pin ERR_N [1] Internal flag Flag available on pin ERR_N Flag status: set Pwon in Listen-only mode (coming from Standby or Sleep mode) Wake in Standby and Sleep modes (provided VIO and VBAT are present) [2] [2] Flag status: not set Flag cleared VBAT has risen above Vuvd(VBAT) VBAT has not risen above Vuvd(VBAT) on entering Normal mode remote or local wake-up detected OR Pwon flag has been set no remote or local wake-up on entering Normal mode detected Wake-up source in Normal mode local wake-up OR Pwon flag has been set remote wake-up OR no wake-up on leaving Normal mode Local failure on occurrence of: - TXD dominant failure OR - TXD-RXD short circuit OR - Bus dominant failure OR - Overtemperature none of the set conditions have been met when Pwon flag is set or, provided all local failures have been resolved, when: - device enters Normal mode OR - RXD dominant while TXD recessive OR - bus dominant failure resolved AND no other local failure has set the flag [1] [2] in Listen-only mode (coming from Normal mode) Pin ERR_N is an active-LOW output; a LOW level indicates a set flag and a HIGH level indicates the flag has not been set. Status since flag was last cleared. 7.2.1 Pwon flag Pwon is the VBAT power-on flag. This flag is set when the voltage on pin VBAT recovers after previously dropping below Vuvd(VBAT) (usually because the battery was disconnected). The Pwon flag can be used for cold start diagnosis. The Wake and Wake-up source flags are set to ensure consistent system power-up under all supply conditions. Coming from Sleep or Standby and entering Listen-Only mode, a LOW level on pin ERR_N signals that the Pwon flag has been set. The flag is cleared when the transceiver enters Normal mode. 7.2.2 Wake flag The Wake flag is set when the transceiver detects a local or remote wake-up request. 7.2.2.1 Local wake-up (via WAKE pin) A local wake-up request is registered when the logic level on pin WAKE changes and the new level remains stable for at least twake. The system state machine can set the Wake flag in Standby or Sleep mode. Setting the Wake flag clears the timers. Once set, the Wake flag status is immediately available on pins ERR_N and RXD (provided VIO and VBAT are present). This flag is also set at power-on and cleared when the transceiver enters Normal mode. 7.2.2.2 Remote wake-up (via the CAN bus) The TJR1443 wakes up from Sleep to Standby mode when a dedicated wake-up pattern (specified in ISO 11898-2: 2016) is detected on the bus. The wake-up pattern consists of: • a dominant phase of at least twake(busdom) followed by • a recessive phase of at least twake(busrec) followed by • a dominant phase of at least twake(busdom) Dominant or recessive bits between the above mentioned phases that are shorter than twake(busdom) and twake(busrec) respectively are ignored. The complete dominant-recessive-dominant pattern must be received within tto(wake)bus to be recognized as a valid wake-up pattern (see Figure 6). Otherwise, the internal wakeTJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 12 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode up logic is reset. The complete wake-up pattern then needs to be retransmitted to trigger a wake-up event. Pins RXD and ERR_N remain HIGH until the wake-up event has been triggered and then switch LOW after tstartup(RXD). Pin INH remains floating until the wakeup event has been triggered and then switches HIGH after tstartup(INH). A wake-up event is not flagged on RXD if any of the following events occurs while a valid wake-up pattern is being received: • The device switches to Normal mode • The complete wake-up pattern was not received within tto(wake)bus • A VCC or VIO undervoltage is detected CANH VO(dif) CANL twake(busdom) twake(busrec) twake(busdom) wake-up pattern detected RXD ≤ tto(wake)bus tstartup(RXD) INH tstartup(INH) aaa-038570 Figure 6. TJR1443 wake-up timing 7.2.3 Wake-up source flag Wake-up source recognition is provided via the Wake-up source flag. It is set after the Wake flag has been set by a local wake-up request via the WAKE pin. The Wake-up source flag can be polled via the ERR_N pin in Normal mode (see Table 5). This flag is also set at power-on and cleared when the transceiver leaves Normal mode. 7.2.4 Local failure flag In Normal and Listen-only modes, the transceiver can distinguish four local failure events, any of which will cause the Local failure flag to be set. The four local failure events are: • • • • TXD dominant failures TXD-to-RXD short circuit Bus dominant failures Overtemperature The nature and detection of these local failures is described in Section 7.3. The Local failure flag can be polled via the ERR_N pin in Listen-only mode, when coming from Normal mode (see Table 5). TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 13 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode This flag is cleared at power-on when the Pwon flag is set or, provided all local failures have been resolved, when: • The device enters Normal mode OR • RXD is dominant while TXD is recessive OR • Bus dominant failure has been resolved AND no other local failure has set the flag 7.3 Local failure events The TJR1443 can detect four different local failure conditions, any of which will set the Local failure flag. In most cases, the transmitter is disabled. 7.3.1 TXD dominant failures A hardware and/or software application failure that caused pin TXD to be held LOW would drive the bus lines to a permanent dominant state (blocking all network communications). The TXD dominant time-out function prevents such a network lock-up. A 'TXD dominant time-out' timer is started when pin TXD goes LOW. If the LOW state on this pin persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus lines to recessive state. The transmitter remains disabled until the Local failure flag has been cleared. The TXD dominant time-out timer is reset when pin TXD is set HIGH. 7.3.2 TXD-to-RXD short circuit A short-circuit between pins RXD and TXD would lock the bus in a permanent dominant state once it had been driven dominant, because the low-side driver of RXD is typically stronger than the high-side driver of the controller connected to TXD. TXD-to-RXD short-circuit detection prevents such a network lock-up by disabling the transmitter. The transmitter remains disabled until the Local failure flag has been cleared. 7.3.3 Bus dominant failures A CAN bus short circuit (to VBAT, VCC or GND) or a failure in one of the other network nodes could result in a differential voltage on the bus high enough to represent a bus dominant state. Because a node will not begin to transmit while the bus is dominant, the host controller would not be able to detect this failure condition. However, bus dominant clamping detection will detect the short circuit. The Local failure flag is set if the dominant state on the bus persists for longer than tto(dom)bus. By checking this flag, the controller can determine if a clamped bus is blocking network communications. There is no need to disable the transmitter. Note that the Local failure flag is reset as soon as the bus returns to recessive state. 7.3.4 Overtemperature The device is protected against overtemperature conditions. If the junction temperature exceeds the shutdown junction temperature, Tj(sd), the CAN bus drivers are disabled. The transmitter will remain disabled until the junction temperature drops below Tj(sd)rel and the Local failure flag has been cleared. 7.4 I/O levels Pin VIO should be connected to the same supply voltage used to supply the microcontroller. This adjusts the signal levels on pins TXD, RXD, STB_N, EN and TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 14 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode ERR_N to the I/O levels of the microcontroller, allowing for direct interfacing without additional glue logic. Spurious signals from the microcontroller on pins STB_N and EN are filtered out with a filter time of tfltr(IO). 7.5 WAKE pin A local wake-up event is triggered by a LOW-to-HIGH or HIGH-to-LOW transition on the WAKE pin when VWAKE passes the wake-up threshold, Vth(wake). After the transition, the new HIGH or LOW level should remain stable for at least twake. This allows for maximum flexibility when designing a local wake-up circuit. A local wake-up is guaranteed in the case of: - a LOW-to-HIGH transition from VWAKE < Vth(wake)min to VWAKE > Vth(wake)max, followed by VWAKE > Vth(wake)max for t > twake(max) - a HIGH-to-LOW transition from VWAKE > Vth(wake)max to VWAKE < Vth(wake)min, followed by VWAKE < Vth(wake)min for t > twake(max) A local wake-up is guaranteed not to occur if the HIGH/LOW level after the transition does not remain stable for at least t(wake)min. To minimize current consumption, the internal bias voltage follows the logic state on the pin after a delay of twake. A HIGH level on pin WAKE is followed by an internal pull-up to VBAT. A LOW level on pin WAKE is followed by an internal pull-down towards GND. In applications that do not make use of the local wake-up facility, it is recommended to connect the WAKE pin to pin VBAT or GND for optimal EMI performance. 7.6 Internal biasing of TXD, STB_N and EN input pins Pin TXD has an internal pull-up to VIO and pins STB_N and EN have internal pull-downs to GND to ensure a safe, defined state in case one, or all, of these pins is left floating. Pull-up/pull-down resistors are present on these pins in all states. Pull-down on pin EN is only active when VBAT is present. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 15 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 8 Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are referenced to pin GND, unless otherwise specified; positive currents flow into the IC. Symbol Vx Parameter Voltage on pin x [1] Conditions Min Max Unit pins VCC, VIO, TXD, STB_N, EN −0.3 +6 V pin VBAT, load dump −0.3 V pins CANH, CANL, WAKE −36 +40 V electrostatic discharge voltage [5] −0.3 VIO+0.3 V -2 - mA −40 +40 V pulse 1 -100 - V pulse 2a - +75 V pulse 3a -150 - V - +100 V -8 +8 kV on pins VBAT, WAKE, CANH, CANL [6] pulse 3b VESD V [4] VBAT+0.3 output current on pin INH transient voltage +40 −0.3 V(CANH-CANL) voltage between pin CANH and pin CANL Vtrt V [3] pin INH pins RXD, ERR_N IO(INH) +7 [2] IEC 61000-4-2 (150 pF, 330 Ω discharge circuit) [7] on pins CANH, CANL; pin VBAT with 100 nF capacitor; pin WAKE with 33 kΩ resistor Human Body Model (HBM) on any pin [8] -4 +4 kV on pins CANH, CANL [9] -8 +8 kV -750 +750 V Charged Device Model (CDM) [10] on corner pins on any other pin Tvj Tstg -500 +500 V virtual junction temperature [11] -40 +175 °C storage temperature [12] -55 +150 °C [1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients) never exceed these values. [2] The device can withstand voltages between 6 V and 7 V for a total of 20 s over the product lifetime. [3] For a maximum of 50 hours over the product lifetime. [4] Absolute maximum of 40 V under the conditions defined in Table note 3 above. [5] Subject to the qualifications detailed in Table notes 1 and 2 above for pins VCC, VIO, TXD, STB_N and EN. [6] Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO 7637, Part 2. [7] Verified by an external test house according to IEC TS 62228, Section 4.3. [8] According to AEC-Q100-002. [9] Pins stressed to reference group containing all ground and supply pins, emulating the application circuits (Figure 10). HBM pulse as specified in AECQ100-002 used. [10] According to AEC-Q100-011. [11] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [12] Tstg in application according to IEC61360-4. For component transport and storage conditions, see instead IEC61760-2. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 16 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 9 Thermal characteristics Table 7. Thermal characteristics Value determined for free convection conditions on a JEDEC 2S2P board. Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient [2] [1] Typ Unit SO14 83 K/W HVSON14 54 K/W Rth(j-c) thermal resistance from junction to case HVSON14 21 K/W Ѱj-top thermal characterization parameter from junction to top of package SO14 19 K/W HVSON14 11 K/W [1] [2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 μm). Case temperature refers to the center of the heatsink at the bottom of the package. 10 Static characteristics Table 8. Static characteristics Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V; VBAT = 4.5 V to 28 V; RL = 60 Ω unless specified [1] otherwise; all voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V 4 - 4.5 V 50 - - mV dominant; VTXD = 0 V; t < tto(dom)TXD - 38 60 mA dominant; VTXD = 0 V; short circuit on bus lines; -3 V < (VCANH = VCANL) < +40 V - - 125 mA Normal mode, recessive; VTXD = VIO - 4 7 mA Listen-only mode - 3 5 mA Standby or Sleep mode; Tvj < 85 °C - - 2 µA 2.95 - 5.5 V 2.65 - 2.95 V 50 - - mV Normal mode, dominant; VTXD = 0 V - 90 250 µA Normal mode, recessive, VTXD = VIO or Listen-only mode - - 2 µA Supply; pin VCC VCC supply voltage Vuvd undervoltage detection voltage Vuvhys undervoltage hysteresis voltage ICC supply current [2] Normal mode I/O level adapter supply; pin VIO VIO supply voltage Vuvd undervoltage detection voltage Vuvhys undervoltage hysteresis voltage IIO supply current TJR1443 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 17 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 8. Static characteristics...continued Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V; VBAT = 4.5 V to 28 V; RL = 60 Ω unless specified [1] otherwise; all voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Standby or Sleep mode; Tvj < 85 °C - - 2 µA 4.5 - 28 V 4 - 4.5 V Normal or Listen-only mode; pin INH left open - 80 300 µA Normal or Listen-only mode; pin INH left open; Tvj ≤ 25 °C; VBAT = 14.5 V - 80 100 µA Standby mode; pin INH left open; VWAKE = VBAT; Tvj < 85 °C - 13 20 µA Sleep mode; VWAKE = VBAT; Tvj < 85 °C - 13 20 µA Supply; pin VBAT VBAT battery supply voltage Vuvd undervoltage detection voltage IBAT battery supply current [2] CAN transmit data input; pin TXD VIH HIGH-level input voltage 0.7VIO - - V VIL LOW-level input voltage - - 0.3VIO V Vhys(TXD) hysteresis voltage on pin TXD 50 - - mV Rpu pull-up resistance 20 - 80 kΩ - - 10 pF Ci [3] input capacitance CAN receive data output; pin RXD IOH HIGH-level output current VRXD = VIO - 0.4 V -10 - -1 mA IOL LOW-level output current VRXD = 0.4 V 1 - 10 mA Standby and enable control inputs; pins STB_N and EN VIH HIGH-level input voltage 0.7VIO - - V VIL LOW-level input voltage - - 0.3VIO V Vhys hysteresis voltage Rpd pull-down resistance [4] Ci input capacitance [3] 50 - - mV 20 - 80 kΩ - - 10 pF Local failure detection and power-on indication output; pin ERR_N IOH HIGH-level output current VERR_N = VIO - 0.4 V -50 - -4 µA IOL LOW-level output current VERR_N = 0.4 V 0.1 - 2 mA Local wake-up input; pin WAKE Rpu pull-up resistance VWAKE > Vth(wake)(max) for t > twake(max) 100 - 400 kΩ Rpd pull-down resistance VWAKE < Vth(wake)(min) for t > twake(max) 100 - 400 kΩ Vth(wake) wake-up threshold voltage Sleep or Standby mode 1.8 - 2.6 V Vhys hysteresis voltage 90 - - mV TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 18 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 8. Static characteristics...continued Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V; VBAT = 4.5 V to 28 V; RL = 60 Ω unless specified [1] otherwise; all voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit ΔVH = VBAT - VINH; IINH = -1 mA 0 - 1 V ΔVH = VBAT - VINH; IINH = -2 mA 0 - 2 V Inhibit output; pin INH ΔVH HIGH-level voltage drop IL leakage current Sleep mode; Off mode -2 - +2 µA IO(sc) short-circuit output current VINH = 0 V -15 - - mA 2.75 3.5 4.5 V 0.5 1.5 2.25 V 0.9VCC - 1.1VCC V -150 - +150 mV -300 - +300 mV 1.5 - 3 V 1.4 - 3.3 V 1.5 - 5 V Normal or Listen-only mode; VTXD = VIO -50 - +50 mV Standby or Sleep mode -0.2 - +0.2 V Normal or Listen-only mode; VTXD = VIO; no load 2 2.5 3 V Standby or Sleep mode; no load -0.1 0 +0.1 V Normal or Listen-only mode 0.5 - 0.9 V Standby or Sleep mode 0.4 - 1.1 V Normal or Listen-only mode -4 - +0.5 V Standby or Sleep mode -4 - +0.4 V Bus lines; pins CANH and CANL VO(dom) dominant output voltage VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V pin CANH; RL = 50 Ω to 65 Ω pin CANL; RL = 50 Ω to 65 Ω VTXsym transmitter voltage symmetry Vcm(step) common mode voltage step VTXsym = VCANH + VCANL; CSPLIT = 4.7 nF; fTXD = 250 kHz, 1 MHz or 2.5 MHz [3] [5] [3] [5] [6] Vcm(p-p) VO(dif) [3] peak-to-peak common mode voltage differential output voltage [5] [6] dominant; Normal mode; VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V [5] RL = 50 Ω to 65 Ω RL = 45 Ω to 70 Ω RL = 2240 Ω [3] recessive; no load VO(rec) Vth(RX)dif Vrec(RX) Vdom(RX) recessive output voltage differential receiver threshold voltage receiver recessive voltage receiver dominant voltage TJR1443 Product data sheet -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 19 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 8. Static characteristics...continued Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V; VBAT = 4.5 V to 28 V; RL = 60 Ω unless specified [1] otherwise; all voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Normal or Listen-only mode 0.9 - 9 V Standby or Sleep mode 1.1 - 9 V Vhys(RX)dif differential receiver hysteresis voltage -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Normal or Listenonly mode 50 - - mV IO(sc) short-circuit output current -15 V ≤ VCANH ≤ +40 V; -15 V ≤ VCANL ≤ +40 V - - 115 mA IO(sc)rec recessive short-circuit output -27 V ≤ VCANH ≤ +32 V; current -27 V ≤ VCANL ≤ +32 V; Normal or Listenonly mode; VTXD = VIO -3 - +3 mA IL leakage current VCC = VIO = 0 V or pins shorted to GND via 47 KΩ; VCANH = VCANL = 5 V; -10 - +10 µA Ri input resistance -2 V ≤ VCANL ≤ +7 V; -2 V ≤ VCANH ≤ +7 V 25 40 50 kΩ ΔRi input resistance deviation 0 V ≤ VCANL ≤ +5 V; 0 V ≤ VCANH ≤ +5 V -3 - +3 % Ri(dif) differential input resistance -2 V ≤ VCANL ≤ +7 V; -2 V ≤ VCANH ≤ +7 V 50 80 100 kΩ - - 20 pF Ci(cm) common-mode input capacitance [3] Ci(dif) differential input capacitance [3] - - 10 pF Temperature detection Tj(sd) shutdown junction temperature [3] 180 - 200 °C Tj(sd)rel release shutdown junction temperature [3] 175 - 195 °C [1] [2] [3] [4] [5] [6] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. Undervoltage is detected between min and max values. Undervoltage is guaranteed to be detected below min value and guaranteed not to be detected above max value. Not tested in production; guaranteed by design. Pull-down on EN pin is only active when VBAT is present. The test circuit used to measure the bus output voltage symmetry and the common-mode voltages (which includes CSPLIT) is shown in Figure 12. See Figure 9. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 20 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 11 Dynamic characteristics Table 9. Dynamic characteristics Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V; VBAT = 4.5 V to 28 V; RL = 60 Ω unless specified [1] otherwise; all voltages are defined with respect to ground. Symbol Parameter Conditions Min Typ Max Unit CAN timing characteristics; tbit(TXD) ≥ 200 ns; see Figure 7, Figure 8 and Figure 11 td(TXD-busdom) delay time from TXD to bus dominant Normal mode - - 102.5 ns td(TXD-busrec) delay time from TXD to bus recessive Normal mode - - 102.5 ns td(busdom-RXD) delay time from bus dominant to RXD Normal or Listen-Only mode - - 127.5 ns td(busrec-RXD) delay time from bus recessive to RXD Normal or Listen-Only mode - - 127.5 ns td(TXDL-RXDL) delay time from TXD LOW to RXD LOW Normal mode - - 230 ns td(TXDH-RXDH) delay time from TXD HIGH to RXD HIGH Normal mode - - 230 ns tbit(TXD) = 500 ns 435 - 530 ns tbit(TXD) = 200 ns 155 - 210 ns tbit(TXD) = 500 ns -65 - +40 ns tbit(TXD) = 200 ns -45 - +15 ns tbit(TXD) = 500 ns 400 - 550 ns tbit(TXD) = 200 ns 120 - 220 ns 0.8 - 9 ms 0.8 - 9 ms 0.5 - 1.8 µs 0.5 - 1.8 µs 0.8 - 9 ms CAN FD timing characteristics according to ISO 11898-2:2016; see Figure 8 and Figure 11 tbit(bus) Δtrec tbit(RXD) transmitted recessive bit width receiver timing symmetry bit time on pin RXD Dominant time-out times tto(dom)TXD TXD dominant time-out time VTXD = 0 V; Normal mode [2] tto(dom)bus bus dominant time-out time VO(dif) > 0.9 V; Normal or ListenOnly mode [2] [3] [3] Bus wake-up times; pins CANH and CANL; see Figure 6 twake(busdom) bus dominant wake-up time Standby or Sleep mode [2] twake(busrec) bus recessive wake-up time Standby or Sleep mode [2] tto(wake)bus bus wake-up time-out time Standby or Sleep mode [2] [4] [4] [3] Mode transitions mode change transition time [2] - - 50 µs start-up time [2] - - 1 ms tstartup(RXD) RXD start-up time after local or remote wake-up detected [2] 4 - 20 µs tstartup(INH) INH start-up time after local or remote wake-up detected; transition from Sleep to Standby [2] 4 - 50 µs tt(moch) tstartup TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 [5] [6] © NXP B.V. 2021. All rights reserved. 21 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 9. Dynamic characteristics...continued Tvj = -40 °C to +175 °C; VCC = 4.5 V to 5.5 V; VIO = 2.95 V to 5.5 V; VBAT = 4.5 V to 28 V; RL = 60 Ω unless specified [1] otherwise; all voltages are defined with respect to ground. Symbol th(gotosleep) Parameter Conditions go-to-sleep hold time Min Typ Max Unit 24 - 50 µs [2] - - 20 µs [8] 20 - 50 µs [9] 1 - 5 µs on pin VBAT [2] - - 30 µs on pin VCC [2] - - 30 µs on pin VIO [2] - - 30 µs [2] 100 - 150 ms STB_N = LOW and EN = HIGH hold time for entering Sleep mode td(moch-ERR_N) delay time from mode change to ERR_N to ERR_N stable after mode transition [2] [7] Local wake-up input; pin WAKE twake wake-up time in response to a falling or rising edge on pin WAKE; Standby or Sleep mode IO filter; pins STB_N, EN tfltr(IO) I/O filter time Undervoltage detection; see Figure 3 and Figure 5 tdet(uv) undervoltage detection time tdet(uv)long long undervoltage detection time on pins VCC and/or VIO trec(uv) undervoltage recovery time on pin VCC [2] - - 50 µs on pin VIO [2] - - 50 µs [10] [1] All parameters are guaranteed over the junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. [2] Not tested in production; guaranteed by design. [3] Time-out occurs between the min and max values. Time-out is guaranteed not to occur below the min value; time-out is guaranteed to occur above the max value. [4] A dominant/recessive phase shorter than the min value is guaranteed not be seen as a dominant/recessive bit; a dominant/recessive phase longer than the max value is guaranteed to be seen as a dominant/recessive bit. [5] When a wake-up is detected, RXD start-up time is between the min and max values. RXD cannot be relied on below the min value; RXD can be relied on above the max value; see Figure 6. [6] INH switches HIGH between the min and max values after a wake-up had been detected. INH is guaranteed to be floating below the min value and guaranteed to be HIGH above the max value; see Figure 6. [7] The device is guaranteed to switch to Sleep mode when STB_N = LOW and EN = HIGH for longer than max value, and guaranteed not to switch to Sleep mode when less than the min value. [8] The device is guaranteed to wake up above 50 μs and guaranteed not to wake up below 20 μs. [9] Pulses shorter than the min value are guaranteed to be filtered out; pulses longer than the max value are guaranteed to be processed. [10] An undervoltage longer than the max value is guaranteed to force a transition to Sleep mode; an undervoltage shorter than the min value is guaranteed not to force a transition to Sleep mode. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 22 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode TXD HIGH 70 % 30 % LOW CANH CANL dominant 0.9 V VO(dif) 0.5 V recessive RXD HIGH 70 % 30 % LOW td(TXD-busdom) td(TXD-busrec) td(busdom-RXD) td(busrec-RXD) aaa-029311 Figure 7. CAN transceiver timing diagram 70 % TXD 30 % 30 % td(TXDL-RXDL) 5 x tbit(TXD) tbit(TXD) 0.9 V VO(dif) 0.5 V tbit(bus) 70 % RXD 30 % td(TXDH-RXDH) tbit(RXD) aaa-029312 Figure 8. CAN FD timing definitions according to ISO 11898-2:2016 TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 23 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode CANH CANL Vcm(step) VCANH + VCANL Vcm(p-p) aaa-037830 Figure 9. CAN bus common-mode voltage according to SAE 1939-14 12 Application information 12.1 Application diagram BAT 3.3 V (1) on/off control 5V (1) VBAT 10 INH 7 VCC 3 VIO 5 14 WAKE GND 6 9 8 4 2 13 1 12 CANH STB_N EN ERR_N RXD port w, x, y, z MICROCONTROLLER TXD CANL CAN bus wires aaa-038117 (1) Optional, depends on regulator. Figure 10. Typical TJR1443 application with a 3.3 V microcontroller 12.2 Application hints Further information on the application of the TJR1443 can be found in NXP application hints AH2002 'TJx144x/TJx146x Application Hints', available on request from NXP Semiconductors. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 24 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 13 Test information TXD CANH RL 60 Ω RXD CL 100 pF CANL 15 pF aaa-030850 Figure 11. CAN transceiver timing test circuit TXD CANH 30 Ω fTXD CSPLIT 4.7 nF RXD 30 Ω CANL aaa-030851 Figure 12. Test circuit for measuring transceiver driver symmetry 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 Rev-H - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 25 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 14 Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 13. Package outline SOT108-1 (SO14) TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 26 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode HVSON14: plastic, thermal enhanced very thin small outline package; no leads; 14 terminals; body 3 x 4.5 x 0.85 mm SOT1086-2 X B D A E A A1 c terminal 1 index area detail X e1 terminal 1 index area e v w b 1 7 C C A B C y1 C y L k Eh 14 8 Dh 0 2.5 scale Dimensions Unit mm 5 mm A A1 b max 1.00 0.05 0.35 nom 0.85 0.03 0.32 min 0.80 0.00 0.29 c D Dh E 0.2 4.6 4.5 4.4 4.25 4.20 4.15 3.1 3.0 2.9 Eh e e1 1.65 1.60 0.65 1.55 3.9 k L 0.35 0.45 0.30 0.40 0.25 0.35 v 0.1 w y 0.05 0.05 y1 0.1 sot1086-2 References Outline version IEC JEDEC JEITA SOT1086-2 --- MO-229 --- European projection Issue date 10-07-14 10-07-15 Figure 14. Package outline SOT1086-2 (HVSON14) TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 27 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 15 Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 16 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 28 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and Table 11 Table 10. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 11. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 29 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17 Soldering of HVSON packages Section 16 contains a brief introduction to the techniques most commonly used to solder Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON leadless package ICs can be found in the following application note: • AN10365 “Surface mount reflow soldering description” TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 30 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 18 Appendix: ISO 11898-2:2016 parameter cross-reference list Table 12. ISO 11898-2:2016 to NXP data sheet parameter conversion ISO 11898-2:2016 NXP data sheet Parameter Notation Symbol Parameter Single ended voltage on CAN_H VCAN_H VO(dom) dominant output voltage Single ended voltage on CAN_L VCAN_L Differential voltage on normal bus load VDiff VO(dif) differential output voltage VSYM VTXsym transmitter voltage symmetry Absolute current on CAN_H ICAN_H IO(sc) short-circuit output current Absolute current on CAN_L ICAN_L HS-PMA dominant output characteristics Differential voltage on effective resistance during arbitration Optional: Differential voltage on extended bus load range HS-PMA driver symmetry Driver symmetry Maximum HS-PMA driver output current HS-PMA recessive output characteristics, bus biasing active/inactive Single ended output voltage on CAN_H VCAN_H Single ended output voltage on CAN_L VCAN_L Differential output voltage VO(rec) recessive output voltage VDiff VO(dif) differential output voltage tdom tto(dom)TXD TXD dominant time-out time Optional HS-PMA transmit dominant time-out Transmit dominant time-out, long Transmit dominant time-out, short HS-PMA static receiver input characteristics, bus biasing active/inactive Recessive state differential input voltage range Dominant state differential input voltage range VDiff Vth(RX)dif differential receiver threshold voltage Vrec(RX) receiver recessive voltage Vdom(RX) receiver dominant voltage HS-PMA receiver input resistance (matching) Differential internal resistance RDiff Ri(dif) differential input resistance Single ended internal resistance RCAN_H RCAN_L Ri input resistance Matching of internal resistance MR ΔRi input resistance deviation tLoop td(TXDH-RXDH) delay time from TXD HIGH to RXD HIGH td(TXDL-RXDL) delay time from TXD LOW to RXD LOW HS-PMA implementation loop delay requirement Loop delay TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 31 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Table 12. ISO 11898-2:2016 to NXP data sheet parameter conversion...continued ISO 11898-2:2016 NXP data sheet Parameter Notation Symbol Parameter Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to 2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s, intended tBit(Bus) tbit(bus) transmitted recessive bit width Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s tBit(RXD) tbit(RXD) bit time on pin RXD Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s ΔtRec Δtrec receiver timing symmetry VDiff V(CANH-CANL) voltage between pin CANH and pin CANL Vx voltage on pin x HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff Maximum rating VDiff General maximum rating VCAN_H and VCAN_L VCAN_H Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered Leakage current on CAN_H, CAN_L ICAN_H ICAN_L IL leakage current tFilter twake(busdom) twake(busrec) bus dominant wake-up time bus recessive wake-up time tWake tto(wake)bus bus wake-up time-out time HS-PMA bus biasing control timings CAN activity filter time, long CAN activity filter time, short Wake-up time-out, short [1] Wake-up time-out, long [1] tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 32 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 19 Appendix: TJx144x/TJx146x/TJF1441 family overview Table 13. Feature overview of the complete TJx144x/TJx146x/TJF1441 family Data rate Additional features TXD dominant timeout [6] Single supply pin wake-up Short WUP support [0.5 - 1.8 µs] [4] Wake-up source recognition Signal improvement [3] [2] Up to 8 Mbit/s CAN FD Up to 5 Mbit/s CAN FD VBAT pin VIO pin ● ● ● ● ● ● ● ● ● ● TJx1441D ● ● ● ● ● TJF1441A ● ● [7] TJx1442A ● ● TJx1442B ● ● TJx1443A ● ● TJx1448A ● TJx1448B Sleep VCC pin Selectable Off Silent/Listen-only Standby ● TJx1441B [1] Normal TJx1441A Device ● ● ● ● ● ● ● ● ● ● ● ● ● ● TJx1448C ● ● ● ● ● TJx1462A ● ● ● ● ● ● TJx1462B ● ● ● ● ● TJx1463A ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● [1] [2] [3] [4] [5] [6] [7] ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Local diagnostics via ERR_N pin Supplies [5] Modes ● ● ● ● TJx: TJA14xxx is AEC-Q100 Grade 1; TJR14xxx is AEC-Q100 Grade 0; TJF1441A is non-automotive grade. Only guaranteed for TJA146x, AEC-Q100 Grade 1. CAN FD Signal Improvement Capability (SIC) according to CiA 601-4:2019. RXD is held LOW after wake-up request, enabling wake-up source recognition. WUP = wake-up pattern according ISO11898-2:2016. Only VIO supply needed for wake-up in TJA1442A, TJA1448A, TJA1448C, TJA1462A; only VBAT supply needed for wake-up in TJA1443A, TJA1463A. Not having TXD dominant timeout allows for very low data rates in non-automotive grade applications. TJR1443 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 33 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 20 Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes TJR1443 v.2 20211015 Product data sheet - TJR1443 v.1 Modifications • • • • TJR1443 v.1 20200907 TJR1443 Product data sheet Added device (Table 3) and family (Section 19) feature overviews Figure 3: text defining transition from Sleep to Standy revised Section 7.1.1.2: typo corrected - STBN_N changed to STB_N Table 6: table notes 3 and 4 revised; table note 12 added; measurement conditions and table note changed for parameter Vtrt • Table 9: measurement conditions for parameters tstartup(RXD) and tstartup(INH) revised; table note 8 added • Section 21: Suitability for use in Automotive applications and Security disclaimers revised Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 - © NXP B.V. 2021. All rights reserved. 34 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode 21 Legal information 21.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 21.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 21.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without TJR1443 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 35 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 21.4 Trademarks Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Security — Customer understands that all NXP products may be subject to unidentified or documented vulnerabilities. Customer is responsible TJR1443 Product data sheet Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2021 © NXP B.V. 2021. All rights reserved. 36 / 37 TJR1443 NXP Semiconductors High-speed CAN transceiver with Sleep mode Contents 1 2 2.1 2.2 2.3 2.4 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.1.1 7.1.1.2 7.1.1.3 7.1.1.4 7.1.1.5 7.1.1.6 7.1.2 7.1.2.1 7.1.2.2 7.1.2.3 7.1.2.4 7.1.2.5 7.1.2.6 7.2 7.2.1 7.2.2 7.2.2.1 7.2.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.5 7.6 8 9 10 11 12 12.1 12.2 13 General description ............................................ 1 Features and benefits .........................................1 General .............................................................. 1 Predictable and fail-safe behavior ..................... 1 Low-power management ................................... 2 Diagnosis & Protection ...................................... 2 Quick reference data .......................................... 3 Ordering information .......................................... 3 Block diagram ..................................................... 5 Pinning information ............................................ 6 Pinning ............................................................... 6 Pin description ................................................... 6 Functional description ........................................7 Operating modes ............................................... 7 System operating modes ...................................7 Off mode ............................................................7 Standby mode ................................................... 8 Normal mode ..................................................... 8 Listen-only mode ............................................... 8 Sleep mode ....................................................... 8 System operating modes and gap-free operation ............................................................ 9 CAN operating modes ..................................... 10 CAN Off mode ................................................. 10 CAN Offline mode ........................................... 10 CAN Wake mode .............................................11 CAN Pass-through mode .................................11 CAN Active mode ............................................ 11 CAN Listen-only mode .....................................11 Internal flags .................................................... 11 Pwon flag .........................................................12 Wake flag .........................................................12 Local wake-up (via WAKE pin) ........................ 12 Remote wake-up (via the CAN bus) ................ 12 Wake-up source flag ........................................13 Local failure flag .............................................. 13 Local failure events ......................................... 14 TXD dominant failures ..................................... 14 TXD-to-RXD short circuit ................................. 14 Bus dominant failures ...................................... 14 Overtemperature ..............................................14 I/O levels ..........................................................14 WAKE pin ........................................................ 15 Internal biasing of TXD, STB_N and EN input pins ......................................................... 15 Limiting values .................................................. 16 Thermal characteristics ....................................17 Static characteristics ........................................ 17 Dynamic characteristics ...................................21 Application information .................................... 24 Application diagram ......................................... 24 Application hints .............................................. 24 Test information ................................................ 25 13.1 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 21 Quality information ...........................................25 Package outline .................................................26 Handling information ........................................ 28 Soldering of SMD packages .............................28 Introduction to soldering ............................. Wave and reflow soldering ......................... Wave soldering ........................................... Reflow soldering ......................................... Soldering of HVSON packages ........................ 30 Appendix: ISO 11898-2:2016 parameter cross-reference list ........................................... 31 Appendix: TJx144x/TJx146x/TJF1441 family overview ................................................. 33 Revision history ................................................ 34 Legal information .............................................. 35 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 October 2021 Document identifier: TJR1443