TZA3012HW

TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Rev. 01 — 15 December 2005 Product data sheet 1. General description The TZA3012HW is a fully integrated optical network receiver containing a dual limiter, data and clock recovery and demultiplexer with demultiplexing ratios of 1 : 16, 1 : 10, 1 : 8, or 1 : 4. The A-rate feature allows the IC to operate at any bit rate between 30 Mbit/s and 3.2 Gbit/s using a single reference frequency. The receiver supports loop modes with serial clock and data inputs and outputs. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution giving a true, continuous rate operation. For full configuration flexibility, the receiver can be configured by pin or via the I2C-bus. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 2. Features 2.1 General s Single 3.3 V supply voltage s I2C-bus and pin configured fiber-optic receiver 2.2 Dual limiter s s s s Dual limiting input with 12 mV sensitivity Received Signal Strength Indicator (RSSI) Loss-Of-Signal (LOS) indicator with threshold adjust Differential overvoltage protection 2.3 Data and clock recovery s Supports SHD/SONET bit rates at 155.52 Mbit/s, 622.08 Mbit/s, 2488.32 Mbit/s and 2666.06 Mbit/s (STM16/OC48 + FEC) s Supports Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s s Supports Fiber Channel at 1062.5 Mbit/s and 2125 Mbit/s s ITU-T compliant jitter tolerance s Frequency lock indicator s Stable clock signal when input data absent s Outputs for recovered data and clock loop mode Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 2.4 Demultiplexer s Demultiplexing ratios of 1 : 16, 1 : 10, 1 : 8 or 1 : 4 s Low Voltage Positive Emitter Coupled Logic (LVPECL) or Common Mode Logic (CML) demultiplexer outputs s Parity bit generation s Loop mode inputs to demultiplexer 2.5 Additional features with I2C-bus s s s s s s s s s s A-rate supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one reference frequency Programmable frequency resolution of 10 Hz Four reference frequency ranges Adjustable swing of data, clock and parallel outputs Programmable polarity of all RF I/Os Exchangeable pin designations of RF clock with data for all I/Os for optimum connectivity Reversible pin designations of parallel data bus bits for optimum connectivity Slice level adjustment to improve Bit Error Rate (BER) Mute function for a forced logic 0 output state Programmable parity 3. Applications s s s s Any optical transmission system with bit rates between 30 Mbit/s and 3.2 Gbit/s Physical interface IC in receive channels Transponder applications Dense Wavelength Division Multiplexing (DWDM) systems 4. Ordering information Table 1: Ordering information Package Name TZA3012HW HTQFP100 Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 × 14 × 1 mm; exposed die pad Version SOT638-1 Type number TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 2 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 5. Block diagram CLOOP DLOOPQ CLOOPQ RSSI1 7 6 LOS1 5 DLOOP 87 ENLINQ 88 84 85 91 30 31 DMXR0 DMXR1 LOSTH1 38 39 44, 46, 48, 53 55, 57, 59, 61, 64, 66, 68, 70 72, 77, 79, 81 PARITY PARITYQ LOS RSSI INSEL IN1 IN1Q 12 9 10 LIM TZA3012HW c d DMX 1 : 4 16 1:8 1 : 10 1 : 16 PARITY GENERATOR AND BUS SWAP 16 D00 to D15 SWITCH 16 IN2 17 IN2Q LPF RSSI LOS LOSTH2 SCL(DR2) SDA(DR1) CS(DR0) UI i.c. 2 19 24 23 22 4 28, 29 14 8, 11, 15, 18 4 VCCA 20 RSSI2 21 LOS2 WINSIZE I2C-BUS LIM PHASE 2 DETECTOR 2 2 2 d c 16 45, 47, 49, 54 56, 58, 60, 62, 65, 67, 69, 71 73, 78, 80, 82 D00Q to D15Q POCLK POCLKQ COUT COUTQ DOUT DOUTQ INT 41 42 94 95 FREQUENCY WINDOW DETECTOR 97 98 INTERRUPT CONTROLLER 92 36, 37 1, 35, 40, 43, 51 75, 76, 83, 86, 89, 93, 96, 99 32 13 VDD VCCD ENLOUTQ VCCO VEE n.c. RREF 13 33 34 27 2 CREFQ CREF 3 90 25 26, 50, 52, 63, 74, 100 001aad377 PRSCLOQ PRSCLO INWINDOW LIM = Limiting amplifier RSSI = Received signal strength indicator LOS = Loss-of-signal detector LPF = Low-pass filter DMX = Demultiplexer Fig 1. Block diagram TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 3 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 6. Pinning information 6.1 Pinning 90 ENLOUTQ 88 DLOOPQ 85 CLOOPQ 91 ENLINQ 98 DOUTQ 95 COUTQ 87 DLOOP 84 CLOOP 97 DOUT 94 COUT 80 D14Q 78 D13Q 82 D15Q 99 VCCD 96 VCCD 93 VCCD 89 VCCD 86 VCCD 83 VCCD 100 VEE VCCD PRSCLO PRSCLOQ UI LOS1 RSSI1 LOSTH1 VCCA IN1 1 2 3 4 5 6 7 8 9 76 VCCD 75 VCCD 74 VEE 73 D12Q 72 D12 71 D11Q 70 D11 69 D10Q 68 D10 67 D09Q 66 D09 65 D08Q 64 D08 63 VEE 62 D07Q 61 D07 60 D06Q 59 D06 58 D05Q 57 D05 56 D04Q 55 D04 54 D03Q 53 D03 52 VEE 51 VCCD VEE 50 001aad378 81 D15 79 D14 D01Q 47 INQ1 10 VCCA 11 INSEL 12 WINSIZE 13 RREF 14 VCCA 15 IN2 16 IN2Q 17 VCCA 18 LOSTH2 19 RSSI2 20 LOS2 21 CS/DR0 22 SDA/DR1 23 SCL/DR2 24 VDD 25 VEE 26 INWINDOW 27 i.c. 28 i.c. 29 DMXR0 30 DMXR1 31 VCCO 32 CREF 33 CREFQ 34 VCCD 35 n.c. 36 n.c. 37 PARITY 38 PARITYQ 39 VCCD 40 POCLK 41 POCLKQ 42 VCCD 43 D00 44 D00Q 45 D01 46 D02 48 D02Q 49 TZA3012HW Fig 2. Pin configuration TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 77 D13 92 INT 4 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 6.2 Pin description Table 2: Symbol VCCD PRSCLO PRSCLOQ UI LOS1 RSSI1 LOSTH1 VCCA IN1 IN1Q VCCA INSEL WINSIZE RREF VCCA IN2 IN2Q VCCA LOSTH2 RSSI2 LOS2 CS/DR0 SDA/DR1 SCL/DR2 VDD VEE INWINDOW i.c. i.c. DMXR0 DMXR1 VCCO CREF CREFQ VCCD n.c. n.c. PARITY PARITYQ TZA3012HW_1 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Description supply voltage (digital signal part) prescaler output prescaler inverted output user interface select input first input channel loss-of-signal output first input channel received signal strength indicator output first input channel loss-of-signal threshold input supply voltage (analog part) first channel input first channel inverted input supply voltage (analog part) input selector wide and narrow frequency detect window select input reference resistor input supply voltage (analog part) second channel input second channel inverted input supply voltage (analog part) second input channel loss-of-signal threshold input second input channel received signal strength indicator output second input channel loss-of-signal output chip select input or data rate select input 2 I2C-bus serial data input and output or data rate select input 1 I2C-bus serial clock input or data rate select input 2 supply voltage (digital controller part) ground frequency window detector output internally connected; leave open internally connected; leave open demultiplexing ratio select 0 demultiplexing ratio select 1 supply voltage (clock generator part) reference clock input reference clock inverted input supply voltage (digital signal part) not connected not connected parity output parity inverted output © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 5 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Pin description …continued Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Description supply voltage (digital signal part) parallel clock output parallel clock inverted output supply voltage (digital signal part) parallel data 00 output parallel data 00 inverted output parallel data 01 output parallel data 01 inverted output parallel data 02 output parallel data 02 inverted output ground supply voltage (digital signal part) ground parallel data 03 output parallel data 03 inverted output parallel data 04 output parallel data 04 inverted output parallel data 05 output parallel data 05 inverted output parallel data 06 output parallel data 06 inverted output parallel data 07 output parallel data 07 inverted output ground parallel data 08 output parallel data 08 inverted output parallel data 09 output parallel data 09 inverted output parallel data 10 output parallel data 10 inverted output parallel data 11 output parallel data 11 inverted output parallel data 12 output parallel data 12 inverted output ground supply voltage (digital signal part) supply voltage (digital signal part) parallel data 13 output parallel data 13 inverted output parallel data 14 output parallel data 14 inverted output © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Table 2: Symbol VCCD POCLK POCLKQ VCCD D00 D00Q D01 D01Q D02 D02Q VEE VCCD VEE D03 D03Q D04 D04Q D05 D05Q D06 D06Q D07 D07Q VEE D08 D08Q D09 D09Q D10 D10Q D11 D11Q D12 D12Q VEE VCCD VCCD D13 D13Q D14 D14Q TZA3012HW_1 Product data sheet Rev. 01 — 15 December 2005 6 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Pin description …continued Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Description parallel data 15 output parallel data 15 inverted output supply voltage (digital signal part) loop mode clock input loop mode clock inverted input supply voltage (digital signal part) loop mode data input loop mode data inverted input supply voltage (digital signal part) line loop back enable input (active LOW) diagnostic loop back enable input (active LOW) interrupt output supply voltage (digital signal part) recovered clock output recovered clock inverted output supply voltage (digital signal part) recovered data output recovered data inverted output supply voltage (digital signal part) ground Table 2: Symbol D15 D15Q VCCD CLOOP CLOOPQ VCCD DLOOP DLOOPQ VCCD ENLOUTQ ENLINQ INT VCCD COUT COUTQ VCCD DOUT DOUTQ VCCD VEE VEE die pad common ground plane TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 7 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 7. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCA VCCD VCCO VDD Vn Parameter analog supply voltage digital supply voltage oscillator supply voltage supply voltage voltage on pin n D00 to D15, D00Q to D15Q, POCLK, POCLKQ, PARITY, PARITYQ, PRSCLO and PRSCLOQ LOSTH1, LOSTH2 and RREF RSSI1 and RSSI2 UI, INSEL, WINSIZE, CS, SDA, SCL, DMXR0, DMXR1, ENLOUTQ and ENLINQ LOS1, LOS2 and INWINDOW INT II(n) input current on pin n IN1, IN1Q, IN2 and IN2Q CREF, CREFQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ INT Tamb Tj Tstg ambient temperature junction temperature storage temperature −30 −20 −2 −40 −65 +30 +20 +2 +85 +125 +150 mA mA mA °C °C °C VCC − 2.5 VCC + 0.5 V Conditions Min −0.5 −0.5 −0.5 −0.5 Max +3.6 +3.6 +3.6 +3.6 Unit V V V V −0.5 −0.5 −0.5 VCC + 0.5 V VCC + 0.5 V VCC + 0.5 V −0.5 −0.5 VCC + 0.5 V VCC + 0.5 V 8. Thermal characteristics Table 4: Symbol Rth(j-a) [1] [2] Thermal characteristics Parameter thermal resistance from junction to ambient Conditions [1] [2] Typ 16 Unit K/W In compliance with JEDEC standards JESD 51-5 and JESD 51-7. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 8 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 9. Characteristics Table 5: Default measurement settings All measurements are done with the default settings. Parameter Pin configured mode STM16/OC48 Limiter 1 active Detect window 1000 ppm Disabled DOUT and COUT Disabled DLOOP and CLOOP DMX ratio = 1 : 16 Reference frequency LOS2 switched off D00 to D15 and D00Q to D15Q PARITY, PARITYQ POCLK, POCLKQ PRSCLO and PRSCLOQ Pin UI = LOW DR0 = LOW, DR1 = HIGH, DR2 = LOW INSEL = HIGH WINSIZE = HIGH ENLOUTQ = HIGH ENLINQ = HIGH DMXR0 = HIGH, DMXR1 = HIGH CREF and CREFQ = 19.44 MHz LOSTH2 = not connected not connected not connected not connected not connected Table 6: Supply characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol VCC ICCA ICCD ICCO ICC(tot) VDD IDD General Ptot Vref [1] Parameter supply voltage analog supply current digital supply current oscillator supply current total supply current supply voltage supply current total power dissipation reference voltage Conditions Min 3.14 15 270 20 [1] Typ 3.30 20 350 25 395 3.30 0 1.3 1.21 Max 3.47 27 450 33 511 3.47 1 1.77 1.26 Unit V mA mA mA mA V mA W V Supplies: pins VCCA, VCCD, VCCO 305 3.14 0 Digital controller: pins VDD [1] 0.96 1.17 Reference: pin RREF 10 kΩ to 20 kΩ to VEE The total supply current and power dissipation are dependent on the IC setups such as swing and loop modes and termination conditions. TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 9 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 7: Logic control input and output characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol VIL VIH IIL IIH VOL VOH Parameter LOW-state input voltage HIGH-state input voltage LOW-state input current HIGH-state input current LOW-state output voltage HIGH-state output voltage VIL = 0 V VIH = VCC IOL = 1 mA IOH = −0.5 mA Conditions Min −200 0 VCC − 0.2 0 Typ Max Unit CMOS input: pins UI, DR0, DR1, DR2, INSEL, WINSIZE, DMXR0, DMXR1, ENLOUTQ and ENLINQ 0.2VCC V 10 0.2 VCC V µA µA V V 0.8VCC - CMOS output: INWINDOW and INT Open-drain output: pin INT VOL IOH LOW-state output voltage HIGH-state output current IOL = 1 mA VOH = VCC 0.2 10 V µA Table 8: RF input, RSSI and LOS characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Vi(p-p) Vsl(lower) Vsl(upper) Zi Parameter peak-to-peak input voltage lower slice level voltage upper slice level voltage input impedance differential Conditions single-ended [1] [2] [2] Min 12 80 - Typ −50 +50 100 60 17 680 - Max 500 120 20 780 +50 Unit mV mV mV Ω dB mV/dB mV mV RF input: pins IN1, INQ1, IN2 and INQ2 αisol(ch-ch) isolation between channels RSSI circuit Vi(sens) VO ∆VO input sensitivity voltage output voltage output voltage variation Vi = 5 mV to 500 mV (p-p) Vi = 32 mV (p-p); PRBS = (231 − 1) input 30 Mbit/s to 3200 Mbit/s; PRBS = (231 − 1); VCC = 3.14 V to 3.47 V; ∆Tamb = 120 °C 15 580 −50 Output: pins RSSI1 and RSSI2 IO(source) IO(sink) Zo LOS circuit Vhys(i) tas tdas output source current output sink current output impedance - 1 1 0.4 10 mA mA Ω LOS detector input hysteresis voltage assert time de-assert time ∆Vi(p-p) = 3 dB ∆Vi(p-p) = 3 dB [3] - 3 - 5 5 dB µs µs TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 10 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 8: RF input, RSSI and LOS characteristics …continued VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol VOL VOH Parameter LOW-state output voltage HIGH-state output voltage Conditions IOL = 1 mA IOH = −0.5 mA Min 0 VCC − 0.2 Typ Max 0.2 VCC Unit V V CMOS output: pins LOS1 and LOS2 [1] [2] [3] The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. It is assumed that both inputs carry a complementary signal of the specified peak-to-peak value. The slice level is adjustable in 256 steps controlled by I2C-bus registers LIMSLICE1 (address C0h) and LIMSLICE2 (address C1h). The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I2C-bus registers LIMLOS1CNF (address BDh) and LIMLOS2CNF (address BFh). Table 9: Clock and PLL characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Vi(p-p) VI Zi fi(ref) ∆fi(ref) tacq tacq(pc) tacq(oc) TDRmax Parameter peak-to-peak input voltage input voltage input impedance reference input frequency reference input frequency accuracy acquisition time power cycle acquisition time octave change acquisition time maximum transitionless data run single-ended to VCC R = 1, 2, 4 or 8 SDH/SONET requirement 30 Mbit/s 30 Mbit/s 30 Mbit/s 30 Mbit/s Conditions single-ended Min 50 VCC − 1 40 18R −20 Typ 50 19.4R 1000 Max 1000 VCC + 0.25 60 21R +20 200 10 10 Unit mV V Ω MHz ppm µs ms µs bit Reference input frequency: pins CREF and CREFQ PLL characteristics Table 10: Serial input and output characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Vi(p-p) VI Zi td Parameter peak-to-peak input voltage input voltage input impedance delay time single-ended to VCC data DLOOP and DLOOPQ to clock CLOOP and CLOOPQ; between differential crossovers referenced to negative clock edge see Figure 3 see Figure 3 clock CLOOP and CLOOPQ; between differential crossovers Conditions single-ended Min 50 40 260 Typ 50 340 Max 100 60 400 Unit mV Ω ps Serial input: pins CLOOP, CLOOPQ, DLOOP and DLOOPQ VCC − 1 VCC + 0.25 V tsu th δclk setup time hold time clock duty cycle 15 15 40 30 30 50 60 60 60 ps ps % TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 11 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 10: Serial input and output characteristics …continued VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Vo(p-p) Zo tr tf td Parameter peak-to-peak output voltage output impedance rise time fall time delay time Conditions single-ended with 50 Ω external load; ENLOUTQ = LOW single-ended to VCC 20 % to 80 % 80 % to 20 % data DOUT and DOUTQ to clock COUT and COUTQ; between differential crossovers referenced to negative clock edge COUT and COUTQ; between differential crossovers [1] Min 50 80 80 Typ 80 100 100 100 140 Max 110 120 200 Unit mV Ω ps ps ps Serial output: pins COUT, COUTQ, DOUT and DOUTQ δclk clock duty cycle 40 50 60 % [1] The output swing is adjustable in 16 steps controlled by bits RFS in I2C-bus register CBh. CLOOP td tsu th DLOOP mbl554 The timing is measured from the crossover point of the clock input signal to the crossover point of the data input. Fig 3. Loop mode input timing Table 11: Parallel outputs characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter CML mode Vo(p-p) peak-to-peak output voltage single-ended with 50 Ω external load to VCC; AC-coupled or DC-coupled single-ended to VCC 20 % to 80 % 80 % to 20 % [1] Conditions Min Typ Max Unit Parallel output: pins D00 to D15, D00Q to D15Q, PARITY, PARITYQ, POCLK, POCLKQ, PRSCLO and PRSCLOQ 650 800 1000 mV Zo tr tf fbit(par) VOH VOL TZA3012HW_1 output impedance rise time fall time parallel bit rate HIGH-state output voltage LOW-state output voltage 70 200 200 - 95 250 250 - 110 350 350 400 Ω ps ps Mbit/s LVPECL mode 50 Ω termination to VCC − 2 V 50 Ω termination to VCC − 2 V VCC − 1.2 VCC − 1.0 VCC − 0.9 V VCC − 2.0 VCC − 1.9 VCC − 1.7 V © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 12 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver Table 11: Parallel outputs characteristics …continued VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter Vo(p-p) peak-to-peak output voltage Conditions LVPECL floating; single-ended with 50 Ω external load to VCC; AC-coupled or DC-coupled 20 % to 80 % 80 % to 20 % [1] Min 700 Typ 900 Max 1150 Unit mV tr tf fbit(par) Timing td rise time fall time parallel bit rate delay time data D00 to D15 to clock POCLK data D06 to D09 to clock POCLK 300 300 - 350 350 - 400 400 400 ps ps Mbit/s referenced to negative clock edge DMX = 1 : 16, 1 : 10, 1 : 8 DMX = 1 : 4 POCLK and POCLKQ; between differential crossovers between channels DMX = 1 : 16, 1 : 10, 1 : 8 DMX = 1 : 4 [2] −100 150 40 [2] +100 180 50 +250 250 60 ps ps % δclk tsk(o) clock duty cycle output skew time data D00 to data Dn data D06 to D09 to clock POCLK - - 200 50 ps ps [1] [2] The output swing is adjustable in 16 steps controlled by bits MFS in I2C-bus register IOCNF3 (address C8h). In standard LVPECL mode only swing = 12 (default) should be used. With 50 % duty cycle. Table 12: Jitter tolerance characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol Parameter tjit(tol)(p-p) peak-to-peak jitter tolerance Conditions ITU-T G.958; PRBS = (231 − 1) STM1/OC3 mode f = 6.5 kHz f = 65 kHz f = 1 MHz STM4/OC12 mode f = 25 kHz f = 250 kHz f = 5 MHz STM16/OC48 mode f = 100 kHz f = 1 MHz f = 20 MHz [1] The peak-to-peak jitter tolerance is expressed as a ratio of the Unit Interval (UI): [4] [3] [1] [2] Min Typ Max Unit 3 0.3 0.3 3 0.3 0.3 3 0.3 0.3 10 1.0 0.5 10 1.0 0.5 10 1.0 0.5 - UI ( max ) – UI ( min ) t jit ( tol ) ( p – p ) = -------------------------------------------------UI ( nom ) [2] The minimum value of the peak-to-peak jitter tolerance is 0.25 for Tamb = −40 °C to 0 °C at f = 65 kHz and 1 MHz. © Koninklijke Philips Electronics N.V. 2005. All rights reserved. TZA3012HW_1 Product data sheet Rev. 01 — 15 December 2005 13 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver [3] [4] The minimum value of the peak-to-peak jitter tolerance is 0.25 for Tamb = −40 °C to 0 °C at f = 250 kHz and 5 MHz. The minimum value of the peak-to-peak jitter tolerance is 0.25 for Tamb = −40 °C to 0 °C at f = 1 MHz and 20 MHz. Table 13: I2C-bus characteristics VCC = 3.14 V to 3.47 V; Tamb = −40 °C to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings; all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. Symbol VIL VIH Vhys VOL1 Ii Ci Cb VnL VnH fSCL tLOW tHD;STA tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tr tf tBUF tSP Parameter LOW level input voltage HIGH level input voltage hysteresis of Schmitt trigger inputs LOW level output voltage input current each I/O pin capacitance for each I/O pin capacitive load for each bus line noise margin at the LOW-level noise margin at the HIGH-level SCL clock frequency LOW period of the SCL clock hold time (repeated) START condition HIGH period of the SCL clock set-up time for a repeated START condition data hold time data set-up time setup time for STOP condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals bus free time between a STOP and START condition pulse width of spikes that must be suppressed by the input filter SDA open-drain; IOL = 3 mA Conditions Min 0.8VCC 0 −10 0.1VCC 0.2VCC 1.3 0.6 0.6 0.6 0 100 0.6 20 20 1.3 0 Typ Max Unit DC characteristics: pins SCL and SDA 0.2VCC V 0.4 +10 10 400 100 0.9 300 300 50 V V V µA pF pF V V kHz µs µs µs µs µs ns µs ns ns µs ns 0.05VCC - Timing (standard mode): pins SCL and SDA SDA tf tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF SCL tHD;STA S tSU;STA Sr tSU;STO tHD;DAT tHIGH P S msc610 Fig 4. I2C-bus timing TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 14 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 10. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 c y exposed die pad side X Dh 75 76 51 50 ZE A e E HE wM bp pin 1 index θ Lp L detail X Eh A A2 A1 (A3) 100 1 wM ZD 25 bp D HD 26 e vM A B vM B 0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD 10 mm HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 ZD(1) ZE(1) 1.15 0.85 1.15 0.85 θ 7° 0° 16.15 16.15 15.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 03-04-07 05-02-02 Fig 5. Package outline SOT638-1 (HTQFP100) TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 15 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 11. Revision history Table 14: Revision history Release date 20051215 Data sheet status Product data sheet Change notice Doc. number Supersedes Document ID TZA3012HW_1 TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 16 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 12. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 13. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 15. Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. A-Rate — is a trademark of Koninklijke Philips Electronics N.V. 14. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 16. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com TZA3012HW_1 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 15 December 2005 17 of 18 Philips Semiconductors TZA3012HW 30 Mbit/s up to 3.2 Gbit/s A-Rate fiber-optic receiver 17. Contents 1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Dual limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Data and clock recovery . . . . . . . . . . . . . . . . . . 1 Demultiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Additional features with I2C-bus . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 15 December 2005 Document number: TZA3012HW_1 Published in The Netherlands