UBA2033

INTEGRATED CIRCUITS DATA SHEET UBA2033 HF full bridge driver IC Product specification 2002 Oct 08 NXP Semiconductors Product specification HF full bridge driver IC FEATURES • Full bridge driver circuit • Integrated bootstrap diodes • Integrated high voltage level shift function • High voltage input for the internal supply voltage • 550 V maximum voltage • Bridge disable function • Input for start-up delay • Adjustable oscillator frequency • Predefined bridge position during start-up. APPLICATIONS • The UBA2033 can drive (via the MOSFETs) any kind of load in a full bridge configuration • The circuit is especially designed as a commutator for High Intensity Discharge (HID) lamps. ORDERING INFORMATION TYPE NUMBER UBA2033TS PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm GENERAL DESCRIPTION UBA2033 The UBA2033 is a high voltage monolithic integrated circuit made in the EZ-HV SOI process. The circuit is designed for driving the MOSFETs in a full bridge configuration. In addition, it features a disable function, an internal adjustable oscillator and an external drive function with a low-voltage level shifter for driving the bridge. To guarantee an accurate 50% duty factor, the oscillator signal can be passed through a divider before being fed to the output driver. VERSION SOT341-1 2002 Oct 08 2 NXP Semiconductors Product specification HF full bridge driver IC BLOCK DIAGRAM UBA2033 handbook, full pagewidth −LVS 1 EXTDR 2 +LVS 3 16 FSL GHL SHL FSR LOGIC SIGNAL GENERATOR HIGH VOLTAGE LEVEL SHIFTER HIGHER RIGHT DRIVER 28 26 GHR SHR GLR 6 HV HIGHER LEFT DRIVER 15 17 SGND 14 STABILIZER UVLO 27 9 VDD 13 RC OSCILLATOR 2 10 UBA2033TS LOWER RIGHT DRIVER 23 SU 12 BD 1.29 V bridge disable 11 DD LOGIC LOW VOLTAGE LEVEL SHIFTER LOWER LEFT DRIVER 4, 5, 7, 8, 18, 19, 22, 24, 25 n.c. 20 GLL 21 PGND MBL457 Fig.1 Block diagram. 2002 Oct 08 3 NXP Semiconductors Product specification HF full bridge driver IC PINNING SYMBOL −LVS EXTDR +LVS n.c. n.c. HV n.c. n.c. VDD SU DD BD RC SGND GHL FSL SHL n.c. n.c. GLL PGND n.c. GLR n.c. n.c. SHR FSR GHR PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION negative supply voltage (for logic input) oscillator signal input positive supply voltage (for logic input) not connected not connected high voltage supply input not connected not connected internal low voltage supply input signal for start-up delay divider disable input bridge disable control input RC input for internal oscillator signal ground gate of higher left output MOSFET floating supply voltage left source of higher left MOSFET not connected not connected gate of lower left output MOSFET power ground not connected gate of lower right output MOSFET not connected not connected source of higher right MOSFET floating supply voltage right gate of higher right output MOSFET DD 11 BD 12 RC 13 SGND 14 MBL458 UBA2033 handbook, halfpage −LVS 1 28 GHR 27 FSR 26 SHR 25 n.c. 24 n.c. 23 GLR 22 n.c. EXTDR 2 +LVS 3 n.c. 4 n.c. 5 HV 6 n.c. 7 UBA2033TS n.c. 8 VDD 9 SU 10 21 PGND 20 GLL 19 n.c. 18 n.c. 17 SHL 16 FSL 15 GHL Fig.2 Pin configuration. 2002 Oct 08 4 NXP Semiconductors Product specification HF full bridge driver IC FUNCTIONAL DESCRIPTION Supply voltage The UBA2033 is powered by a supply voltage applied to pin HV, for instance the supply voltage of the full bridge. The IC generates its own low supply voltage for the internal circuitry. Therefore an additional low voltage supply is not required. A capacitor has to be connected to pin VDD to obtain a ripple-free internal supply voltage. The circuit can also be powered by a low voltage supply directly applied to pin VDD. In this case pin HV should be connected to pin VDD or SGND. Start-up With an increasing supply voltage the IC enters the start-up state; the higher power transistors are kept off and the lower power transistors are switched on. During the start-up state the bootstrap capacitors are charged and the bridge output current is zero. The start-up state is defined until VDD = VDD(UVLO), where UVLO stands for Under Voltage Lock-out. The state of the outputs during the start-up phase is overruled by the bridge disable function. Release of the power drive At the moment the supply voltage on pin VDD or HV exceeds the level of release power drive, the output voltage of the bridge depends on the control signal on pin EXTDR (see Table 1). The bridge position after start-up, disable, or delayed start-up (via pin SU) depends on the status of the pins DD and EXTDR. If pin DD = LOW (divider enabled) the bridge will start in the pre-defined position: pin GLR and pin GHL = HIGH and pin GLL and pin GHR = LOW. If pin DD = HIGH (divider disabled) the bridge position will depend on the status of pin EXTDR. If the supply voltage on pin VDD or HV decreases and drops below the reset level of power drive the IC enters the start-up state again. Oscillation At the point where the supply voltage on pin HV crosses the level of release power drive, the bridge begins commutating between the following two defined states: • Higher left and lower right MOSFETs on, higher right and lower left MOSFETs off • Higher left and lower right MOSFETs off, higher right and lower left MOSFETs on. The oscillation can take place in three different modes: • Internal oscillator mode. UBA2033 In this mode the bridge commutating frequency is determined by the values of an external resistor (Rosc) and capacitor (Cosc). In this mode pin EXTDR must be connected to pin +LVS. To realize an accurate 50% duty factor, the internal divider should be used. The internal divider is enabled by connecting pin DD to SGND. Due to the presence of the divider the bridge frequency is half the oscillator frequency. The commutation of the bridge will take place at the falling edge of the signal on pin RC. To minimize the current consumption pins +LVS, −LVS and EXTDR can be connected together to either pin SGND or VDD. In this way the current source in the logic voltage supply circuit is shut off. • External oscillator mode without the internal divider. In the external oscillator mode the external source is connected to pin EXTDR and pin RC is short-circuited to pin SGND to disable the internal oscillator. If the internal divider is disabled (pin DD = VDD) the duty factor of the bridge output signal is determined by the external oscillator signal and the bridge frequency equals the external oscillator frequency. • External oscillator mode with the internal divider. The external oscillator mode can also be used with the internal divider function enabled (pin RC and pin DD = SGND). Due to the presence of the divider the bridge frequency is half the external oscillator frequency. The commutation of the bridge is triggered by the falling edge of the EXTDR signal with respect to V−LVS. The design equation for the bridge oscillator frequency is: 1 f bridge = -------------------------------------------------( k osc × R osc × C osc ) Non-overlap time The non-overlap time is the time between turning off the conducting pair of MOSFETs and turning on the next pair. The non-overlap time is internally fixed to a very small value, which allows an HID system to operate with a very small phase difference between load current and full bridge voltage (pins SHL and SHR). Especially when igniting an HID lamp via a LC resonance circuit, a small ‘dead time’ is essential. The high maximum operating frequency, together with a small ‘dead time’, also gives the opportunity to ignite the HID lamp at the third harmonic of the full bridge voltage, thereby reducing costs in the magnetic power components. 2002 Oct 08 5 NXP Semiconductors Product specification HF full bridge driver IC ’Dead time’ can be increased by adding a resistor (for slowly turning on the full bridge power FETs) and a diode (for quickly turning off the full bridge power FETs) in parallel, both in series with the gate drivers (see Fig.3). Divider function If pin DD = SGND, then the divider function is enabled/present. If the divider function is present there is no direct relation between the position of the bridge output and the status of pin EXTDR. Start-up delay Normally, the circuit starts oscillating as soon as pin VDD or HV reaches the level of release power drive. At this Table 1 Logic table; note 1 INPUTS BD HIGH LOW Oscillation state HIGH LOW LOW LOW SU X X X LOW HIGH HIGH DD X X X X HIGH LOW EXTDR X X X X HIGH LOW LOW LOW-to-HIGH HIGH HIGH-to-LOW Note 1. X = don’t care a) BD, SU and DD logic levels are with respect to SGND b) EXTDR logic levels are with respect to V−LVS c) GHL logic levels are with respect to SHL d) GHR logic levels are with respect to SHR e) GLL and GLR logic levels are with respect to PGND LOW HIGH GHL LOW LOW LOW LOW LOW HIGH HIGH OUTPUTS GHR LOW LOW LOW LOW HIGH LOW LOW UBA2033 moment the gate drive voltage is equal to the voltage on pin VDD for the low side transistors and VDD − 0.6 V for the high side transistors. If this voltage is too low for sufficient drive of the MOSFETs the release of the power drive can be delayed via pin SU. A simple RC filter (R between pins VDD and SU; C between pins SU and SGND) can be used to make a delay, or a control signal from a processor can be used. Bridge disable The bridge disable function can be used to switch off all the MOSFETs as soon as the voltage on pin BD exceeds the bridge disable voltage (1.29 V). The bridge disable function overrules all the other states. DEVICE STATUS Start-up state GLL LOW HIGH LOW HIGH HIGH LOW LOW GLR LOW HIGH LOW HIGH LOW HIGH HIGH HIGH LOW f) If pin DD = LOW the bridge enters the state (oscillation state and pin BD = LOW and pin SU = HIGH) in the pre-defined position pin GHL and pin GLR = HIGH and pin GLL and pin GHR = LOW. 2002 Oct 08 6 NXP Semiconductors Product specification HF full bridge driver IC UBA2033 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages are measured with respect to SGND; positive currents flow into the IC. SYMBOL VDD VHV VFSL VFSR VSHL VSHR VPGND V−LVS I−LVS V+LVS Vi(EXTDR) Vi(RC) Vi(SU) Vi(BD) Vi(DD) SR Tj Tamb Tstg Vesd PARAMETER supply voltage (low voltage) supply voltage (high voltage) floating supply voltage left floating supply voltage right source voltage for higher left MOSFETs source voltage for higher right MOSFETs power ground voltage negative supply voltage for logic input negative supply current for logic input pin EXTDR = HIGH positive supply voltage for logic input VHV = 0 V; DC value transient at t < 0.1 μs input voltage from external oscillator on pin EXTDR input voltage on pin RC input voltage on pin SU input voltage on pin BD input voltage on pin DD slew rate at output pins junction temperature ambient temperature storage temperature electrostatic discharge voltage on pins HV, +LVS, −LVS, EXTDR, FSL, GHL, SHL, SHR, GHR and FSR note 1 with respect to V−LVS DC value transient at t < 0.1 μs DC value transient at t < 0.1 μs DC value transient at t < 0.1 μs DC value transient at t < 0.1 μs repetitive VSHL = VSHR = 550 V VSHL = VSHR = 0 V VSHL = VSHR = 550 V VSHL = VSHR = 0 V with respect to PGND and SGND with respect to SGND; t < 1 μs with respect to PGND and SGND with respect to SGND; t < 1 μs with respect to SGND DC value transient at t < 0.1 μs CONDITIONS 0 0 0 0 0 0 0 −3 −14 −3 −14 0 −0.9 −1 0 0 0 0 0 0 0 0 0 0 0 0 −40 −40 −55 − MIN. MAX. 14 17 550 564 14 564 14 +550 − +550 − 5 +17 − 14 17 V+LVS VDD 17 VDD 17 VDD 17 VDD 17 4 +150 +150 +150 900 V V V V V V V V V V V V V mA V V V V V V V V V V V V/ns °C °C °C V UNIT Note 1. In accordance with the Human Body Model (HBM): equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. 2002 Oct 08 7 NXP Semiconductors Product specification HF full bridge driver IC THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 100 UBA2033 UNIT K/W QUALITY SPECIFICATION In accordance with “SNW-FQ-611D”. CHARACTERISTICS Tj = 25 °C; all voltages are measured with respect to SGND; positive currents flow into the IC; unless otherwise specified. SYMBOL High voltage IHV IFSL, IFSR high voltage supply current high voltage floating supply current t < 0.5 s and VHV = 550 V t < 0.5 s and VFSL = VFSR = 564 V 0 0 − − 30 30 μA μA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Start-up; powered via pin HV Ii(HV) VHV(rel) VHV(UVLO) VHV(hys) VDD HV input current level of release power drive voltage reset level of power drive voltage HV hysteresis voltage internal supply voltage VHV = 20 V VHV = 11 V; note 1 − 11 8.5 2.0 10.5 − 8.25 5.75 2.0 0.5 12.5 10 2.5 11.5 1.0 14 11.5 3.0 13.5 mA V V V V Start-up; powered via pin VDD Ii(DD) VDD(rel) VDD(UVLO) VDD(hys) Ron(H) Roff(H) Ron(L) Roff(L) Io(source) Io(sink) Vdiode tno VFSL 2002 Oct 08 VDD input current level of release power drive voltage reset level of power drive voltage hysteresis voltage VDD = 8.25 V; note 2 0.5 9.0 6.5 2.5 1.0 9.75 7.25 3.0 mA V V V Ω Ω Ω Ω mA mA V ns V Output stage higher MOSFETs on resistance higher MOSFETs off resistance lower MOSFETs on resistance lower MOSFETs off resistance output source current output sink current bootstrap diode voltage drop non-overlap time HS lockout voltage left 8 VFSR = VFSL = 12 V (with respect to SHR and SHL); Isource = 50 mA VFSR = VFSL = 12 V (with respect to SHR and SHL); Isink = 50 mA VDD = 12 V; Isource = 50 mA VDD = 12 V; Isink = 50 mA VDD = VFSL = VFSR = 12 V; VGHR = VGHL = VGLR = VGLL = 0 V 15 9 15 9 130 21 14 21 14 180 200 2.1 − 4.0 26 18 26 18 − − 2.5 250 5.0 150 VDD = VFSL = VFSR = 12 V; VGHR = VGHL = VGLR = VGLL = 12 V Idiode = 20 mA 1.7 − 3.0 NXP Semiconductors Product specification HF full bridge driver IC UBA2033 SYMBOL VFSR IFSL IFSR DD input VIH VIL Ii(DD) SU input VIH VIL Ii(SU) VIH VIL Ii(EXTDR) fbridge I+LVS V+LVS Vref(dis) Ii(BD) fbridge Δfosc(T) Δfosc(VDD) kH kL kosc Rext Notes PARAMETER HS lockout voltage right FS supply current left FS supply current right CONDITIONS VFSL = 12 V VFSR = 12 V VDD = 12 V MIN. 3.0 2 2 TYP. 4.0 4 4 − − − − − − − − − − MAX. 5.0 6 6 − 3 1 − 2 1 − 1.0 1 250 UNIT V μA μA HIGH-level input voltage LOW-level input voltage input current into pin DD 6 − − V V μA HIGH-level input voltage LOW-level input voltage input current into pin SU VDD = 12 V 4 − − V V μA External drive input HIGH-level input voltage LOW-level input voltage input current into pin EXTDR bridge frequency note 3 with respect to V−LVS with respect to V−LVS 4.0 − − − V V μA kHz μA V Low voltage logic supply low voltage supply current low voltage supply voltage V+LVS = VEXTDR = 5.75 to 14 V with − respect to V−LVS with respect to V−LVS 5.75 250 − 500 14 Bridge disable input disable reference voltage disable input current 1.23 − − −10 −10 0.38 − 0.94 100 1.29 − − 0 0 0.4 0.01 1.02 − 1.35 1 V μA Internal oscillator bridge oscillating frequency oscillator frequency variation with temperature oscillator frequency variation with VDD high level trip point low level trip point oscillator constant external resistor to VDD note 3 fbridge = 250 Hz and Tamb = −40 to +150 °C fbridge = 250 Hz and VDD = 7.25 to 14 V VRC(high) = kH × VDD VRC(low) = kL × VDD fbridge = 250 Hz 100 +10 +10 0.42 − 1.10 − kΩ kHz % % 1. The current is specified without commutation of the bridge. The current into pin HV is limited by a thermal protection circuit. The current is limited to 11 mA at Tj = 150 °C. 2. The current is specified without commutation of the bridge and pin HV is connected to VDD. 3. The minimum frequency is mainly determined by the value of the bootstrap capacitors. 2002 Oct 08 9 NXP Semiconductors Product specification HF full bridge driver IC APPLICATION INFORMATION Basic application A basic full bridge configuration with an HID lamp is shown in Fig.3. The bridge disable, the start-up delay and the external drive functions are not used in this application. The pins −LVS, +LVS, EXTDR and BD are short-circuited to SGND. The internal oscillator is used and to realize a 50% duty cycle the internal divider function has to be used UBA2033 by connecting pin DD to SGND. The IC is powered by the high voltage supply. Because the internal oscillator is used, the bridge commutating frequency is determined by the values of Rosc and Cosc. The bridge starts oscillating when the HV supply voltage exceeds the level of release power drive (typically 12.5 V on pin HV). If the supply voltage on pin HV drops below the reset level of power drive (typically 10 V on pin HV), the UBA2033 enters the start-up state. handbook, full pagewidth high voltage 550 V (max) R>100 Ω HR HL R>100 Ω −LVS EXTDR +LVS HV VDD Ci Rosc C3 SU DD BD RC SGND Cosc 1 2 3 6 9 10 11 12 13 14 28 27 26 GHR FSR SHR C1 LR IGNITOR LL R>100 Ω R>100 Ω 23 GLR PGND GLL SHL FSL GHL UBA2033TS 21 20 17 16 15 C2 GND MBL459 Fig.3 Basic configuration. 2002 Oct 08 10 NXP Semiconductors Product specification HF full bridge driver IC Application with external control Figure 4 shows an application containing a system ground-referenced control circuit. Pin +LVS can be connected to the same supply as the external oscillator control unit and pin −LVS is connected to SGND. Pin RC is UBA2033 short-circuited to SGND. The bridge commutation frequency is determined by the external oscillator. The bridge disable input (pin BD) can be used to immediately turn off all four MOSFETs in the full bridge. handbook,high voltage full pagewidth 550 V (max) R>100 Ω HR HL R>100 Ω low voltage −LVS EXTDR +LVS HV VDD SU DD BD RC SGND C3 1 2 3 6 9 10 11 12 13 14 28 27 26 GHR FSR SHR C1 LR IGNITOR LL R>100 Ω R>100 Ω Ci EXTERNAL OSCILLATOR CONTROL CIRCUIT 23 GLR PGND GLL SHL FSL GHL UBA2033TS 21 20 17 16 15 C2 GND MBL460 Fig.4 External control configuration. 2002 Oct 08 11 NXP Semiconductors Product specification HF full bridge driver IC Additional application information GATE RESISTORS At ignition of an HID lamp, a large EMC spark occurs. This can result in a large voltage transient or oscillation at the gates of the full bridge MOSFETs (LL, LR, HR and HL). When these gates are directly coupled to the gate drivers (pins GHR, GLR, GHL and GLL), voltage overstress of the driver outputs may occur. Therefore it is advised to add a resistor with a minimum value of 100 Ω in series with each gate driver to isolate the gate driver outputs from the actual power MOSFETs gate. ’Dead time’ can also be adjusted via the combination gate resistor and gate-source capacitance. UBA2033 GATE CHARGE AND SUPPLY CURRENT AT HIGH FREQUENCY USE The total gate current needed to charge the gates of the power MOSFETs equals: I gate = 4 × f bridge × Q gate Where: Igate = gate current fbridge = bridge frequency Qgate = gate charge. This current is supplied via the internal low voltage supply (VDD). Since this current is limited to 11 mA (see “Characteristics” table note 1), at higher frequencies and with MOSFETs having a relative high gate charge, this maximum VDD supply current may not be sufficient anymore. As a result the internal low voltage supply (VDD) and the gate drive voltage will drop resulting in an increase of the higher resistance (Ron) of the full bridge MOSFETs. In this case an auxiliary low voltage supply is necessary. 2002 Oct 08 12 NXP Semiconductors Product specification HF full bridge driver IC PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm UBA2033 SOT341-1 D E A X c y HE vMA Z 28 15 Q A2 pin 1 index A1 (A 3) θ Lp L 1 14 A detail X e bp wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 θ 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2002 Oct 08 13 NXP Semiconductors Product specification HF full bridge driver IC SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. UBA2033 If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2002 Oct 08 14 NXP Semiconductors Product specification HF full bridge driver IC Suitability of surface mount IC packages for wave and reflow soldering methods UBA2033 SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable 2002 Oct 08 15 NXP Semiconductors Product specification HF full bridge driver IC DATA SHEET STATUS DOCUMENT STATUS(1) Objective data sheet Preliminary data sheet Product data sheet Notes 1. Please consult the most recently issued document before initiating or completing a design. PRODUCT STATUS(2) Development Qualification Production DEFINITION UBA2033 This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. DISCLAIMERS Limited warranty and liability ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2002 Oct 08 16 property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. NXP Semiconductors Product specification HF full bridge driver IC Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. UBA2033 Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products ⎯ Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 2002 Oct 08 17 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613502/01/pp18 Date of release: 2002 Oct 08 Document order number: 9397 750 09574