UBA2036TS

UBA2036TS Full bridge control IC for HID automotive lighting Rev. 01 — 30 October 2008 Product data sheet 1. General description The UBA2036 is a high voltage monolithic Integrated Circuit (IC) manufactured in a High Voltage Silicon On Insulator (HVSOI) process. This circuit is designed for driving MOSFETs in a full bridge configuration. In addition, it features a disable function, an internal adjustable oscillator and an external clock input function with a high-voltage level shifter for driving the bridge. To guarantee an accurate 50 % duty cycle, the oscillator signal can be passed through a divider before being fed to the output drivers. The UBA2036 is especially suitable for High Intensity Discharge (HID) lamp drivers for car headlights, projectors and general lighting applications. 2. Features I I I I I I I I I I I Full bridge driver circuit Integrated bootstrap diodes 464 V integrated high voltage level shift function to drive HID lamps below ground level 550 V series regulator input to make the internal supply 550 V maximum bridge voltage Accurate bridge disable function Input for start-up delay Adjustable oscillator frequency Selectable frequency divider Predefined bridge position during start-up Adaptive non-overlap 3. Applications I The UBA2036 can drive (via the power MOSFETs) any kind of load in a full bridge configuration I The circuit is especially designed as a commutator controller for HID lamps in car headlights, projectors and general lighting applications 4. Ordering information Table 1. Ordering information Package Name UBA2036TS SSOP28 Description plastic shrink small outline package; 28 leads; body width 5.3 mm Version SOT341-1 Type number NXP Semiconductors UBA2036TS Full bridge control IC for HID automotive lighting 5. Block diagram VSS(CLK) CLK VDD(CLK) 1 2 3 16 FSL HIGHER LEFT DRIVER 15 GHL 17 6 HV 14 SGND STABILIZER LOGIC SIGNAL GENERATOR OSCILLATOR HIGH VOLTAGE LEVEL SHIFTER HIGHER RIGHT DRIVER SHL FSR 27 9 VDD RC 13 28 26 GHR SHR GLR UBA2036TS ÷2 LOWER RIGHT DRIVER 23 21 SU BD 10 12 1.29 V bridge disable 11 DD 4, 5, 7, 8, 18, 19, 22, 24, 25 n.c. 014aaa632 PGND LOGIC LOW VOLTAGE LEVEL SHIFTER LOWER LEFT DRIVER 20 GLL Fig 1. Block diagram UBA2036TS_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 30 October 2008 2 of 13 NXP Semiconductors UBA2036TS Full bridge control IC for HID automotive lighting 6. Pinning information 6.1 Pinning VSS(CLK) CLK VDD(CLK) n.c. n.c. HV n.c. n.c. VDD 1 2 3 4 5 6 7 8 9 28 GHR 27 FSR 26 SHR 25 n.c. 24 n.c. 23 GLR 22 n.c. 21 PGND 20 GLL 19 n.c. 18 n.c. 17 SHL 16 FSL 15 GHL 014aaa633 UBA2036TS SU 10 DD 11 BD 12 RC 13 SGND 14 Fig 2. Pin assignment SSOP28 package (top view) 6.2 Pin description Table 2. Symbol VSS(CLK) CLK VDD(CLK) n.c. n.c. HV n.c. n.c. VDD SU DD BD RC SGND GHL FSL SHL n.c. n.c. UBA2036TS_1 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Description negative supply voltage for logic oscillator input oscillator input positive supply voltage for logic oscillator input not connected not connected high voltage supply input for internal series regulator not connected not connected internal low voltage supply input for start-up delay input for divider disable input for bridge disable RC input for internal oscillator signal ground gate driver output for upper left MOSFET floating supply left source upper left MOSFET not connected not connected © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 30 October 2008 3 of 13 NXP Semiconductors UBA2036TS Full bridge control IC for HID automotive lighting Pin description …continued Pin 20 21 22 23 24 25 26 27 28 Description gate driver output for lower left MOSFET power ground not connected gate driver output for lower right MOSFET not connected not connected source upper right MOSFET floating supply right gate driver upper right MOSFET Table 2. Symbol GLL PGND n.c. GLR n.c. n.c. SHR FSR GHR 7. Functional description 7.1 Supply voltage The UBA2036 is powered by a supply voltage applied to pin HV, e.g. the supply voltage of the full bridge. The IC generates its own low supply voltage for its internal circuitry. Therefore an additional low voltage supply is not required. A capacitor has to be connected to pin VDD to obtain a ripple-free internal supply voltage. The circuit can also be powered by a low voltage supply directly applied to pin VDD. In this case pin HV should be connected to pin VDD or pin SGND. The maximum current that the internal series regulator can deliver, is temperature dependent. This is shown in Figure 3. 7.2 Start-up With an increasing supply voltage the IC enters the start-up state i.e. the upper power transistors are set in off-state and the lower power transistors are switched on. During the start-up state the bootstrap capacitors are charged. The start-up state is defined until VVDD = Vstartup(VDD) or VHV = Vstartup(HV). The state of the outputs during the start-up phase is overruled by the bridge disable function. 7.3 Oscillation state At the moment the supply voltage on pin VDD exceeds Vstartup(VDD) or the supply voltage on pin VHV exceeds Vstartup(HV), the output voltage of the full bridge depends on the control signals on pins CLK, SU, DD and BD. This is listed in Table 3. As soon as the supply voltage on pin VDD becomes lower than VUVLO(VDD) or the supply voltage on pin VHV becomes lower than VUVLO(HV), the IC enters the start-up state again. Table 3. Driver Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK. Device state Start-up state BD SU DD 1 0 CLK GHL 0 (= VSHL) 0 (= VSHL) GHR 0 (= VSHR) 0 (= VSHR) GLL 0 (= VPGND) 1 (= VVDD) GLR 0 (= VPGND) 1 (= VVDD) UBA2036TS_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 30 October 2008 4 of 13 NXP Semiconductors UBA2036TS Full bridge control IC for HID automotive lighting Table 3. Driver …continued Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK. Device state Oscillation state BD SU DD 1 0 0 0 0 [1] [2] CLK 1 0 1→ 0[2] GHL 0 (= VSHL) 0 (= VSHL) 0 (= VSHL) 1 (= VFSL) GHL GHR 0 (= VSHR) 0 (= VSHR) 1 (= VFSR) 0 (= VSHR) GHR GLL 0 (= VPGND) 1 (= VVDD) 1 (= VVDD) 0 (= VPGND) GLL GLR 0 (= VPGND) 1 (= VVDD) 0 (= VPGND) 1 (= VVDD) GLR 0 1 1 1 1 1 0[1] If pin DD = 0 the bridge enters the state (oscillation state and pin BD = 0 and pin SU = 1) in the pre-defined position: VGHL = VFSL, VGLR = VVDD, VGLL = VPGND, and VGHR = VSHR. Only if the level of pin CLK changes from logical 1 to 0, the level of outputs GHL, GHR, GLL and GLR changes. If there is no external clock available, the internal oscillator can be used. The design equation for the bridge oscillator frequency is shown in Equation 1. 1 f bridge = -------------------------------------------K osc × R osc × C osc (1) Rosc and Cosc are external components connected to the RC pin (Rosc connected to pin VDD and Cosc connected to pin SGND). In this situation the pins VDD(CLK), CLK and VSS(CLK) can be connected to SGND. The clock signal, coming from either pin RC or pin CLK, is divided by two in order to obtain a 50 % duty-cycle gate drive signal. This can be achieved by applying a voltage to the DD input lower than VIL(DD) (e.g. connect pin DD to pin SGND). 7.4 Non-overlap time In the full bridge configuration the non-overlap time is defined as the time between turning off the two conducting MOSFETs and turning on the two other MOSFETs. The non-overlap time is realized by means of an adaptive non-overlap circuit. With an adaptive non-overlap, the application determines the duration of the non-overlap and makes the non-overlap time optimal for each frequency. The non-overlap time is determined by the duration of the falling slope of the relevant half bridge voltage. The occurrence of a slope is sensed internally. The minimum non-overlap time is internally fixed. 7.5 Start-up delay A simple resistor-capacitor (RC) filter (R between pin VDD and pin SU; C between pin SU and pin SGND) or a control signal from a processor can be used to make a start-up delay. This can be beneficial for those applications in which building up the high voltage takes a larger amount of time: A start-up delay will ensure that the HID system will not start up before this high voltage has been reached. 7.6 Bridge disable The bridge disable function can be used to switch off all the MOSFETs as soon as the voltage on pin BD exceeds the bridge disable voltage VBD. The bridge disable function overrules all the other states. UBA2036TS_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 30 October 2008 5 of 13 NXP Semiconductors UBA2036TS Full bridge control IC for HID automotive lighting 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to signal ground (pin 14); positive currents flow into the chip. The voltage ratings are valid provided other ratings are not violated. Symbol General Tamb Tj Tstg Voltages VVDD VHV VSHL voltage on pin VDD voltage on pin HV voltage on pin SHL with respect to PGND and SGND with respect to SGND; maximum pulse time = 1 µs VSHR voltage on pin SHR with respect to PGND and SGND with respect to SGND; maximum pulse time = 1 µs VFSL VFSR VGHL VGHR VGLL VGLR VPGND VSS(CLK) VDD(CLK) voltage on pin FSL voltage on pin FSR voltage on pin GHL voltage on pin GHR voltage on pin GLL voltage on pin GLR voltage on pin PGND CLK ground supply voltage CLK supply voltage t