UBA2074ATS/N1,518

D D D D D R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D A FT D R A F FT FT A A R R D D Preliminary data sheet R R FT FT A A R R D D D D High Voltage Full-bridge control IC for CCFL backlighting Rev. 02.0 — February 2007 FT FT FT FT FT UBA2074(A) D FT FT A A R R D D D R 1. General description A The A-version has no hardswitching protection in order to suit medium voltage (e.g 60V) full bridge systems. 2. Features Suitable for operating in a very wide inverter supply voltage range (up to 550 V DC for SO28 package, up to 225 V for SSOP28 package) Wide IC supply voltage range (9 V to 30 V DC) Suitable for synchronizing multiple inverters to a single operating frequency with equal lamp current phase Adjustable maximum fault timing Integrated level-shifters Integrated bootstrap diodes Lamp current control Over-voltage control Over-current protection Ignition failure detection Hard-switching control (not in the A-version) Arcing detection Brightness level adjustment through PWM dimming Integrated PWM generator A The UBA2074 is designed to operate in a very wide inverter supply voltage range. The IC can be configured to be supplied directly from a low voltage supply up to 30 V DC. The fullbridge voltage can range up to 550V. R Multiple inverters can be synchronized to a single operating frequency, while maintaining constant lamp current. Also, PWM dimming can be synchronized by either using the internal PWM generator, or by using an externally applied PWM signal. D Furthermore, the UBA2074 has a build-in HF oscillator which determines the operating frequency, a phase shift controller for obtaining constant lamp current, and a PWM generator which is used to set the brightness level of the CCFLs. FT The UBA2074 is a high voltage IC intended to drive Cold Cathode Fluorescent Lamps (CCFLs) for back-lighting applications. The IC contains level-shifters, bootstrap diodes and drivers for the external full-bridge power switches. D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 3. Applications D FT FT A A R R D LCD-backlighting, including LCD-TV and LCD-Monitor applications. The IC is intended to drive and control a full-bridge inverter with resonant load circuit for CCFLs, but can also drive an array of External Electrode Fluorescent Lamps (EEFLs). D D R A FT D R Table 1: A 4. Ordering information Ordering information Type number Package Name Description Version UBA2074T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 UBA2074TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 UBA2074AT SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 UBA2074ATS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 2 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5. Block diagram D FT FT A A R R D D D R A FT D R A Fig 1. Block diagram UBA2074(A) (Shaded circuit not present in the UBA2074A). UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 3 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 6. Pinning information D FT FT A A R R D 6.1 Pinning D D R A FT D R A Fig 2. Pin assignment SO28 and SSOP28 package (top view) 6.2 Pin description Table 2: Pin description Symbol Pin Description Function IFB 1 current feedback input. Input signal for the lamp current control loop. Should be connected to a voltage proportional to the lamp current. CIFB 2 current regulation capacitor. A capacitor must be connected between this pin and the signal ground. It sets the time constant of the lamp current control loop. VFB 3 voltage feedback input Input signal for the voltage control loop. Should be connected to a voltage proportional to the transformer output voltage CVFB 4 voltage regulation capacitor A capacitor must be connected between this pin and the signal ground. It sets the time constant of the voltage control loop. IREF 5 reference current output A 33kΩ resistor must be connected between this pin and the signal ground. The IC uses it to make accurate internal currents. CT 6 fault timing capacitor A capacitor must be connected between this pin and the signal ground. It sets the time that a fault condition is allowed before the IC shuts itself down. SGND 7 signal ground CF 8 HF-oscillator timing capacitor A capacitor must be connected between this pin and the signal ground. It sets the minimum switching frequency of the full bridge. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 4 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R A FT R A Function phase-shift sweep capacitor A capacitor must be connected between this pin and the signal ground. It sets the time in which the phase difference between bridge halve A and bridge halve B is swept down from regulation level to zero or swept up from zero to regulation level during PWM dimming. CPWM 10 PWM timing capacitor If a capacitor is connected between this pin and the signal ground, it sets the frequency of the PWM oscillator. FT FT A A R R Description 9 D Pin CSWP D Symbol F FT FT A A R R D D D Pin description …continued R FT FT A A R R D D D Table 2: D D R A By connecting this pin to the SYNC-pins of other ICs, they can synchronise their hf-oscillators. Also the IC can synchronise to an external pulse source connected to this pin. nonFAULT 12 status signal input/output The IC signals a fault condition to an external circuit by pulling this pin low and external circuits can also signal a fault condition to the IC by pulling this pin low. PWMa 13 analog PWM dimming input The dutycycle of the internally generated PWM signal is proportional to the voltage on this pin. PMWd 14 digital PWM dimming input/output Digital output of internally generated PWM signal if a capacitor is connected to the CPWM-pin. Digital input of PWM signal if the CPWM-pin is connected to signal ground. Note that the signal on the PWMd-pin is active low, so low voltage on the PWMd-pin means lamps are on. GHB 15 high-side driver output B Gate connection of the high side power switch of full bridge halve B FSB 16 floating supply output B A buffer capacitor must be connected between this pin and the SHB-pin. This capacitor is charged when the low side switch B is on and supplies the high side driver B. SHB 17 high-side source connection B Return for high side gate driver B. Must be connected to the source of the high side power switch of full bridge halve B. NC 18 not connected HV spacer pin EN 19 chip enable input A low voltage on this pin will reset and shutt down the IC VDC 20 IC low-voltage supply input IC supply VDD 21 regulated 12 V supply output/input A buffer capacitor must be connected between this pin and power ground GLB 22 low-side driver output B Gate connection of the low side power switch of full bridge halve B PGND 23 power ground return for low side drivers A and B GLA 24 low-side driver output A Gate connection of the low side power switch of full bridge halve A NC 25 not connected HV spacer pin SHA 26 high-side source connection A Return for high side gate driver A. Must be connected to the source of the high side power switch of full bridge halve A. FSA 27 floating supply output A A buffer capacitor must be connected between this pin and the SHA-pin. This capacitor is charged when the low side switch A is on and supplies the high side driver A. GHA 28 high-side driver output A Gate connection of the high side power switch of full bridge halve A UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 5 of 33 A synchronization input/output R 11 D SYNC FT If this pin is connected to signal ground the internal PWM oscillator is disabled. D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 7. Functional description D FT FT A A R R D The UBA2074 is designed to drive a full-bridge inverter with resonant load. The load consists typically of transformers with CCFLs. Two parameters are used by the UBA2074 to control the switches of the full-bridge inverter: the phase shift and the switching frequency. D D R A FT D Fig 4. Full-bridge inverter voltage and definition of phase shift UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 6 of 33 A Fig 3. Full-bridge inverter definition R The two full bridge halves A and B (Figure 3) always operate at the same switching frequency. The frequency is used to control transformer output voltage during the first ignition of the lamps. The phase difference between the full-bridge halves A and B voltages (VA and VB) controls the lamp current, as this determines the rms value of the full-bridge inverter voltage VA - VB (Figure 4). D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The IC can be supplied in two ways, as illustrated in Figure 5. The voltage at the VDC pin at which the IC starts up and stops, non-overlap time and minimum phase shift during PWM dimming depend on the this supply configuration. F FT FT A A R R D D D 7.1 IC Supply D D R A FT D R A Fig 5. IC supply configurations In the low voltage configuration the VDC pin is connected to an external supply with a voltage of 9 V to 30 V. The VDD-pin is only connected to a buffer capacitor. The VDD-pin acts as a regulated 12 V output, from which the gate drivers are supplied. In the high voltage configuration the VDC-pin is connected to the VDD-pin. Both pins are supplied with a start-up current source and an auxiliary supply. The auxiliary supply is made by the inverter itself using an auxiliary winding on the lamp transformer or a dV/dt supply. To start up a current source of minimal Isupply(hv,start) is needed. At start-up the IC is supplied by a buffer capacitor (C1 in Figure 5) until the auxiliary supply is settled. The start-up current source may be a resistor connected to the inverter supply voltage if that has a high enough voltage. The auxiliary supply must not exceed the maximum voltage allowed on the VDD-pin as stated in Table 3 and has to be above VVDC(stop-high). 7.2 VDD clamp In the high voltage configuration, when the IC is disabled (EN-pin low) or in the stop state, the VDD clamp is activated. The VDD clamp is always disconnected when the IC is supplied in low voltage configuration. The VDD clamp is an internal active zener of VVDD(clamp) (see Table 5) connected to the VDD-pin. It prevents the start up current source from charging the supply buffer capacitor to a too high voltage. The current supplied by the start up current source must always be below the maximum internal zener clamp current as stated in Table 3. To prevent damage to the IC, in the high voltage configuration, the IC should not be supplied directly by a low impedance voltage source. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 7 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT D FT In the low voltage configuration, the IC starts up at VVDC(start-low) and locks out (stops oscillating) when the voltage on the VDC-pin drops below VDC(stop-low). FT A A R R D The start and stop voltage levels on the VDC-pin depent on the way the IC is supplied: FT A A R R D D D 7.3 Start-up and Under-Voltage Lock-Out (UVLO) D D R A 7.5 Lamp (re-)ignition The IC starts at its maximum switching frequency Fs(max). First the capacitors at the CIFB-pin and CSWP-pin are charged (setting the phase shift between the two bridge halves to maximum). Then the frequency is swept down to the minimum frequency Fs(min) (see Figure 7). During this initial ignition frequency sweep the lamp voltage will increase as the frequency comes closer to the resonant frequency of the unloaded resonance circuit. Once the ignition voltage Vign is reached, the lamps will ignite and the lamp voltage will drop to the voltage of the loaded resonance curve. Fig 6. Initial ignition of flourescent lamp via frequency sweep and load resonance . UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 8 of 33 A When the voltage on the EN-pin comes above VEN(high) the IC will start up again. R The UBA2074 is put in standby when the voltage on the EN-pin comes below VEN(low) (see Table 5). The IC will stop oscillating, and most of the internal circuits will shut down. However, in low voltage configuration, the internal linear regulator between VDC and VDD will remain active, but with reduced current supply capability. All internal signals are reset when the EN-pin is low. D 7.4 Enable FT In the high voltage configuration, the IC starts up at VVDC(start-high) and locks out (stops oscillating) when the voltage on the VDC-pin drops below VVDC(stop-high). D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Advantage of the sweep rather then a fixed ignition frequency is that sensitivity for spread in resonance frequency is much lower. D FT FT A A R R D Once the lamps are ignited the frequency sweep down continues, gradually increasing the lamp current (the resonance circuit should now still be inductive, so current increases as frequency drops) untill the current regulation level is reached and the current regulation loop starts decreasing the phase shift between the bridge halves in order to keep the lamp current constant. If the current regulation loop cannot decrease the phase shift fast enough to counteract the frequency sweep down, then the frequency sweep is slowed down. Once the frequency has reached Fs(min), synchronisation and PWM dimming are enabled (See Figure 7). D D R A The voltage at the CSWP-pin is proportional to the phase shift (see Figure 8). The voltage at the CSWP-pin is clamped at the low side at VCSWP(lclamp) and at the high side at VCIFB. Because VCIFB is clamped at VCIFB(hclamp), VCSWP is also clamped. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 9 of 33 A The voltage at the CVFB-pin is inverse proportional to the switching frequency,(see Figure 8). The voltage at the CVFB-pin is clamped at the voltage VCVFB(range) were the switching frequency is Fs(min). R During PWM dimming the switching frequency is constant. Only the phase shift is swept from its regulated value to its minimum value and back. The phase shift sweep has to provide re-ignition of the lamps, therefor the unloaded resonance curve of Figure 6 has to be high enough at the normal operation switching frequency (which is either Fs(min) or the synchronised switching freqency fsync. D Fig 7. Timing diagram of the initial ignition frequency sweep FT Initial ignition frequency sweep and PWM-generator are not synchronised, and once the frequency sweep is finished PWM dimming can start anywhere in its cycle. D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A Fig 8. frequency and phase shift as function of CVFB and CSWP voltages 7.6 Lamp current control The lamp current control is active during the initial ignition frequency sweep and when the lamps are on. It is disabled during the time within a PWM dim cycle that the lamps are off. An (AC or DC) voltage representing the lamp current, usually the voltage across an external sense resistor, is to be connected to the IFB-pin. This voltage is internally double-side rectified (DSR), and compared to a reference level VIFB(reg) by an operational transconductance amplifier (OTA), as shown in Figure 9. When the current is being regulated, switches S1 and S2 (see Figure 9) are closed (conducting). The output current of the OTA is fed into capacitor C1, which is connected to the CIFB-pin. The voltage across this capacitor is copied into capacitor C2, which is connected to the CSWP-pin. The voltage on the CSWP-pin controls the phase shift. Fig 9. Lamp current control circuit UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 10 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A FT FT A A R R D D During the time within a PWM dim cycle that the lamps are off, switches S1 and S2 are opened (non-conducting). In this way the regulation level is stored in C1 when the current regulation loop is opened (see Figure 9). F FT FT A A R R D D D 7.7 PWM dimming D D R A Fig 10. Light output as function of PWMa input voltage Three pins are available to configure the internal PWM generator: the CPWM-, PWMa-, and the PWMD-pin. The two possible PWM configurations are shown in Figure 11. In the analog or master mode the internal PWM generator is active and generating the PWM signal. This signal is put on the PWMd-pin, which is automatically configured as an output. The minimum dutycycle of the internal PWM generator is limited to DPWM(min,intern). When the CPWM-pin is connected to ground, the IC is put in digital or slave mode. The PWMd-pin is then an input and the IC uses the PWM signal provided on the PWMd-pin. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 11 of 33 A The phase shift sweep speed is determined by the capacitor connected to the CSWP-pin (C2 in Figure 9). The real lamp light output will be slightly less then the PWMd signal duty cycle because of the phase shift sweep time (see Figure 10). When the lamp-on time is too short to sweep up the voltage on the CSWP-pin, the IC will wait until the CSWP voltage has actually reached the current control level before sweeping down again. This prevents that the lamps go out completely when deep dimming is combined with a too large capacitor at the CSWP-pin. R During the PWM lamps off period the phase shift level at which the lamp current was in regulation is preserved in the capacitor connected to the CIFB-pin (C1 in Figure 9). Switches S1 and S2 are closed (conducting) again when the voltage on the CSWP-pin has reached the voltage on the CIFB-pin again. D The minimum phase difference between the bridge halves during the lamps off period of each PWM cycle is ∆φ(min,lv) in low voltage configuration and ∆φ(min,hv) in high voltage configuration. ∆φ(min,hv)>∆φ(min,lv) because of the need to keep commuttation current for zero voltage switching at high bridge voltages. FT After the regulation loop is opened, C2 is discharged (the voltage on the CSWP-pin is swept down) to switch off the lamps, and charged again to turn the lamps on again. The lamps on versus off time is determined by the signal on the PWMd-pin (low = lamps on). D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The signal on the PWMd-pin is active low. A voltage below VPWMD(low) on the pin will turn the lamps on and a voltage above VPWMD(high) will turn the lamps off. D FT FT A A R R D D D R A FT D R A Fig 11. PWM dimming configurations PWM dimming of multiple ICs can be synchronised by configuring one IC as master and the others as slaves and connecting all PWMd-pins together. PWM dimming is only enabled in normal mode, when no fault condition excists. The only exception is when an external detected fault condition is entered via the nonFAULT-pin, then PWM dimming remains active (see Figure 17). 7.8 HF synchronization of inverters There are two ways to sychronize one inverter or multiple inverters to a single operating frequency. The first way is to apply an external signal to all control ICs through the SYNC-pin, see Figure 12. All inverters will lock to the external signal frequency in a PLL-type of way. The frequency of the external signal has to be above the minimum switching frequencies of all ICs. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 12 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R R A FT FT A ICn R IC2 F D D IC1 A FT FT A A R R D D D VDC D D R A SYNC SYNC D SYNC FT ext clk R A R1 Fig 12. HF synchronization of multiple inverters with an external SYNC-signal The second way consists of interconnecting all inverters through the SYNC-pin, see Figure 13. In this case all inverters will lock to the highest of the minimum switching frequencies of all ICs in a PLL-type of way. IC1 SYNC IC2 SYNC ICn SYNC Fig 13. HF synchronization of multiple inverters without an external SYNC-signal Fig 14. SYNC-signal waveform (as seen on the SYNC-pin of an IC) For both synchronisation methods the waveform of the voltage on the SYNC pins looks like Figure 14 (tsync(period) = 1/Fsync). UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 13 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Both synchronisation methods will also lock all inverters in phase. All the full bridge voltages will all be exactly in phase, even if the (regulated) phase difference between outputs A and B of each IC is not the same. In this way, all lamps in a multi inverter system are running at the same frequency and with equal lamp current phase, as illustrated in Figure 15. D FT FT A A R R D D D R A Synchronisation is only enabled in normal mode, when no fault condition excists. The only exception is when an external detected fault condition is entered via the nonFAULT-pin, then synchronisation remains active (see Figure 17). FT D R A Fig 15. Full bridge voltages of two HF synchronised inverters 7.9 The fault timer The fault timer provides a delay inbetween the detection of a fault and the shut down of the IC (enter STOP-state). Its time Tfault(timeout) is proportional to the capacitor connected to the CT-pin. Any fault condition will start the timer. When the timer is activated, the capacitor at the CT-pin will be alternatingly charged and discharged (see Figure 16). These cycles are being counted by a four bit counter. After one cycle (the fault signalling delay Tfault(delay)) the nonFAULT-pin is activated (pulled low), to signal to any external circuit that there is a fault detected and the IC will stop if that fault continues. After 15 cycles is the fault time-out period Tfault(timeout) reached, and the IC will enter STOP-state. If the fault timer is inactive, the CT-pin voltage is one Vbe (≅0.7V). The CT-timer has a protection that prevents the IC to start-up if the CT-pin is shorted to GND. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 14 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A Fig 16. Fault timer wavefporms 7.10 Protections All fault conditions and how they are processed in the IC can be found in Figure 17. The hardswitching is not present in the A-version. The UBA2074 includes internal over voltage (OV), overcurrent (OC), bad contact or arcing (ARC), ignition failure (IF) and hard switching (HS)1 protections. There is also one pin (the nonFAULT-pin) which provides bidirectional fault signalling to and from any external circuit. Via this pin a lamp short detection or over temperature detection or such can be added. Fig 17. Simplified control schematic. In the next sections each fault protection function will be explained. 1. Not present in the UBA2074A. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 15 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A D FT FT A A R R D The over voltage protection circuit is intended to prevent the transformer output voltage from exceeding its maximum rating. It can also be used to regulate the output voltage to the required lamp ignition voltage. F FT FT A A R R D D D 7.10.1 Over voltage protection D D R A 7.10.2 Over current detection When the absolute value3 of the voltage across the current sense resistor (connected to the IFB-pin) exceeds the OC reference level VIFB(ocref), over-current is detected. As result PWM dimming and synchronisation are disabled and the fault timer is started. 7.10.3 Arcing detection If arcing occurs, for instance due to a bad lamp connection, it causes repetitive short current spikes that can be seen as voltage spikes at the IFB input4. The arcing detection circuit is directly connected to the IFB-pin, so it can only see spikes with a positive polarity. Usually that will be sufficient. It can detect spikes with amplitude above VIFB(arcref) and a duration longer then TSPIKE(min). Each spike will trigger an internal one-shot, which signals to the control circuits that arcing has been detected. If this happens PWM dimming and synchronisation are disabled, and the fault timer is started. 7.10.4 Hard switching protection The hard switching protection is not present in the A-version. 2. 3. 4. Presuming that the effective full bridge load impedance is in inductive region. The OC comparator is behind the double side rectifier at the IFB-pin Provided that the current sensing circuit is simple sense resistor only. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 16 of 33 A The voltage at CVFB is limited by the oscillator circuit to VCVFB(range) when the minimum switching frequency Fs(min) is reached. This ensures an immediate frequency increase capability at over voltage detection. R An internal latch makes the OV fault signal continuesly high even if the voltage at the VFB-pin only exceeds VVFB(ovref) during part of the output period. So the peak of the voltage on the VFB-pin determines if an over voltage fault condition is seen.In order to avoid that OV fault condition at the nominal switching frequency (with the lamps operating normally), the voltage ripple on the VFB-pin must not be too large. D If CVFB is more discharged then charged (over a hf cycle) then the CVFB voltage will drop, and the switching frequency increase. As a result the output voltage of the transformer will decrease2. When this happens the current control loop is froozen (switch S1 of Figure 9 is opened (non-conducting), so the regulation level stored in C1 cannot be changed by the current regulation loop) in order to prevent the frequency increase being compensated by a phase shift difference increase by the current control. FT When the voltage on the VFB-pin exceeds the OV reference level VVFB(ovref), over voltage is detected. As result PWM dimming and synchronisation are disabled and the fault timer is started. Also the capacitor connected to the CVFB-pin is discharged (by ICVFB(ov)). When the voltage at the VFB-pin drops below the OV reference level, the CVFB capacitor is charged (by ICVFB(charge)) again.and the output voltage of the transformer will increase again. Because the charging and discharging of the CVFB capacitor follows the ripple on the VFB voltage, the feedback gain of the voltage control loop is set by the ripple on the feedback signal. D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D The UBA2074 is capable of driving a full bridge at a higher voltage then its own supply voltage. A special feature is included to accomodate applications where zero voltage switching becomes important. The design of the resonant load determines if zero voltage switching occurs during normal operation. To prevent overheating of the external power switches of the full bridge due to high switching losses in case of any abnormal condition, the hard-switching of both half-bridge voltages is monitored internally. At the moment the high side switch is turned on, the voltage step at the SH-pin is measured. If it is above VHS(thresshold) then PWM dimming and synchronisation are disabled and the fault timer is started. Also the frequency is increased by discharging the capacitor at the CVFB pin (by ICVFB(hs)). D FT FT A A R R D D D R A An external circuit can signal to the IC that a fault has been detected by pulling down the pin. The IC will detect the current drawn from the pin and start the fault timer. To prevent interference with the PWM dimming, the IC will only look at the nonFAULT pin during the period that the lamp current regulation loop is closed (VCSWP=VCIFB). When the IC detects a fault internal (as in Section 7.10.1 to Section 7.10.5), it signals this via the nonFAULT pin by pulling the pin down. In this case the IC can not see anymore if there’s an external detected fault, but that’s no problem, because the faulttimer is then already running. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 17 of 33 A The nonFAULT-pin provides bidirectional signalling of the fault status between the IC and any external circuit. When no fault is detected, the voltage on the pin is pulled high by an internal current source. R 7.10.6 The nonFAULT-pin D When the current control loop comes close to its regulation point, the lamps are presumed to be on (ignited). This is when the average double side rectified IFB-pin voltage is above VIFB(lampon). If the lamps are not on when the ignition sweep is finished (switching frequency has reached FS(min)), then an ignition failure is detected, PWM dimming and synchronisation are disabled and the fault timer is started. FT 7.10.5 Ignition Failure (IF) D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A Fig 18. Input and output levels at the nonFAULT pin. The signal from the IC is a voltage signal and the signal to the IC is a current signal. In this way a driving conflict is prevented. Also it leaves the possibility for the outside world to see the signal from the IC even while a fault condition is being signalled to the IC in the mean time, as illustrated in Figure 19. Fig 19. Splitting the nonFAULT pin signals to and from the IC. 7.11 High- and low-side drivers The four drivers are identical. The output of each driver is connected to the equivalent gate of an external power MOSFET. The bootstrap capacitors are charged from the VDD voltage when the low-side power MOSFETs are turned on, and they supply the high-side drivers. The VDD voltage directly supplies the low-side drivers. Current sourcing capability and the on-resistance of the drivers can be found in Table 5. UBA2074(A) Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 02.0 — February 2007 18 of 33 D D D D D R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D UBA2074(A) D NXP Semiconductors High Voltage Full-bridge control IC for CCFL backlighting D R R A FT FT FT A A R R D D D R A D FT FT A A R R D For each half bridge a delay is made between the switching-off of the external high side power transistor and the switching-on of the external low side power transistor and the other way round. The duration of this so called ‘non-overlap’ time (TNONOV) can be selected via the supply configuration (see Figure 5). When the IC is in high voltage configuration the non-overlap time is longer (Tnonov(hv)) then when the IC is in low voltage configuration (Tnonov(lv)). This because commutation takes longer at high bridge voltages. F FT FT A A R R D D D 7.12 Non overlap D D R A Conditions Min Max Unit General RIREF reference resistor value on pin IREF 30 36 kΩ SR slew rate on pins FSA, FSB, GHA, GHB, SHA, and SHB −4 +4 V/ns Tamb ambient temperature −25 +100 °C Tj junction temperature −25 +125 °C Tstg storage temperature −55 +150 °C Voltages VFSA, VFSB voltage on pins FSA and FSB VVDD, VEN voltage on pins VDD and EN continuous 0 +570 V t < 0.5 s 0 +630 V with respect to VSHA, VSHB -0.3 +14 V -0.3 +14 V VGLA, VGLB voltage on pins GLA and GLB -0.3 VVDD V VGHA voltage on pins GHA VSHA -0.3 VFSA V VGHB voltage on pins GHB VSHB VFSB V -0.3 VPGND voltage on pin PGND 0 0 V VVDC voltage on pin VDC -0.3 +30 V VPWMa, VPWMd, VnonFAULT voltage on pins PWMa, PWMd and nonFAULT -0.1 +5 V VVFB voltage on pin VFB continuous -0.1 +5 V t