UJA1166A
High-speed CAN transceiver with 5 V LDO and Sleep mode
Rev. 1 — 23 August 2019
Product data sheet
1. General description
The UJA1166A contains an ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5
compliant HS-CAN transceiver with an integrated 5 V low-dropout linear voltage regulator.
The 5 V regulator provides the internal CAN supply and can also be used to supply
additional discrete CAN transceivers or other onboard loads. The UJA1166A can be
operated in very-low-current Sleep mode with local and bus wake-up capability. It can be
controlled by a microcontroller supplied from an independent 3.3 V or 5 V supply.
This implementation enables reliable communication in the CAN FD fast phase at data
rates up to 5 Mbit/s.
2. Features and benefits
2.1 General
Self-supplied ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant
high-speed CAN transceiver
Hardware and software compatible with the UJA116x product family and with improved
EMC performance
Loop delay symmetry timing enables reliable communication at data rates up to
5 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V low-drop voltage regulator for supplying additional discrete
transceivers or other onboard loads
VIO input allows for direct interfacing with 3.3 V to 5 V microcontrollers
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC TS 62228 on the CAN bus pins and on pins
BAT and WAKE
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins are protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Sleep mode
Leadless HVSON14 package (3 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability
UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
2.3 Integrated 5 V low-drop linear voltage regulator (V1)
5 V nominal output; 2 % accuracy
100 mA output current capability
Current limiting above 150 mA
On-resistance of 5 (max)
Undervoltage detection at 90 % of nominal value
Excellent transient response with a 4.7 F ceramic output load capacitor
Turned off in Sleep mode
Short-circuit to GND/overload protection on pin V1
2.4 Power Management
Sleep mode featuring very low supply current
Remote wake-up capability via standard CAN wake-up pattern
Local wake-up capability via the WAKE pin
Entire node can be powered down via the inhibit output, INH
2.5 System control and diagnostic features
Mode control via SLPN pin
Overtemperature shutdown
Transmit data (TXD) dominant time-out function
3. Ordering information
Table 1.
Ordering information
Type number
UJA1166ATK
UJA1166A
Product data sheet
Package
Name
Description
Version
HVSON14
plastic thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 4.5 0.85 mm
SOT1086-2
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
4. Block diagram
VIO
5
BAT
10
UJA1166A
7
INH
5 V low-drop regulator (V1)
RXD
TXD
SLPN
V1
4
HS-CAN
1
13
12
CAN TRANSCEIVER STATUS
WAKE
3
INH
9
6
CANH
CANL
CTS
WAKE-UP
14
MODE CONTROL
2
GND
Fig 1.
UJA1166A
Product data sheet
aaa-025781
Block diagram of UJA1166A
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
5. Pinning information
5.1 Pinning
terminal 1
index area
TXD
1
14 SLPN
GND
2
13 CANH
V1
3
12 CANL
RXD
4
VIO
5
10 BAT
CTS
6
9
WAKE
INH
7
8
i.c.
UJA1166A
11 i.c.
aaa-025782
Transparent top view
Fig 2.
Pin configuration diagram
5.2 Pin description
Table 2.
Symbol
Pin
Description
TXD
1
transmit data input
GND
2[1]
ground
V1
3
5 V supply for external on-board load
RXD
4
receive data output; reads out data from the bus lines
VIO
5
supply voltage for I/O level adaptor
CTS
6
CAN transceiver status output
INH
7
inhibit output for switching external voltage regulators
i.c.
8
internally connected; should be left floating or connected to GND
WAKE
9
local wake-up input
BAT
10
battery supply voltage
i.c.
11
internally connected; should be left floating or connected to GND
CANL
12
LOW-level CAN bus line
CANH
13
HIGH-level CAN bus line
SLPN
14
Sleep mode control input (active LOW)
[1]
UJA1166A
Product data sheet
Pin description
The exposed die pad at the bottom of the package allows for better heat dissipation and grounding from the
transceiver via the printed circuit board. For enhanced thermal and electrical performance, it is
recommended to solder the exposed die pad to GND.
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
6. Functional description
The UJA1166A is a high-speed CAN transceiver with integrated 5 V linear voltage
regulator. The internally connected regulator provides up to 100 mA to supply external
on-board loads, such as additional CAN transceivers. A variety of fail safe and diagnostic
features offer enhanced system reliability and advanced power management.
6.1 System controller
The system controller is a state machine that manages register configuration and controls
the internal functions of the UJA1166A. UJA1166A operating modes and state transitions
are illustrated in Figure 3. These modes are discussed in more detail in the following
sections.
6.1.1 Operating modes
The UJA1166A supports five operating modes: Normal, Standby, Sleep, Overtemp and
Off.
6.1.1.1
Normal mode
Normal mode is the active operating mode. In this mode, the UJA1166A is fully
operational. Normal mode can be selected from Standby and Sleep (via Standby) modes
by setting pin SLPN HIGH, provided VIO > Vuvd(VIO). The UJA1166A exits Normal mode:
• if the microcontroller selects Standby mode by setting pin SLPN LOW
• if the UJA1166A detects an undervoltage on VIO, causing the UJA1166A to switch to
Standby mode
• if the chip temperature rises above Tth(act)otp, causing the UJA1166A to switch to
Overtemp mode
• if the battery supply voltage drops below Vth(det)poff, causing the UJA1166A to switch
to Off mode
All pending wake-up events (power-on, CAN bus wake-up, local wake-up via the WAKE
pin) are cleared when the UJA1166A enters Normal mode.
6.1.1.2
Standby mode
Standby mode is a transitional mode between Normal and Sleep modes. The transceiver
is unable to transmit or receive data in Standby mode, but pin INH is active.
The receiver monitors bus activity for a wake-up request in Standby mode. The bus pins
are biased at GND level (via Ri(cm)) when the bus is inactive for t > tto(silence) and at
approximately 2.5 V when there is activity on the bus (autonomous biasing). Wake-up can
be triggered remotely via a standard wake-up pattern on the CAN bus (see Section 6.3.2)
or locally via the WAKE pin. Pin RXD is forced LOW when a bus or local wake-up event is
detected.
The UJA1166A switches to Standby mode:
• from Normal mode if pin SLPN goes LOW or an undervoltage is detected on VIO
• from Sleep mode in the event of a local or remote wake-up event or if SLPN = HIGH
(with a valid voltage on VIO)
UJA1166A
Product data sheet
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
overtemperature event
NORMAL
OVERTEMP
SLPN =HIGH &
VIO > Vuvd(VIO)
SLPN = LOW OR
VIO < Vuvd(VIO)
no overtemperature
event
SLPN = HIGH(1) OR
wake-up event
SLEEP
STANDBY
(SLPN = LOW for t > tsleep &
no wake-up pending & VIO > Vuvd(VIO)) OR
VIO < Vuvd(VIO) for t > tuv(VIO)
power-on
VBAT undervoltage event
OFF
from any mode
015aaa303
(1) SLPN = HIGH is only possible in Sleep mode if a valid VIO supply voltage is connected
Fig 3.
UJA1166A system controller state diagram
6.1.1.3
Sleep mode
Sleep mode is the power saving mode of the UJA1166A. In Sleep mode, the transceiver
behaves like in Standby Mode with the exception that pin INH is set floating and
temperature protection is inactive. Voltage regulators controlled by this pin will be
switched off, and the current into pin BAT will be reduced to a minimum.
A HIGH level on SLPN (provided a valid voltage is present on VIO), a local wake-up via
the WAKE pin or a remote CAN bus wake-up will cause the UJA1166A to wake up from
Sleep mode and switch to Standby mode. Pin RXD is forced LOW when a local wake-up
via WAKE or a remote bus wake-up is detected.
The UJA1166A can be set to Sleep mode by holding pin SLPN LOW for t > tsleep (provided
there are no wake-up events pending). If one or more wake-up events is pending, the
UJA1166A will remain in Standby mode. The UJA1166A must be switched to Normal
mode to clear pending wake-up events.
UJA1166A
Product data sheet
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
The UJA1166A will also be forced to Sleep mode if an undervoltage lasting longer than
td(uvd-slp) is detected on VIO (VIO < Vuvd(VIO)). In this event, all pending wake-up events will
be cleared automatically.
6.1.1.4
Off mode
The UJA1166A switches to Off mode from any mode when VBAT < Vth(det)poff. Only
power-on detection is enabled; all other modules are inactive. The UJA1166A starts to
boot up when the battery voltage rises above the power-on detection threshold Vth(det)pon
(triggering an initialization process) and switches to Standby mode after tstartup. Pin RXD is
driven LOW when the UJA1166A switches from Off mode to Standby mode, to indicate a
power-on event has occurred.
In Off mode, the CAN pins disengage from the bus (zero load; high-ohmic).
6.1.1.5
Overtemp mode
Overtemp mode is provided to prevent the UJA1166A being damaged by excessive
temperatures. The UJA1166A switches immediately to Overtemp mode from Normal
mode when the global chip temperature rises above the overtemperature protection
activation threshold, Tth(act)otp.
In Overtemp mode, the CAN transmitter and receiver are disabled and the CAN pins are
in a high-ohmic state. No wake-up event will be detected, but a pending wake-up will still
be signalled by a LOW level on pin RXD, which will persist after the overtemperature
event has been cleared. V1 is off in Overtemp mode. INH remains unchanged.
The UJA1166A exits Overtemp mode:
• and switches to Standby mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
• if the device is forced to switch to Off mode (VBAT < Vth(det)poff)
6.1.1.6
Hardware characterization for the UJA1166A operating modes
Table 3.
Hardware characterization by functional block
Block
Operating mode
Off
Standby
Normal
Overtemp
Sleep
V1
off
on/off[1]
on
off
off
CAN
off
Offline
Active
off
Offline
RXD
VIO level
VIO level/LOW if
wake-up detected
CAN bit stream
VIO level/LOW if
wake-up detected
VIO level/LOW if
wake-up detected
INH
off
VBAT level
VBAT level
VBAT level
off
[1]
V1 is switched on in Standby mode if a CAN wake-up pattern is detected on the bus; if pin SLPN does not go HIGH within tto(silence), V1
is switched off again. V1 is also switched on in Standby mode if SLPN goes HIGH to select Normal mode.
6.1.2 Mode control via pin SLPN
The UJA1166A can be switched between Normal and Standby/Sleep modes via the SLPN
control input (see Figure 3). When SLPN goes LOW, the UJA1166A switches to Standby
mode. If SLPN remains low for tsleep, the UJA1166A then switches to Sleep mode (if no
wake-up is pending). When SLPN goes HIGH, the UJA1166A switches to Normal mode.
UJA1166A
Product data sheet
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
6.2 Power supplies
6.2.1 Battery supply voltage (VBAT)
The internal circuitry is supplied from the battery via pin BAT. The device needs to be
protected against negative supply voltages, e.g. by using an external series diode. If VBAT
falls below the power-off detection threshold, Vth(det)poff, the UJA1166A switches to Off
mode, shutting down the 5 V supply (V1) and other internal logic (except for power-on
detection),
The UJA1166A switches from Off mode to Standby mode tstartup after the battery voltage
rises above the power-on detection threshold, Vth(det)pon. A power-on event is indicated by
a LOW level on pin RXD. RXD remains LOW from the moment UJA1166A exits Off mode
until it switches to Normal mode.
6.2.2 5 V low-drop supply voltage (V1)
V1 is intended to supply the internal high-speed CAN transceiver and external on-board
loads. It delivers up to 150 mA at 5 V. The output voltage on V1 is monitored. If VV1 falls
below the 90 % undervoltage threshold (90 % of the nominal V1 output voltage), the
internal CAN transceiver switches to (or remains in) Offline mode.
The internal high-speed CAN transceiver consumes 50 mA (max) when the bus is
continuously dominant, leaving 100 mA available for the external loads on pin V1
(additional on-board CAN transceivers, for example). In practice, the typical current
consumption of the internal CAN transceiver is lower (25mA), depending on the
application, leaving more current available for the external load.
6.3 High-speed CAN transceiver
The integrated high-speed CAN transceiver is designed for active communication at bit
rates up to 1 Mbit/s, providing differential transmit and receive capability to a CAN protocol
controller. The transceiver is ISO 11898-2:2016 compliant. The CAN transmitter is
supplied from V1. The UJA1166A includes additional timing parameters on loop delay
symmetry to ensure reliable communication in fast phase at data rates up to 5 Mbit/s, as
used in CAN FD networks.
The CAN transceiver supports autonomous CAN biasing, which helps to minimize RF
emissions. CANH and CANL are always biased to 2.5 V when the UJA1166A is in Normal
mode with V1 > 90 % threshold. Autonomous biasing is active when the UJA1166A is in
Standby or Sleep mode with the CAN transceiver in CAN Offline mode - to 2.5 V if there is
activity on the bus (CAN Offline Bias mode) and to GND if there is no activity on the bus
for t > tto(silence) (CAN Offline mode). This is useful when the node is disabled due to a
malfunction in the microcontroller. The transceiver ensures that the CAN bus is correctly
biased to avoid disturbing ongoing communication between other nodes. The
autonomous CAN bias voltage is derived directly from VBAT.
6.3.1 CAN operating modes
The integrated CAN transceiver supports three operating modes: Active, Offline and
Offline Bias (see Figure 4). The CAN transceiver operating mode depends on the
UJA1166A operating mode and the output voltage on pin V1.
UJA1166A
Product data sheet
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
6.3.1.1
CAN Active mode
In CAN Active mode, the transceiver can transmit and receive data via CANH and CANL.
The differential receiver converts the analog data on the bus lines into digital data, which
is output on pin RXD. The transmitter converts digital data generated by the CAN
controller (input on pin TXD) into analog signals suitable for transmission over the CANH
and CANL bus lines.
The CAN transceiver is in Active mode when:
• the UJA1166A is in Normal mode (SLPN = 1) AND VV1 > Vuvd(V1) AND VIO > Vuvd(VIO)
In CAN Active mode, the CAN bias voltage is derived from VV1. If VV1 falls below Vuvd(V1),
the UJA1166A exits CAN Active mode and enters CAN Offline Bias mode with
autonomous CAN voltage biasing via pin BAT.
If pin TXD is LOW when the transceiver switches to CAN Active mode (UJA1166A in
Normal mode; VV1 and VIO ok), the transmitter and receiver will remain disabled until TXD
goes HIGH. This prevents network traffic being blocked for tto(dom)TXD (i.e. while the TXD
dominant time-out timer is running; see Section 6.7.1) every time the transceiver enters
Active mode, if the TXD pin is clamped permanently LOW.
6.3.1.2
CAN Offline and Offline Bias modes
In CAN Offline mode, the transceiver monitors the CAN bus for a wake-up event. CANH
and CANL are biased to GND.
CAN Offline Bias mode is the same as CAN Offline mode, with the exception that the CAN
bus is biased to 2.5 V. This mode is activated automatically when activity is detected on
the CAN bus while the transceiver is in CAN Offline mode. The transceiver will return to
CAN Offline mode if the CAN bus is silent (no CAN bus edges) for longer than tto(silence).
The CAN transceiver switches to CAN Offline mode from CAN Active mode when:
• the UJA1166A switches to Standby or Sleep mode
provided the CAN-bus has been inactive for at least tto(silence). If the CAN-bus has been
inactive for less than tto(silence), the CAN transceiver switches first to CAN Offline Bias
mode and then to CAN Offline mode once the bus has been silent for tto(silence).
The CAN transceiver switches to CAN Offline Bias mode from CAN Active mode if:
• VV1 < Vuvd(V1) OR VIO < Vuvd(VIO)
The CAN transceiver switches to CAN Offline mode:
• from CAN Offline Bias mode when the UJA1166A is in Standby or Sleep mode and no
activity has been detected on the bus (no CAN edges) for t > tto(silence) OR
• when the UJA1166A switches from Off or Overtemp mode to Standby mode
The CAN transceiver switches from CAN Offline mode to CAN Offline Bias mode if:
• a standard wake-up pattern is detected on the CAN bus OR
• the UJA1166A switches to Normal mode while VV1 < Vuvd(V1) OR VIO < Vuvd(VIO)
UJA1166A
Product data sheet
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UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
CAN Active
transmitter: on
RXD: bitstream
CANH/CANL: terminated
to VV1/2 (≈2.5 V)
[t < tto(silence) & Standby/Sleep] OR
VV1 < Vuvd(V1) OR
VIO < Vuvd(VIO)
Normal &
VV1 > Vuvd(V1) &
VIO > Vuvd(VIO)
t > tto(silence) &
Standby/Sleep
CAN Offline Bias
transmitter: off
RXD: wake-up/HIGH
CANH/CANL: terminated
to 2.5 V (from VBAT)
CAN wake-up OR
(Normal &
VV1 < Vuvd(V1) OR
VIO < Vuvd(VIO))
Normal &
VV1 > Vuvd(V1) &
VIO > Vuvd(VIO)
from all modes
t > tto(silence) &
Standby/Sleep
Off OR
Overtemp OR
VBAT < Vuvd(CAN)
CAN Offline
CAN Off
transmitter: off
RXD: wake-up/HIGH
CANH/CANL: terminated
to GND
transmitter: off
RXD: wake-up/HIGH
CANH/CANL: floating
leaving
Off/Overtemp
aaa-025796
Fig 4.
CAN transceiver state machine
6.3.1.3
CAN Off mode
The CAN transceiver is switched off completely with the bus lines floating when:
• the UJA1166A switches to Off or Overtemp mode OR
• VBAT falls below the CAN receiver undervoltage detection threshold, Vuvd(CAN)
It will be switched on again on entering CAN Offline mode when VBAT rises above the
undervoltage recovery threshold (Vuvr(CAN)) and the UJA1166A is no longer in
Off/Overtemp mode. CAN Off mode prevents reverse currents flowing from the bus when
the battery supply to the UJA1166A is lost.
UJA1166A
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
6.3.2 CAN standard wake-up
The UJA1166A monitors the bus for a wake-up pattern when the CAN transceiver is in
Offline mode.
A filter at the receiver input prevents unwanted wake-up events occurring due to
automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be
transmitted on the CAN bus within the wake-up timeout time (tto(wake)) to pass the wake-up
filter and trigger a wake-up event (see Figure 5; note that additional pulses may occur
between the recessive/dominant phases). The recessive and dominant phases must last
at least twake(busrec) and twake(busdom), respectively. Pin RXD is driven LOW when a valid
CAN wake-up pattern is detected on the bus.
CANH
VO(dif)
CANL
twake(busdom)
twake(busrec)
twake(busdom)
RXD
≤ tto(wake)bus
aaa-021858
Fig 5.
CAN wake-up timing
6.4 WAKE pin
In Standby and Sleep modes, a local wake-up event is triggered by a LOW-to-HIGH or a
HIGH-to-LOW transition on the WAKE pin. In applications that don’t make use of the local
wake-up facility, the WAKE pin should be connected to GND for optimal EMI performance.
Pin RXD is driven LOW when a valid edge is detected on pin WAKE.
6.5 VIO supply pin
Pin VIO should be connected to the microcontroller supply voltage. This will cause the
signal levels on TXD, RXD, SLPN and CTS to be adjusted to the I/O levels of the
microcontroller, enabling direct interfacing without the need for glue logic.
6.6 CAN transceiver status pin (CTS)
Pin CTS is driven HIGH to indicate to microcontroller that the transceiver is fully enabled
and data can be transmitted and received via the TXD/RXD pins.
Pin CTS is actively driven LOW:
• while the transceiver is starting up (e.g. during a transition from Standby to Normal
mode) or
• if pin TXD is clamped LOW for t > tto(dom)TXD or
• if an undervoltage is detected on VIO or V1
UJA1166A
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
6.7 CAN fail-safe features
6.7.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
traffic). The TXD dominant time-out timer is reset when pin TXD goes HIGH. The TXD
dominant time-out time also defines the minimum possible bit rate of 4.4 kbit/s.
6.7.2 Pull-up on TXD pin
Pin TXD has an internal pull-up (towards VIO) to ensure a safe defined recessive driver
state in case the pin is left floating.
6.7.3 Pull-down on SLPN pin
Pin SLPN has an internal pull-down (to GND) to ensure the UJA1166A switches to Sleep
mode if SLPN is left floating.
6.7.4 Loss of power at pin BAT
A loss of power at pin BAT has no impact on the bus lines or on the microcontroller. No
reverse currents flow from the bus.
UJA1166A
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UJA1166A
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High-speed CAN transceiver with 5 V LDO and Sleep mode
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
voltage on pin
Vx
Conditions
x[1]
Min
Max
Unit
0.2
+6
V
0.2
VV1 + 0.2 V
pins WAKE, INH
18
+40
V
pin BAT
0.2
+40
V
pins CANH and CANL with respect to any other pin
58
+58
V
40
+40
V
pulse 1
100
-
V
pulse 2a
-
75
V
pulse 3a
150
-
V
-
100
V
6
+6
kV
pins
V1[2],
VIO
pins TXD, RXD, SLPN, CTS
V(CANH-CANL)
voltage between pin
CANH and pin CANL
Vtrt
transient voltage
on pins CANL, CANH, WAKE, BAT
[3]
[4]
pulse 3b
VESD
electrostatic discharge IEC 61000-4-2 (150 pF, 330 ) discharge circuit
voltage
on pins CANH and CANL; pin BAT with
capacitor; pin WAKE with 10 nF capacitor and
10 k resistor
[5]
Human Body Model (HBM)
on any pin
[6]
2
+2
kV
on pins BAT, WAKE
[7]
4
+4
kV
on pins CANH, CANL
[8]
8
+8
kV
100
+100
V
750
+750
V
500
+500
V
40
+150
C
55
+150
C
Machine Model (MM)
[9]
on any pin
Charged Device Model (CDM)
[10]
on corner pins
on any other pin
Tvj
virtual junction
temperature
Tstg
storage temperature
[11]
[1]
The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2]
When the device is not powered up, IV1 (max) = 25 mA.
[3]
Maximum voltage should never exceed 6 V.
[4]
Verified by an external test house according to IEC TS 62228, Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2.
[5]
Verified by an external test house according to IEC TS 62228, Section 4.3.
[6]
According to AEC-Q100-002.
[7]
Pins stressed to reference group containing all grounds, emulating the application circuit (Figure 9). HBM pulse as specified in
AEC-Q100-002 used.
[8]
Pins stressed to reference group containing all ground and supply pins, emulating the application circuit (Figure 9). HBM pulse as
specified in AEC-Q100-002 used.
[9]
According to AEC-Q100-003.
UJA1166A
Product data sheet
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
[10] According to AEC-Q100-011.
[11] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P Rth(j-a), where Rth(j-a) is a
fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient
temperature (Tamb).
UJA1166A
Product data sheet
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Rev. 1 — 23 August 2019
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
8. Thermal characteristics
Table 5.
Symbol
Rth(vj-a)
[1]
Thermal characteristics
Parameter
Conditions
[1]
thermal resistance from virtual junction to ambient
Typ
Unit
60
K/W
According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers
(thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m).
9. Static characteristics
Table 6.
Static characteristics
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; RL = R(CANH-CANL) =60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply; pin BAT
Vth(det)pon
power-on detection threshold
voltage
VBAT rising
4.2
-
4.55
V
Vth(det)poff
power-off detection threshold
voltage
VBAT falling
2.8
-
3
V
Vuvr(CAN)
CAN undervoltage recovery
voltage
VBAT rising
4.5
-
5
V
Vuvd(CAN)
CAN undervoltage detection
voltage
VBAT falling
4.2
-
4.55
V
IBAT
battery supply current
Normal mode; CAN Active mode
CAN recessive; VTXD = VIO
-
4
7.5
mA
CAN dominant; VTXD = 0 V
-
46
67
mA
Standby mode; CAN Offline mode;
40 C < Tvj < +85 C;
VBAT = 7 V to 18 V; IV1 = 0 A
-
[2]
91
A
Sleep mode; CAN Offline mode;
40 C < Tvj < +85 C;
VBAT = 7 V to 18 V
-
[2]
65
A
additional current in CAN Offline
Bias mode; 40 C < Tvj < 85 C
-
38
55
A
VBAT = 5.5 V to 28 V; VTXD = VV1;
IV1 = 120 mA to 0 mA
4.9
5
5.1
V
VBAT = 5.65 V to 28 V; VTXD = VV1
IV1 = 150 mA to 0 mA
4.9
5
5.1
V
VBAT = 5.65 V to 28 V;
IV1 = 100 mA to 0 mA;
VTXD = 0 V; VCANH = 0 V
4.9
5
5.1
V
-
-
5
VBAT = 3 V to 4 V; IV1 = 40 mA
-
2.625
-
Vuvd(nom) = 90 %
4.5
-
4.75
V
4.5
-
4.75
V
Voltage source: pin V1
VO
R(BAT-V1)
output voltage
resistance between pin BAT and VBAT = 4 V to 6 V; IV1 = 120 mA;
pin V1
Tvj < 150 C
Vuvd
undervoltage detection voltage
Vuvr
undervoltage recovery voltage
UJA1166A
Product data sheet
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
Table 6.
Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; RL = R(CANH-CANL) =60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
IO(sc)
short-circuit output current
Conditions
Min
Typ
Max
Unit
300
-
150
mA
2.7
-
2.85
V
Standby/Normal mode;
40 C < Tvj < 85 C
-
7.1
11
A
Sleep mode;
40 C < Tvj < 85 C
-
5.9
9.5
A
Supply; pin VIO
Vuvd
undervoltage detection voltage
II(VIO)
input current on pin VIO
Sleep mode control input; pin SLPN
Vth(sw)
switching threshold voltage
0.25VIO
-
0.75VIO V
Rpd
pull-down resistance
40
60
80
k
Inhibit output: pin INH
VO
output voltage
IINH = 180 A
VBAT 0.8 -
VBAT
V
Rpd
pull-down resistance
Sleep mode
3
4
5
M
CAN transmit data input; pin TXD
Vth(sw)
switching threshold voltage
0.25VIO
-
0.75VIO V
Vth(sw)hys
switching threshold voltage
hysteresis
0.05VIO
-
-
V
Rpu
pull-up resistance
40
60
80
k
CAN transmitter status; pin CTS
IOH
HIGH-level output current
VCTS = VIO 0.4 V; transmitter on
-
-
4
mA
IOL
LOW-level output current
VCTS = 0.4 V; transmitter off
4
-
-
mA
CAN receive data output; pin RXD
VOH
HIGH-level output voltage
IOH = 4 mA
VIO 0.4
-
-
V
VOL
LOW-level output voltage
IOL = 4 mA
-
-
0.4
V
Rpu
pull-up resistance
CAN Offline mode
40
60
80
k
Local wake input; pin WAKE
Vth(sw)r
rising switching threshold
voltage
2.8
-
4.1
V
Vth(sw)f
falling switching threshold
voltage
2.4
-
3.75
V
Vhys(i)
input hysteresis voltage
250
-
800
mV
Ii
input current
-
-
1.5
A
pin CANH; RL = 50 to 65
2.75
3.5
4.5
V
pin CANL; RL = 50 to 65
0.5
1.5
2.25
V
400
-
+400
mV
Tvj = 40 C to +85 C
High-speed CAN bus lines; pins CANH and CANL
VO(dom)
Vdom(TX)sym
dominant output voltage
CAN Active mode; VTXD = 0 V;
t < tto(dom)TXD;
VV1 = 4.5 V to 5.5 V
transmitter dominant voltage
symmetry
UJA1166A
Product data sheet
Vdom(TX)sym = VV1 VCANH VCANL;
VV1 = 5 V
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
Table 6.
Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; RL = R(CANH-CANL) =60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
VTXsym
transmitter voltage symmetry
VO(dif)
differential output voltage
Min
Typ
Max
Unit
0.9VV1
-
1.1VV1
V
RL = 50 to 65
1.5
-
3
V
RL = 45 to 70
1.4
-
3.3
V
RL = 2240
1.5
-
5
V
CAN Active/Offline Bias mode;
VTXD = VIO
50
-
+50
mV
CAN Offline mode
0.2
-
+0.2
V
CAN Active mode; VTXD = VIO;
RL = no load
2
0.5VV1 3
V
CAN Offline mode;
RL = no load
0.1
-
+0.1
V
CAN Offline Bias mode;
RL = no load
2
2.5
3
V
pin CANH;
VCANH = 3 V to +27 V
55
-
-
mA
pin CANL;
VCANL = 15 V to +18 V
-
-
+55
mA
3
-
+3
mA
CAN Active mode
0.5
0.7
0.9
V
CAN Offline mode
0.4
0.7
1.15
V
CAN Active mode
4[3]
-
+0.5
V
CAN Offline/Offline Bias modes
4[3]
-
+0.4
V
0.9
-
9.0[3]
V
1.15
-
9.0[3]
V
1
30
60
mV
VTXsym = VCANH + VCANL;
fTXD = 250 kHz, 1 MHz or 2.5 MHz;
CSPLIT = 4.7 nF
[3]
[4]
CAN Active mode (dominant);
VTXD = 0 V; VBAT > 5.5 V;
t < tto(dom)TXD
recessive; RL = no load;
VBAT > 5.5 V
VO(rec)
IO(sc)dom
recessive output voltage
dominant short-circuit output
current
CAN Active mode;
VBAT > 5.5 V; VTXD = 0 V
IO(sc)rec
recessive short-circuit output
current
VCANL = VCANH = 27 V to +32 V;
VTXD = VIO
Vth(RX)dif
differential receiver threshold
voltage
12 V VCANL +12 V;
12 V VCANH +12 V
Vrec(RX)
Vdom(RX)
12 V VCANL +12 V;
12 V VCANH +12 V
receiver recessive voltage
12 V VCANL +12 V;
12 V VCANH +12 V
receiver dominant voltage
CAN Active mode
CAN Offline/Offline Bias modes
Vhys(RX)dif
differential receiver hysteresis
voltage
UJA1166A
Product data sheet
CAN Active mode;
12 V VCANL +12 V;
12 V VCANH +12 V
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
Table 6.
Static characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; RL = R(CANH-CANL) =60 ; all voltages are defined with
respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Ri
input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
9
15
28
k
Ri
input resistance deviation
V VCANL +5 V;
V VCANH +5 V
1
-
+1
%
Ri(dif)
differential input resistance
2 V VCANL +7 V;
2 V VCANH +7 V
19
30
52
k
Ci(cm)
common-mode input
capacitance
[3]
-
-
20
pF
Ci(dif)
differential input capacitance
[3]
-
-
10
pF
IL
leakage current
5
-
+5
A
VBAT = VV1 = 0 V or
VBAT = VV1 = shorted to ground via
47 k; VCANH = VCANL = 5 V
Temperature protection
Tth(act)otp
overtemperature protection
activation threshold temperature
167
177
187
C
Tth(rel)otp
overtemperature protection
release threshold temperature
127
137
147
C
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 6.
[3]
Not tested in production; guaranteed by design.
[4]
The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 11.
aaa-034449
100
IBAT
(μA)
80
(1)
(2)
60
40
20
0
-50
-25
0
25
50
75
Tvj (°C)
100
(1) Standby Mode: CAN Offline mode, VBAT = 12 V, IV1 = 0 A.
(2) Sleep mode: CAN Offline mode, VBAT = 12 V.
Fig 6.
UJA1166A typical Standby and Sleep mode quiescent current (A)
UJA1166A
Product data sheet
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; RL = R(CANH-CANL) = 60 ; C(CANH-CANL) = 100 pF; all
voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless
otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ Max Unit
from VBAT exceeding the power-on
detection threshold until VV1 > 90 %
undervoltage threshold; CV1 = 4.7 F
-
2.8
4.7
ms
6
-
54
s
180
-
440
ms
2.5
-
13.5 s
21
-
36
s
7
-
42
s
Supply; pins V1 and VIO
tstartup
start-up time
td(uvd)
undervoltage detection delay time
td(uvd-sleep)
delay time from undervoltage
detection to sleep mode
from undervoltage detection on VIO
until UJA1166A forced to Sleep mode
Mode control: pin SLPN
tfltr(sleep)
sleep filter time
td(sleep)
sleep delay time
minimum LOW time to trigger a
transition to Sleep mode
Pin WAKE
tdet(wake)
wake-up detection time
CAN transceiver timing; pins CANH, CANL, TXD and RXD
td(TXD-busdom)
delay time from TXD to bus dominant
[2]
-
80
-
ns
td(TXD-busrec)
delay time from TXD to bus recessive
[2]
-
80
-
ns
delay time from bus dominant to RXD
[2]
-
105 -
ns
delay time from bus recessive to RXD
[2]
-
120 -
ns
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
tbit(TXD) = 200 ns
[3]
-
-
255
ns
td(TXDH-RXDH)
delay time from TXD HIGH to RXD
HIGH
tbit(TXD) = 200 ns
[3]
-
-
255
ns
tbit(bus)
transmitted recessive bit width
tbit(TXD) = 500 ns
[3]
435
-
530
ns
tbit(TXD) = 200 ns
[3]
155
-
210
ns
tbit(TXD) = 500 ns
[3]
400
-
550
ns
tbit(TXD) = 200 ns
[3]
120
-
220
ns
tbit(TXD) = 500 ns
65
-
+40
ns
tbit(TXD) = 200 ns
45
-
+15
ns
first pulse (after first recessive) for
wake-up on pins CANH and CANL;
CAN Offline mode
0.5
-
1.8
s
second pulse for wake-up on pins
CANH and CANL
0.5
-
1.8
s
first pulse for wake-up on pins CANH
and CANL; CAN Offline mode
0.5
-
1.8
s
second pulse (after first dominant) for
wake-up on pins CANH and CANL
0.5
-
1.8
s
td(busdom-RXD)
td(busrec-RXD)
tbit(RXD)
trec
twake(busdom)
twake(busrec)
bit time on pin RXD
receiver timing symmetry
bus dominant wake-up time
bus recessive wake-up time
tto(wake)bus
bus wake-up time-out time
between first and second dominant
pulses; CAN Offline mode
0.8
-
10
ms
tto(dom)TXD
TXD dominant time-out time
CAN Active mode; VTXD = 0 V
2.7
-
3.3
ms
UJA1166A
Product data sheet
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
Table 7.
Dynamic characteristics …continued
Tvj = 40 C to +150 C; VBAT = 4.5 V to 28 V; VIO = 2.85 V to 5.5 V; RL = R(CANH-CANL) = 60 ; C(CANH-CANL) = 100 pF; all
voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless
otherwise specified.[1]
Symbol
Parameter
Conditions
Min
Typ Max Unit
tto(silence)
bus silence time-out time
recessive time measurement started
in all CAN modes
0.95
-
1.17 s
td(busact-bias)
delay time from bus active to bias
-
-
200
s
tstartup(CAN)
CAN start-up time
when switching to Active mode
(CTS = HIGH)
-
-
220
s
delay before CAN transceiver is
activated after the UJA1166A enters
Normal mode
-
-
320
s
Mode transition
td(act)norm
normal mode activation delay time
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[2]
See Figure 7 and Figure 10.
[3]
See Figure 8 and Figure 10.
HIGH
70 %
TXD
30 %
LOW
CANH
CANL
dominant
0.9 V
VO(dif)
0.5 V
recessive
HIGH
70 %
RXD
30 %
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
aaa-029311
Fig 7.
UJA1166A
Product data sheet
CAN transceiver timing diagram
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UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
70 %
TXD
30 %
30 %
td(TXDL-RXDL)
5 x tbit(TXD)
tbit(TXD)
0.9 V
VO(dif)
0.5 V
tbit(bus)
70 %
RXD
30 %
td(TXDH-RXDH)
tbit(RXD)
aaa-029312
Fig 8.
UJA1166A
Product data sheet
Loop delay symmetry timing diagram
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UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
11. Application information
11.1 Simplified application diagram
BAT
3 V LDO
22 μF
47 nF
(4)
BAT
10 kΩ
INH
WAKE
VIO
VCC
10 nF
MICROCONTROLLER
CTS
V1
(1)
UJA1166A
other on-board
external load
RF(3)
RXD
GND
VBAT
VIO
INH
TXD
VCC
CANH
RT (2)
standard
μC ports
RXD_1
TXD_1
CANL
RT (2)
e.g.
4.7 nF
10 kΩ WAKE
10 nF
SLPN
TJA1043 STB_N
EN
GND
standard
μC ports
ERR_N
CANH
SPLIT
RT(2)
RT(2)
RXD
RXD_2
TXD
TXD_2
GND
CANL
e.g.
4.7 nF
aaa-025797
(1) Actual capacitance value must be a least 1.76 F with 5 V DC offset (recommended capacitor value is 6.8 F).
(2) For bus line end nodes, RT = 60 in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’
termination of e.g. RT = 1.3 k can be used, if required by the OEM.
(3) Recommended value for RF < 1 k.
(4) Diode only needed if RF > 2 k.
Fig 9.
Typical application using the UJA1166A
UJA1166A
Product data sheet
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NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
12. Test information
TXD
CANH
RL
60 Ω
RXD
CL
100 pF
CANL
15 pF
aaa-030850
Fig 10. Timing test circuit for CAN transceiver
TXD
CANH
30 Ω
fTXD
CSPLIT
4.7 nF
RXD
30 Ω
CANL
aaa-030851
Fig 11. Test circuit for measuring transceiver driver symmetry
12.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for
integrated circuits, and is suitable for use in automotive applications.
UJA1166A
Product data sheet
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Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
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UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
13. Package outline
HVSON14: plastic, thermal enhanced very thin small outline package; no leads;
14 terminals; body 3 x 4.5 x 0.85 mm
SOT1086-2
X
B
D
A
A
E
A1
c
terminal 1
index area
detail X
e1
terminal 1
index area
e
v
w
b
1
7
C
C A B
C
y1 C
y
L
k
Eh
14
8
Dh
0
2.5
Dimensions
Unit
mm
5 mm
scale
A
A1
b
max 1.00 0.05 0.35
nom 0.85 0.03 0.32
min 0.80 0.00 0.29
c
D
Dh
E
Eh
0.2
4.6
4.5
4.4
4.25
4.20
4.15
3.1
3.0
2.9
e
e1
1.65
1.60 0.65
1.55
3.9
k
L
0.35 0.45
0.30 0.40
0.25 0.35
v
0.1
w
y
0.05 0.05
y1
0.1
sot1086-2
References
Outline
version
IEC
JEDEC
JEITA
SOT1086-2
---
MO-229
---
European
projection
Issue date
10-07-14
10-07-15
Fig 12. Package outline SOT1086-2 (HVSON14)
UJA1166A
Product data sheet
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Rev. 1 — 23 August 2019
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UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 13) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 8 and 9
Table 8.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 9.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
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High-speed CAN transceiver with 5 V LDO and Sleep mode
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
16. Soldering of HVSON packages
Section 15 contains a brief introduction to the techniques most commonly used to solder
Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON
leadless package ICs can found in the following application notes:
• AN10365 ‘Surface mount reflow soldering description”
• AN10366 “HVQFN application information”
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High-speed CAN transceiver with 5 V LDO and Sleep mode
17. Appendix: ISO 11898-2:201x parameter cross-reference list
Table 10.
ISO 11898-2:201x to NXP data sheet parameter conversion
ISO 11898-2:201x
NXP data sheet
Parameter
Notation
Symbol
Parameter
Single ended voltage on CAN_H
VCAN_H
VO(dom)
dominant output voltage
Single ended voltage on CAN_L
VCAN_L
Differential voltage on normal bus load
VDiff
VO(dif)
differential output voltage
VSYM
VTXsym
transmitter voltage symmetry
Absolute current on CAN_H
ICAN_H
IO(sc)dom
Absolute current on CAN_L
ICAN_L
dominant short-circuit output
current
HS-PMA dominant output characteristics
Differential voltage on effective resistance during arbitration
Optional: Differential voltage on extended bus load range
HS-PMA driver symmetry
Driver symmetry
Maximum HS-PMA driver output current
HS-PMA recessive output characteristics, bus biasing active/inactive
Single ended output voltage on CAN_H
VCAN_H
Single ended output voltage on CAN_L
VCAN_L
VO(rec)
recessive output voltage
Differential output voltage
VDiff
VO(dif)
differential output voltage
tdom
tto(dom)TXD
TXD dominant time-out time
Optional HS-PMA transmit dominant timeout
Transmit dominant timeout, long
Transmit dominant timeout, short
HS-PMA static receiver input characteristics, bus biasing active/inactive
Recessive state differential input voltage range
VDiff
Vth(RX)dif
differential receiver threshold
voltage
Vrec(RX)
receiver recessive voltage
Vdom(RX)
receiver dominant voltage
Dominant state differential input voltage range
HS-PMA receiver input resistance (matching)
Differential internal resistance
RDiff
Ri(dif)
differential input resistance
Single ended internal resistance
RCAN_H
RCAN_L
Ri
input resistance
Matching of internal resistance
MR
Ri
input resistance deviation
tLoop
td(TXDH-RXDH)
delay time from TXD HIGH to
RXD HIGH
td(TXDL-RXDL)
delay time from TXD LOW to RXD
LOW
HS-PMA implementation loop delay requirement
Loop delay
Optional HS-PMA implementation data signal timing requirements for use with bit rates above 1 Mbit/s up to
2 Mbit/s and above 2 Mbit/s up to 5 Mbit/s
Transmitted recessive bit width @ 2 Mbit/s / @ 5 Mbit/s,
intended
tBit(Bus)
tbit(bus)
transmitted recessive bit width
Received recessive bit width @ 2 Mbit/s / @ 5 Mbit/s
tBit(RXD)
tbit(RXD)
bit time on pin RXD
Receiver timing symmetry @ 2 Mbit/s / @ 5 Mbit/s
tRec
trec
receiver timing symmetry
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High-speed CAN transceiver with 5 V LDO and Sleep mode
Table 10.
ISO 11898-2:201x to NXP data sheet parameter conversion
ISO 11898-2:201x
NXP data sheet
Parameter
Notation
Symbol
Parameter
VDiff
V(CANH-CANL)
voltage between pin CANH and
pin CANL
Vx
voltage on pin x
HS-PMA maximum ratings of VCAN_H, VCAN_L and VDiff
Maximum rating VDiff
General maximum rating VCAN_H and VCAN_L
VCAN_H
Optional: Extended maximum rating VCAN_H and VCAN_L VCAN_L
HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Leakage current on CAN_H, CAN_L
ICAN_H
ICAN_L
IL
leakage current
tFilter
twake(busdom)[1] bus dominant wake-up time
HS-PMA bus biasing control timings
CAN activity filter time, long
twake(busrec)[1]
bus recessive wake-up time
tWake
tto(wake)bus
bus wake-up time-out time
Timeout for bus inactivity
tSilence
tto(silence)
bus silence time-out time
Bus Bias reaction time
tBias
td(busact-bias)
delay time from bus active to bias
CAN activity filter time, short
Wake-up timeout, short
Wake-up timeout, long
[1]
tfltr(wake)bus - bus wake-up filter time, in devices with basic wake-up functionality
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18. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
UJA1166A v.1
20190823
Product data sheet
-
-
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
UJA1166A
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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21. Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.1.3
6.1.1.4
6.1.1.5
6.1.1.6
6.1.2
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.2
6.4
6.5
6.6
6.7
6.7.1
6.7.2
6.7.3
6.7.4
7
8
9
10
11
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Designed for automotive applications. . . . . . . . 1
Integrated 5 V low-drop linear voltage regulator
(V1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Power Management . . . . . . . . . . . . . . . . . . . . . 2
System control and diagnostic features . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
System controller . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 5
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 5
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 7
Hardware characterization for the UJA1166A
operating modes . . . . . . . . . . . . . . . . . . . . . . . . 7
Mode control via pin SLPN . . . . . . . . . . . . . . . . 7
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 8
Battery supply voltage (VBAT) . . . . . . . . . . . . . . 8
5 V low-drop supply voltage (V1) . . . . . . . . . . . 8
High-speed CAN transceiver . . . . . . . . . . . . . . 8
CAN operating modes . . . . . . . . . . . . . . . . . . . 8
CAN Active mode . . . . . . . . . . . . . . . . . . . . . . . 9
CAN Offline and Offline Bias modes. . . . . . . . . 9
CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . 10
CAN standard wake-up . . . . . . . . . . . . . . . . . 11
WAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VIO supply pin . . . . . . . . . . . . . . . . . . . . . . . . 11
CAN transceiver status pin (CTS). . . . . . . . . . 11
CAN fail-safe features . . . . . . . . . . . . . . . . . . 12
TXD dominant timeout . . . . . . . . . . . . . . . . . . 12
Pull-up on TXD pin . . . . . . . . . . . . . . . . . . . . . 12
Pull-down on SLPN pin. . . . . . . . . . . . . . . . . . 12
Loss of power at pin BAT . . . . . . . . . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal characteristics . . . . . . . . . . . . . . . . . 15
Static characteristics. . . . . . . . . . . . . . . . . . . . 15
Dynamic characteristics . . . . . . . . . . . . . . . . . 19
Application information. . . . . . . . . . . . . . . . . . 22
11.1
12
12.1
13
14
15
15.1
15.2
15.3
15.4
16
17
18
19
19.1
19.2
19.3
19.4
20
21
Simplified application diagram . . . . . . . . . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages. . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering. . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . .
Soldering of HVSON packages . . . . . . . . . . .
Appendix: ISO 11898-2:201x parameter
cross-reference list . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
23
23
24
25
25
25
25
25
26
27
28
30
31
31
31
31
32
32
33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2019
Document identifier: UJA1166A
UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
UJA1166A
Product data sheet
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Rev. 1 — 23 August 2019
© NXP Semiconductors N.V. 2019. All rights reserved.
34 of 35
UJA1166A
NXP Semiconductors
High-speed CAN transceiver with 5 V LDO and Sleep mode
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