UJA1167TK,118

UJA1167 Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Rev. 2 — 18 April 2014 Product data sheet 1. General description The UJA1167 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller. It also features a watchdog and a Serial Peripheral Interface (SPI). The UJA1167 can be operated in very low-current Standby and Sleep modes with bus and local wake-up capability and supports ISO 11898-6 compliant autonomous CAN biasing. The microcontroller supply is switched off in Sleep mode. The UJA1167TK version contains a battery-related high-voltage output (INH) for controlling an external voltage regulator, while the UJA1167TK/VX is equipped with a 5 V sensor supply (VEXT). The UJA1167 implements the standard CAN physical layer as defined in the current ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry are included. This implementation enables reliable communication in the CAN FD fast phase at data rates up to 2 Mbit/s. A number of configuration settings are stored in non-volatile memory, allowing the SBC to be adapted for use in a specific application. This makes it possible to configure the power-on behavior of the UJA1167 to meet the requirements of different applications. 2. Features and benefits 2.1 General  ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver  Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase  Autonomous bus biasing according to ISO 11898-6  Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller supply (V1)  Bus connections are truly floating when power to pin BAT is off 2.2 Designed for automotive applications  8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model (HBM) on the CAN bus pins  6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins, the sensor supply output VEXT and on pins BAT and WAKE  CAN bus pins short-circuit proof to 58 V UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog  Battery and CAN bus pins protected against automotive transients according to ISO 7637-3  Very low quiescent current in Standby and Sleep modes with full wake-up capability  Leadless HVSON14 package (3.0 mm  4.5 mm) with improved Automated Optical Inspection (AOI) capability and low thermal resistance  Dark green product (halogen free and Restriction of Hazardous Substances (RoHS) compliant) 2.3 Low-drop voltage regulator for 5 V microcontroller supply (V1) 5 V nominal output; 2 % accuracy 100 mA output current capability Current limiting above 150 mA On-resistance of 5  (max) Support for microcontroller RAM retention down to a battery voltage of 2 V Undervoltage reset with selectable detection thresholds: 60 %, 70 %, 80 % or 90 % of output voltage  Excellent transient response with a 4.7 F ceramic output capacitor  Short-circuit to GND/overload protection on pin V1  Turned off in Sleep mode       2.4 Power Management  Standby mode featuring very low supply current; voltage V1 remains active to maintain the supply to the microcontroller  Sleep mode featuring very low supply current with voltage V1 switched off  Remote wake-up capability via standard CAN wake-up pattern  Local wake-up via the WAKE pin  Wake-up source recognition  Local and/or remote wake-up can be disabled to reduce current consumption  High-voltage output (INH) for controlling an external voltage (UJA1167TK) 2.5 System control and diagnostic features           Mode control via the Serial Peripheral Interface (SPI) Overtemperature warning and shutdown Watchdog with independent clock source Watchdog can be operated in Window, Timeout and Autonomous modes Optional cyclic wake-up in watchdog Timeout mode Watchdog automatically re-enabled when wake-up event captured Watchdog period selectable between 8 ms and 4 s Supports remote flash programming via the CAN bus 16-, 24- and 32-bit SPI for configuration, control and diagnosis Bidirectional reset pin with variable power-on reset length to support a variety of microcontrollers  Configuration of selected functions via non-volatile memory UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 2.6 Sensor supply voltage (pin VEXT of UJA1167TK/VX)        5 V nominal output; 2 % accuracy 30 mA output current capability Current limiting above 30 mA Excellent transient response with a 4.7 F ceramic output load capacitor Protected against short-circuits to GND and to the battery High ESD robustness of 6 kV according to IEC 61000-4-2 Can handle negative voltages as low as 18 V 3. Ordering information Table 1. Ordering information Type number[1] UJA1167TK UJA1167TK/VX [1] Package Name Description Version HVSON14 plastic thermal enhanced very thin small outline package; no leads; 14 terminals; body 3  4.5  0.85 mm SOT1086-2 UJA1167TK contains a high-voltage output for controlling an external voltage regulatror; UJA1167TK/VX includes a 5 V/30 mA sensor supply. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 4. Block diagram 8-$ %$7  +,*+92/7$*(287387   ,1+9(;7 96(16256833/<   90,&52&21752//(56833/5HVHW256WDQGE\256OHHS25 1RUPDO &0& @ WWWRVLOHQFH IURPDOOPRGHV W!WWRVLOHQFH 1RUPDO &0&  &$1EXVZDNHXS25 1RUPDO &0&  99 >5HVHW256WDQGE\256OHHS25 1RUPDO &0& @ W!WWRVLOHQFH 2II25 2YHUWHPS25 9%$79XYG&$1 &$12IIOLQH WUDQVPLWWHURII UHFHLYHURII 5;'ZDNHXSLQW &$1+&$1/WHUPLQDWHG WR*1' &$12II WUDQVPLWWHURII UHFHLYHURII 5;'ZDNHXSLQW &$1+&$1/IORDWLQJ OHDYLQJ2II2YHUWHPS 9%$7!9XYU&$1 DDD (1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode or CAN Listen-only mode if pin TXD is held LOW (e.g. by a short-circuit to GND) Fig 5. CAN transceiver state machine (with FNMC = 0) 6.7.2 CAN standard wake-up If the CAN transceiver is in Offline mode and CAN wake-up is enabled (CWE = 1), the UJA1167 will monitor the bus for a wake-up pattern. A filter at the receiver input prevents unwanted wake-up events occurring due to automotive transients or EMI. A dominant-recessive-dominant wake-up pattern must be transmitted on the CAN bus within the wake-up timeout time (tto(wake)) to pass the wake-up filter and trigger a wake-up event (see Figure 6; note that additional pulses may occur between the recessive/dominant phases). The recessive and dominant phases must last at least twake(busrec) and twake(busdom), respectively. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog dominant tdom ≥ twake(busdom) recessive dominant trec ≥ twake(busrec) tdom ≥ twake(busdom) twake < tto(wake) CAN wake-up 015aaa267 Fig 6. CAN wake-up timing When a valid CAN wake-up pattern is detected on the bus, wake-up bit CW in the Transceiver event status register is set (see Table 22) and pin RXD is driven LOW. If the SBC was in Sleep mode when the wake-up pattern was detected, V1 is enabled to supply the microcontroller and the SBC switches to Standby mode via Reset mode. 6.7.3 CAN control and Transceiver status registers Table 14. Bit Symbol Access Value 7:2 reserved R/W 1:0 CMC R/W Table 15. CAN transceiver operating mode selection (available when UJA1167 is in Normal mode; MC = 111): 00 Offline mode 01 Active mode (when the SBC is in Normal mode); V1/CAN undervoltage detection active 10 Active mode (when the SBC is in Normal mode); V1/CAN undervoltage detection disabled 11 Listen-only mode Transceiver status register (address 22h) Symbol Access Value Description 7 CTS R 0 CAN transceiver not in Active mode 1 CAN transceiver in Active mode 6:4 reserved R - 3 CBSS R 0 CAN bus active (communication detected on bus) 1 CAN bus inactive (for longer than tto(silence)) 2 reserved R - 1 VCS[1] R 0 the output voltage on V1 is above the 90 % threshold 1 the output voltage on V1 is below the 90 % threshold 0 no TXD dominant timeout event detected 1 CAN transmitter disabled due to a TXD dominant timeout event [1] Product data sheet Description - Bit 0 UJA1167 CAN control register (address 20h) CFS R Only active when CMC = 01. All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 23 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 6.8 CAN fail-safe features 6.8.1 TXD dominant timeout A TXD dominant time-out timer is started when pin TXD is forced LOW while the transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than the TXD dominant time-out time (tto(dom)TXD), the transmitter is disabled, releasing the bus lines to recessive state. This function prevents a hardware and/or software application failure from driving the bus lines to a permanent dominant state (blocking all network communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH. The TXD dominant time-out time also defines the minimum possible bit rate of 15 kbit/s. When the TXD dominant time-out time is exceeded, a CAN failure event is captured (CF = 1; see Table 22), if enabled (CFE = 1; see Table 26). In addition, the status of the TXD dominant timeout can be read via the CFS bit in the Transceiver status register (Table 15) and bit CTS is cleared. 6.8.2 Pull-up on TXD pin Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state in case the pin is left floating. 6.8.3 V1 undervoltage event A CAN failure event is captured (CF = 1), if enabled, when the supply to the CAN transceiver (V1) falls below 90 % of its nominal value. In addition, status bit VCS is set to 1. 6.8.4 Loss of power at pin BAT A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No reverse currents will flow from the bus. 6.9 Local wake-up via WAKE pin Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register (see Table 27). A wake-up event is triggered by a LOW-to-HIGH (if WPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that don’t make use of the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND to ensure optimal EMI performance. Table 16. WAKE status register (address 4Bh) Bit Symbol Access Value 7:2 reserved R - 1 WPVS R 0 reserved R Description WAKE pin status: 0 voltage on WAKE pin below switching threshold (Vth(sw)) 1 voltage on WAKE pin above switching threshold (Vth(sw)) - While the SBC is in Normal mode, the status of the voltage on pin WAKE can always be read via bit WPVS. Otherwise, WPVS is only valid if local wake-up is enabled (WPRE = 1 and/or WPFE = 1). UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 24 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 6.10 Wake-up and interrupt event diagnosis via pin RXD Wake-up and interrupt event diagnosis in the UJA1167 is intended to provide the microcontroller with information on the status of a range of features and functions. This information is stored in the event status registers (Table 20 to Table 22) and is signaled on pin RXD, if enabled. A distinction is made between regular wake-up events and interrupt events (at least one regular wake-up source must be enabled to allow the UJA1167 to switch to Sleep mode; see Section 6.1.1.3). Table 18. Table 17. Regular events Symbol Event Power-on Description CW CAN wake-up disabled WPR rising edge on WAKE disabled pin a rising-edge wake-up was detected on pin WAKE WPF falling edge on WAKE disabled pin a falling-edge wake-up was detected on pin WAKE a CAN wake-up event was detected while the transceiver was in CAN Offline mode. Diagnostic events Symbol Event Power-on Description PO power-on always enabled the UJA1167 has exited Off mode (after battery power has been restored/connected) OTW overtemperature warning disabled the IC temperature has exceeded the overtemperature warning threshold (not in Sleep mode) SPIF SPI failure disabled SPI clock count error (only 16-, 24- and 32-bit commands are valid), illegal WMC, NWP or MC code or attempted write access to locked register (not in Sleep mode) WDF watchdog failure always enabled watchdog overflow in Window or Timeout mode or watchdog triggered too early in Window mode; a system reset is triggered immediately in response to a watchdog failure in Window mode; when the watchdog overflows in Timeout mode, a system reset is only performed if a WDF is already pending (WDF = 1) VEXTO[1] VEXT overvoltage disabled VEXT overvoltage detected VEXTU[1] VEXT undervoltage disabled VEXT undervoltage detected V1U V1 undervoltage disabled voltage on V1 has dropped below the 90 % undervoltage threshold when V1 is active (event is not captured in Sleep mode because V1 is off). V1U event capture is independent of the setting of bits V1RTC. CBS CAN bus silence disabled no activity on CAN bus for tto(silence) (detected only when CBSE = 1 while bus active) CF CAN failure disabled one of the following CAN failure events detected: - CAN transceiver deactivated due to a V1 undervoltage - CAN transceiver deactivated due to a dominant clamped TXD (not in Sleep mode) [1] UJA1167TK/VX only. PO and WDF interrupts are always captured. Wake-up and interrupt detection can be enabled/disabled for the remaining events individually via the event capture enable registers (Table 24 to Table 26). UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 25 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog If an event occurs while the associated event capture function is enabled, the relevant event status bit is set. If the transceiver is in CAN Offline mode with V1 active (SBC Normal or Standby mode), pin RXD is forced LOW to indicate that a wake-up or interrupt event has been detected. If the UJA1167 is in sleep mode when the event occurs, the microcontroller supply, V1, is activated and the SBC switches to Standby mode (via Reset mode). The microcontroller can monitor events via the event status registers. An extra status register, the Global event status register (Table 19), is provided to help speed up software polling routines. By polling the Global event status register, the microcontroller can quickly determine the type of event captured (system, supply, transceiver or WAKE pin) and then query the relevant table (Table 20, Table 21, Table 22 or Table 23 respectively). After the event source has been identified, the status flag should be cleared (set to 0) by writing 1 to the relevant bit (writing 0 will have no effect). A number of status bits can be cleared in a single write operation by writing 1 to all relevant bits. It is strongly recommended to clear only the status bits that were set to 1 when the status registers were last read. This precaution ensures that events triggered just before the write access are not lost. 6.10.1 Interrupt/wake-up delay If interrupt or wake-up events occur very frequently while the transceiver is in CAN Offline mode, they can have a significant impact on the software processing time (because pin RXD is repeatedly driven LOW, requiring a response from the microcontroller each time an interrupt/wake-up is generated). The UJA1167 incorporates an event delay timer to limit the disturbance to the software. When one of the event capture status bits is cleared, pin RXD is released (HIGH) and a timer is started. If further events occur while the timer is running, the relevant status bits are set. If one or more events are pending when the timer expires after td(event), pin RXD goes LOW again to alert the microcontroller. In this way, the microcontroller is interrupted once to process a number of events rather than several times to process individual events. If all events are cleared while the timer is running, RXD remains HIGH after the timer expires, since there are no pending events. The event capture registers can be read at any time. The event capture delay timer is stopped immediately when pin RSTN goes low (triggered by a HIGH-to-LOW transition on the pin). RSTN is driven LOW when the SBC enters Reset, Sleep, Overtemp and Off modes. A pending event is signaled on pin RXD when the SBC enters Sleep mode. 6.10.2 Sleep mode protection The wake-up event capture function is critical when the UJA1167 is in Sleep mode, because the SBC will only leave Sleep mode in response to a captured wake-up event. To avoid potential system deadlocks, the SBC distinguishes between regular and diagnostic events (see Section 6.10). Wake-up events (via the CAN bus or the WAKE pin) are classified as regular events; diagnostic events signal failure/error conditions or state UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 26 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog changes. At least one regular wake-up event must be enabled before the UJA1167 can switch to Sleep mode. Any attempt to enter Sleep mode while all regular wake-up events are disabled will trigger a system reset. Another condition that must be satisfied before the UJA1167 can switch to Sleep mode is that all event status bits must be cleared. If an event is pending when the SBC receives a Sleep mode command (MC = 001), it will immediately switch to Reset mode. This condition applies to both regular and diagnostic events. Sleep mode can be permanently disabled in applications where, for safety reasons, the supply voltage to the host controller must never be cut off. Sleep mode is permanently disabled by setting the Sleep control bit (SLPC) in the SBC configuration register (see Table 8) to 1. This register is located in the non-volatile memory area of the device. When SLPC = 1, a Sleep mode SPI command (MC = 001) will trigger an SPI failure event instead of a transition to Sleep mode. 6.10.3 Event status and event capture registers After an event source has been identified, the status flag should be cleared (set to 0) by writing 1 to the relevant status bit (writing 0 will have no effect). Table 19. Symbol Access Value 7:4 reserved R - 3 WPE R 0 no pending WAKE pin event 1 WAKE pin event pending at address 0x64 0 no pending transceiver event 1 transceiver event pending at address 0x63 0 no pending supply event 1 supply event pending at address 0x62 0 no pending system event 1 system event pending at address 0x61 2 1 0 TRXE SUPE SYSE Table 20. R R System event status register (address 61h) Symbol Access 7:5 reserved R - 4 PO R/W 0 no recent power-on 1 the UJA1167 has left Off mode after power-on Value Description 3 reserved R - 2 OTW R/W 0 overtemperature not detected 1 the global chip temperature has exceeded the overtemperature warning threshold (Tth(warn)otp) 0 no SPI failure detected 1 SPI failure detected 0 no watchdog failure event captured 1 watchdog failure event captured 0 Product data sheet R Description Bit 1 UJA1167 Global event status register (address 60h) Bit SPIF WDF R/W R/W All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 27 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 21. Bit Symbol Access Value 7:3 reserved R - 2 VEXTO[1] R/W 0 no VEXT overvoltage event captured 1 VEXT overvoltage event captured 0 no VEXT undervoltage event captured 1 VEXT undervoltage event captured 0 no V1 undervoltage event captured 1 V1 undervoltage event captured 1 0 [1] VEXTU[1] V1U R/W Transceiver event status register (address 63h) Bit Symbol Access Value 7:5 reserved R - 4 CBS R/W 0 CAN bus active 1 no activity on CAN bus for tto(silence) 3:2 reserved R 1 CF R/W 0 CW Table 23. Description - R/W 0 no CAN failure detected 1 CAN transceiver deactivated due to V1 undervoltage OR dominant clamped TXD 0 no CAN wake-up event detected 1 CAN wake-up event detected while the transceiver is in CAN Offline Mode WAKE pin event capture status register (address 64h) Bit Symbol Access Value 7:2 reserved R - 1 WPR R/W 0 no rising edge detected on WAKE pin 1 rising edge detected on WAKE pin 0 no falling edge detected on WAKE pin 1 falling edge detected on WAKE pin 0 WPF Table 24. R/W Symbol Access Value 7:3 reserved R - 2 OTWE R/W 0 Description System event capture enable register (address 04h) Bit 1 Product data sheet R/W Description UJA1167TK/VX only; reserved in the UJA1167TK. Table 22. UJA1167 Supply event status register (address 62h) SPIFE reserved overtemperature warning event capture: 0 overtemperature warning disabled 1 overtemperature warning enabled R/W R Description SPI failure detection: 0 SPI failure detection disabled 1 SPI failure detection enabled - All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 28 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 25. Supply event capture enable register (address 1Ch) Bit Symbol Access Value 7:3 reserved R - 2 VEXTOE[1] R/W 1 0 [1] VEXTUE[1] V1UE VEXT overvoltage detection: 0 VEXT overvoltage detection disabled 1 VEXT overvoltage detection enabled R/W VEXT undervoltage detection: 0 VEXT undervoltage detection disabled 1 VEXT undervoltage detection enabled R/W V1 undervoltage detection: 0 V1 undervoltage detection disabled 1 V1 undervoltage detection enabled UJA1167TK/VX only; reserved in the UJA1167TK. Table 26. Transceiver event capture enable register (address 23h) Bit Symbol Access Value 7:5 reserved R - 4 CBSE R/W 3:2 reserved R 1 CFE R/W 0 CWE Table 27. Description CAN bus silence detection: 0 CAN bus silence detection disabled 1 CAN bus silence detection enabled CAN failure detection 0 CAN failure detection disabled 1 CAN failure detection enabled R/W CAN wake-up detection: 0 CAN wake-up detection disabled 1 CAN wake-up detection enabled WAKE pin event capture enable register (address 4Ch) Bit Symbol Access Value 7:2 reserved R - 1 WPRE R/W 0 Description WPFE Description rising-edge detection on WAKE pin: 0 rising-edge detection on WAKE pin disabled 1 rising-edge detection on WAKE pin enabled R/W falling-edge detection on WAKE pin: 0 falling-edge detection on WAKE pin disabled 1 falling-edge detection on WAKE pin enabled 6.11 Non-volatile SBC configuration The UJA1167 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. An overview of the MTPNV registers is given in Table 28. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 29 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 28. Overview of MTPNV registers Address Register Name Bit: 7 6 5 4 3 2 0x73 Start-up control (see Table 11) reserved RLC VEXTSUC reserved 0x74 SBC configuration control (see Table 8) reserved V1RTSUC FNMC SDMC 1 0 reserved SLPC 6.11.1 Programming MTPNV cells The UJA1167 must be in Forced Normal mode and the MTPNV cells must contain the factory preset values before the non-volatile memory can be reprogrammed. The UJA1167 will switch to Forced Normal mode after a reset event (e.g. pin RSTN LOW) when the MTPNV cells contain the factory preset values (since FNMC = 1). The factory presets may need to be restored before reprogramming can begin (see Section 6.11.2). When the factory presets have been restored, a system reset is generated automatically and UJA1167 switches to Forced Normal mode. This ensures that the programming cycle cannot be interrupted by the watchdog. Programming of the non-volatile memory registers is performed in two steps. First, the required values are written to addresses 0x73 and 0x74. In the second step, reprogramming is confirmed by writing the correct CRC value to the MTPNV CRC control register (see Section 6.11.1.1). The SBC starts reprogramming the MTPNV cells as soon as the CRC value has been validated. If the CRC value is not correct, reprogramming is aborted. On completion, a system reset is generated to indicate that the MTPNV cells have been reprogrammed successfully. Note that the MTPNV cells cannot be read while they are being reprogrammed. After an MTPNV programming cycle has been completed, the non-volatile memory is protected from being overwritten via a standard SPI write operation. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP; see Table 46). Bit NVMPS in the MTPNV status register (Table 29) indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow). Note that this counter is provided for information purposes only; reprogramming will not be aborted if it reaches its maximum value. An error correction code status bit, ECCS, indicates whether reprogramming was successful. Table 29. Bit Symbol Access Value Description 7:2 WRCNTS R xxxxxx write counter: contains the number of times the MTPNV cells were reprogrammed 1 ECCS R 0 no error detected during MTPNV cell programming 1 an error was detected during MTPNV cell programming 0 MTPNV memory cannot be overwritten 1[1] MTPNV memory is ready to be reprogrammed 0 [1] UJA1167 Product data sheet MTPNV status register (address 70h) NVMPS R Factory preset value. All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 30 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 6.11.1.1 Calculating the CRC value for MTP programming The cyclic redundancy check value stored in bits CRCC in the MTPNV CRC control register is calculated using the data written to registers 0x73 and 0x74. Table 30. MTPNV CRC control register (address 75h) Bit Symbol Access Value Description 7:0 CRCC R/W - CRC control data The CRC value is calculated using the data representation shown in Figure 7 and the modulo-2 division with the generator polynomial: X8 + X5 + X3 + X2 + X + 1. The result of this operation must be bitwise inverted. 7 6 1 0 7 register 0x73 Fig 7. 6 1 register 0x74 0 015aaa382 Data representation for CRC calculation The following parameters can be used to calculate the CRC value (e.g. via the Autosar method): Table 31. Parameters for CRC coding Parameter Value CRC result width 8 bits Polynomial 0x2F Initial value 0xFF Input data reflected no Result data reflected no XOR value 0xFF Alternatively, the following algorithm can be used: data = 0 // unsigned byte crc = 0xFF for i = 0 to 1 data = content_of_address(0x73 + i) EXOR crc for j = 0 to 7 if data  128 data = data * 2 // shift left by 1 data = data EXOR 0x2F else data = data * 2 // shift left by 1 next j crc = data next i crc = crc EXOR 0xFF UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 31 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 6.11.2 Restoring factory preset values Factory preset values are restored if the following conditions apply for at least td(MTPNV) during power-up: • pin RSTN is held LOW • CANH is pulled up to VBAT • CANL is pulled down to GND After the factory preset values have been restored, the SBC performs a system reset and enters Forced normal Mode. Since the CAN bus is clamped dominant, pin RXDC is forced LOW. During the factory preset restore process, this pin is forced HIGH; a falling edge on this pin caused by bit PO being set after power-on then clearly indicates that the process has been completed. Note that the write counter, WRCNTS, in the MTPNV status register is incremented every time the factory presets are restored. 6.12 Device ID A byte is reserved at address 0x7E for a UJA1167 identification code. Table 32. Identification register (address 7Eh) Bit Symbol Access Value Description 7:0 IDS[7:0] R D8h device identification code - UJA1167TK C8h device identification code -UJA1167TK/VX 6.13 Lock control register Sections of the register address area can be write-protected to protect against unintended modifications. Note that this facility only protects locked bits from being modified via the SPI and will not prevent the UJA1167 updating status registers etc. Table 33. Bit Symbol Access Value 7 reserved R 6 LK6C R/W 5 4 3 UJA1167 Product data sheet Lock control register (address 0Ah) LK5C LK4C LK3C - Description cleared for future use lock control 6: address area 0x68 to 0x6F 0 SPI write-access enabled 1 SPI write-access disabled R/W lock control 5: address area 0x50 to 0x5F 0 SPI write-access enabled 1 SPI write-access disabled R/W lock control 4: address area 0x40 to 0x4F - WAKE pin control 0 SPI write-access enabled 1 SPI write-access disabled R/W lock control 3: address area 0x30 to 0x3F 0 SPI write-access enabled 1 SPI write-access disabled All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 32 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 33. Lock control register (address 0Ah) Bit Symbol Access Value Description 2 LK2C R/W lock control 2: address area 0x20 to 0x2F - transceiver control 1 LK1C 0 LK0C 0 SPI write-access enabled 1 SPI write-access disabled R/W lock control 1: address area 0x10 to 0x1F - regulator control 0 SPI write-access enabled 1 SPI write-access disabled R/W lock control 0: address area 0x06 to 0x09 - general purpose memory 0 SPI write-access enabled 1 SPI write-access disabled 6.14 General purpose memory UJA1167 allocates 4 bytes of RAM as general purpose registers for storing user information. The general purpose registers can be accessed via the SPI at address 0x06 to 0x09 (see Table 34). 6.15 SPI 6.15.1 Introduction The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave operations. The SPI is configured for full duplex data transfer, so status information is returned when new control data is shifted in. The interface also offers a read-only access option, allowing registers to be read back by the application without changing the register content. The SPI uses four interface signals for synchronization and data transfer: • • • • SCSN: SPI chip select; active LOW SCK: SPI clock; default level is LOW due to low-power concept (pull-down) SDI: SPI data input SDO: SPI data output; floating when pin SCSN is HIGH Bit sampling is performed on the falling edge of the clock and data is shifted in/out on the rising edge, as illustrated in Figure 8. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 33 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog SCSN SCK 01 02 03 04 N–1 N sampled SDI X SDO floating X MSB MSB–1 MSB–2 MSB–3 01 LSB MSB MSB–1 MSB–2 MSB–3 01 LSB X floating 015aaa255 Fig 8. SPI timing protocol The SPI data in the UJA1167 is stored in a number of dedicated 8-bit registers. Each register is assigned a unique 7-bit address. Two bytes must be transmitted to the SBC for a single register write operation. The first byte contains the 7-bit address along with a ‘read-only’ bit (the LSB). The read-only bit must be 0 to indicate a write operation (if this bit is 1, a read operation is assumed and any data on the SDI pin is ignored). The second byte contains the data to be written to the register. 24- and 32-bit read and write operations are also supported. The register address is automatically incremented, once for a 24-bit operation and twice for a 32-bit operation, as illustrated in Figure 9. Register Address Range 0x00 0x01 0x02 0x03 0x04 ID=0x05 addr 0000101 A6 A5 A4 A3 A2 Address Bits A1 A0 0x05 0x06 data data data byte 1 0x07 0x7D 0x7F data data byte 2 data byte 3 RO x x x Read-only Bit x x x x x x x x Data Bits x x x x x x x Data Bits Fig 9. 0x7E x x x Data Bits x x x 015aaa289 SPI data structure for a write operation (16-, 24- or 32-bit) UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 34 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog During an SPI data read or write operation, the contents of the addressed register(s) is returned via pin SDO. The UJA1167 tolerates attempts to write to registers that don't exist. If the available address space is exceeded during a write operation, the data above the valid address range is ignored (without generating an SPI failure event). During a write operation, the UJA1167 monitors the number of SPI bits transmitted. If the number recorded is not 16, 24 or 32, then the write operation is aborted and an SPI failure event is captured (SPIF = 1). If more than 32 bits are clocked in on pin SDI during a read operation, the data stream on SDI is reflected on SDO from bit 33 onwards. After the UJA1167 exits Reset mode (positive edge on RSTN), an SPI read/write access must not be attempted for at least tto(SPI). Any earlier access may be ignored (without generating an SPI failure event). UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 35 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 6.15.2 Register map The addressable register space contains 128 registers with addresses from 0x00 to 0x7F. An overview of the register mapping is provided in Table 34 to Table 42. The functionality of individual bits is discussed in more detail in relevant sections of the data sheet. Table 34. Overview of primary control registers Address Register Name Bit: 7 6 0x00 Watchdog control WMC 0x01 Mode control reserved 5 4 3 1 0 OTWE SPIFE reserved FNMS SDMS WDS LK3C LK2C LK1C reserved NWP MC 0x03 Main status reserved OTWS 0x04 System event enable reserved 0x05 Watchdog status reserved 0x06 Memory 0 GPM[7:0] 0x07 Memory 1 GPM[15:8] 0x08 Memory 2 GPM[23:16] 0x09 Memory 3 GPM[31:24] 0x0A Lock control reserved LK6C Table 35. Overview of V1 and INH/VEXT and transceiver control registers Address Register Name 2 NMS LK5C RSS LK4C LK0C Bit: 7 6 5 4 3 2 1 0x10 V1 and INH/VEXT control reserved 0x1B Supply status reserved VEXTS 0x1C Supply event enable reserved VEXTOE VEXTUE V1UE 0x20 CAN control reserved CMC 0x22 Transceiver status CTS 0x23 Transceiver event enable reserved Table 36. Overview of WAKE pin control and status registers Address Register Name VEXTC 0 reserved V1RTC CBSS CBSE V1S reserved reserved VCS CFS CFE CWE Bit: 7 6 5 4 3 2 1 0 0x4B WAKE pin status reserved WPVS reserved 0x4C WAKE pin enable reserved WPRE WPFE 1 0 Table 37. Overview of event capture registers Address Register Name Bit: 7 6 0x60 Global event status reserved 0x61 System event status reserved 0x62 Supply event status reserved 0x63 Transceiver event status reserved 0x64 WAKE pin event status reserved UJA1167 Product data sheet 5 4 3 2 WPE TRXE PO reserved OTW VEXTO CBS reserved All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 SUPE SYSE SPIF WDF VEXTU V1U CF CW WPR WPF © NXP Semiconductors N.V. 2014. All rights reserved. 36 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 38. Address Overview of MTPNV status register Register Name Bit: 7 0x70 Table 39. Address MTPNV status 6 Table 40. Address Table 41. Address Register Name Table 42. Address Startup control 6 5 reserved 1 0 ECCS NVMPS 4 RLC 3 2 1 0 VEXTSUC reserved Overview of SBC configuration control register Register Name Bit: 6 5 SBC configuration control reserved 4 V1RTSUC 3 2 1 0 FNMC SDMC reserved SLPC Overview of CRC control register Register Name Bit: MTPNV CRC control 6 5 4 3 2 1 0 5 4 3 2 1 0 CRCC[7:0] Overview of Identification register Register Name Bit: 7 0x7E 2 Bit: 7 0x75 3 Overview of Startup control register 7 0x74 4 WRCNTS 7 0x73 5 Identification 6 IDS[7:0] 6.15.3 Register configuration in UJA1167 operating modes A number of register bits may change state automatically when the UJA1167 switches from one operating mode to another. This is particularly evident when the UJA1167 switches to Off mode. These changes are summarized in Table 43. If an SPI transmission is in progress when the UJA1167 changes state, the transmission is ignored (automatic state changes have priority). Table 43. Register bit settings in UJA1167 operating modes Symbol Off (power-on default) Standby Normal Sleep Overtemp Reset CBS 0 no change no change no change no change no change CBSE 0 no change no change no change no change no change CBSS 1 actual state actual state no change actual state actual state CF 0 no change no change no change no change no change CFE 0 no change no change no change no change no change CFS 0 actual state actual state actual state actual state actual state CMC 00 no change no change no change no change no change CRCC 00000000 no change no change no change no change no change CTS 0 0 actual state 0 0 0 CW 0 no change no change no change no change no change UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 37 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 43. Register bit settings in UJA1167 operating modes …continued Symbol Off (power-on default) Standby Normal Sleep Overtemp Reset CWE 0 no change no change no change no change no change ECCS actual state actual state actual state actual state actual state actual state FNMC MTPNV MTPNV MTPNV MTPNV MTPNV MTPNV FNMS 0 actual state actual state actual state actual state actual state GPMn 00000000 no change no change no change no change no change IDS 1101 1000 (TK) no change 1100 1000 (TKVX) no change no change no change no change LKnC 0 no change no change no change no change no change MC 100 100 111 001 don’t care 100 NMS 1 no change 0 no change no change no change NVMPS actual state actual state actual state actual state actual state actual state NWP 0100 no change no change no change 0100 0100 OTW 0 no change no change no change no change no change OTWE 0 no change no change no change no change no change OTWS 0 actual state actual state actual state actual state actual state PO 1 no change no change no change no change no change RLC MTPNV MTPNV MTPNV MTPNV MTPNV MTPNV RSS 00000 no change no change no change 10010 reset source SDMC MTPNV MTPNV MTPNV MTPNV MTPNV MTPNV SDMS 0 actual state actual state actual state actual state actual state SLPC MTPNV MTPNV MTPNV MTPNV MTPNV MTPNV SPIF 0 no change no change no change no change no change SPIFE 0 no change no change no change no change no change SUPE 0 no change no change no change no change no change SYSE 1 no change no change no change no change no change TRXE 0 no change no change no change no change no change V1RTC defined by V1RTSUC no change no change no change no change no change V1RTSUC MTPNV MTPNV MTPNV MTPNV MTPNV MTPNV V1S 0 actual state actual state actual state actual state actual state V1UE 0 no change no change no change no change no change V1U 0 no change no change no change no change no change VCS 0 actual state actual state actual state actual state actual state VEXTC defined by VEXTSUC no change no change no change no change no change VEXTO[1] 0 no change no change no change no change no change VEXTOE[1] 0 no change no change no change no change no change VEXTS[1] 00 actual state actual state actual state actual state actual state VEXTSUC MTPNV MTPNV MTPNV MTPNV MTPNV MTPNV VEXTU[1] 0 no change no change no change no change no change VEXTUE[1] 0 no change no change no change no change no change UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 38 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 43. Register bit settings in UJA1167 operating modes …continued Symbol Off (power-on default) Standby Normal Sleep Overtemp Reset WDF 0 no change no change no change no change no change WDS 0 actual state actual state actual state actual state actual state WMC [2] no change no change no change no change [2] WPE 0 no change no change no change no change no change WPF 0 no change no change no change no change no change WPR 0 no change no change no change no change no change WPFE 0 no change no change no change no change no change WPRE 0 no change no change no change no change no change WPVS 0 no change no change no change no change no change WRCNTS actual state actual state actual state actual state actual state actual state [1] UJA1167TK/VX only. [2] 001 if SDMC = 1; otherwise 010. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 39 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 7. Limiting values Table 44. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Vx voltage on pin x DC value voltage between pin CANH and pin CANL Vtrt transient voltage Max Unit V 0.2 +6 pins TXD, RXD, SDI, SDO, SCK, SCSN, RSTN 0.2 VV1 + 0.2 V pins INH/VEXT/WAKE 18 +40 V pin BAT 0.2 +40 V pins CANH and CANL with respect to any other pin 58 +58 V 40 +40 V 150 +100 V 6 +6 kV 8 +8 kV 4 +4 kV 2 +2 kV 100 +100 V 750 +750 V 500 +500 V 40 +150 C 55 +150 C [1] pin V1 V(CANH-CANL) Min [2] on pins CANL, CANH, WAKE, VEXT; pin BAT via reverse polarity diode and capacitor to ground VESD electrostatic discharge voltage IEC 61000-4-2 [3] on pins CANH and CANL; pin BAT with capacitor; pin WAKE with 10 nF capacitor and 10 k resistor; pin VEXT with 2.2 F capacitor [4] HBM on pins CANH, CANL [5] on pins BAT, WAKE, VEXT on any other pin [6] MM on any pin [7] CDM on corner pins on any other pin Tvj virtual junction temperature Tstg storage temperature [8] [1] When the device is not powered up, IV1 (max) = 25 mA. [2] Verified by an external test house to ensure pins can withstand ISO 7637 part 2 automotive transient test pulses 1, 2a, 3a and 3b. [3] ESD performance according to IEC 61000-4-2 (150 pF, 330 ) has been verified by an external test house; the result was equal to or better than 6 kV. [4] Human Body Model (HBM): according to AEC-Q100-002 (100 pF, 1.5 k). [5] V1 and BAT connected to GND, emulating the application circuit. [6] Machine Model (MM): according to AEC-Q100-003 (200 pF, 0.75 H, 10 ). [7] Charged Device Model (CDM): according to AEC-Q100-011 (field Induced charge; 4 pF). [8] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: Tvj = Tamb + P  Rth(j-a), where Rth(j-a) is a fixed value used in the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 40 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 8. Thermal characteristics Table 45. Symbol Rth(vj-a) [1] Thermal characteristics Parameter Conditions [1] thermal resistance from virtual junction to ambient HVSON14 Typ Unit 60 K/W According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with two inner copper layers (thickness: 35 m) and thermal via array under the exposed pad connected to the first inner copper layer (thickness: 70 m). 9. Static characteristics Table 46. Static characteristics Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply; pin BAT Vth(det)pon power-on detection threshold voltage VBAT rising 4.2 - 4.55 V Vth(det)poff power-off detection threshold voltage VBAT falling 2.8 - 3 V Vuvr(CAN) CAN undervoltage recovery voltage VBAT rising 4.5 - 5 V Vuvd(CAN) CAN undervoltage detection voltage VBAT falling 4.2 - 4.55 V IBAT battery supply current Sleep mode; MC = 001; 40 C < Tvj < 85 C; CAN Offline mode; CWE = 1; VBAT = 7 V to 18 V - 41 59 A Standby mode; MC = 100; CWE = 1; CAN Offline mode; IV1 = 0 A; VBAT = 7 V to 18 V; 40 C < Tvj < 85 C - 60 85 A additional current in CAN Offline Bias mode; 40 C < Tvj < 85 C - 46 63 A 2 3 A additional current from WAKE input; WPRE = WPFE = 1; 40 C < Tvj < 85 C UJA1167 Product data sheet Normal mode; MC = 111; CAN Active mode; CAN recessive; VTXD = VV1 - 4 7.5 mA Normal mode; MC = 111; CAN Active mode; CAN dominant; VTXD = 0 V - 46 67 mA All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 41 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 46. Static characteristics …continued Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VBAT = 5.5 V to 18 V; IV1 = 120 mA to 0 mA; VTXD = VV1 4.9 5 5.1 V VBAT = 5.65 V to 18 V; IV1 = 150 mA to 0 mA; VTXD = VV1 4.9 5 5.1 V VBAT = 5.65 V to 18 V; IV1 = 100 mA to 0 mA; VTXD = 0 V; VCANH = 0 V 4.9 5 5.1 V - - 100 mV 10 mV - 5  Voltage source: pin V1 VO Vret(RAM) output voltage RAM retention voltage difference between VBAT and VV1 VBAT = 2 V to 3 V; IV1 = 2 mA VBAT = 2 V to 3 V; IV1 = 200 A [1] R(BAT-V1) resistance between pin BAT and pin V1 VBAT = 4 V to 6 V; IV1 = 120 mA VBAT = 3 V to 4 V; IV1 = 40 mA - 2.625 -  Vuvd undervoltage detection voltage Vuvd(nom) = 90 % 4.5 - 4.75 V Vuvd(nom) = 80 % 4 - 4.25 V Vuvd(nom) = 70 % 3.5 3.75 V Vuvd(nom) = 60 % - 3 - 3.25 V Vuvr undervoltage recovery voltage 4.5 - 4.75 V IO(sc) short-circuit output current 300 - 150 mA 4.9 5 5.1 V Voltage source: VEXT (UJA1167TK/VX only) VO output voltage VBAT = 6.5 V to 18 V; IVEXT = 30 mA to 0 mA Vuvd undervoltage detection voltage 4.5 - 4.75 V Vovd overvoltage detection voltage 6.5 - 7 V IO(sc) short-circuit output current 125 - 30 mA Voltage source: INH (UJA1167TK) VO output voltage IINH = 180 A VBAT  0.8 - VBAT V Rpd pull-down resistance Sleep mode 3 4 5 M Serial peripheral interface inputs; pins SDI, SCK and SCSN Vth(sw) switching threshold voltage 0.25VV1 - 0.75VV1 V Rpd(SCK) pull-down resistance on pin SCK 40 60 80 k Rpu(SCSN) pull-up resistance on pin SCSN 40 60 80 k ILI(SDI) input leakage current on pin SDI 5 - +5 A Serial peripheral interface data output; pin SDO VOH HIGH-level output voltage IOH = 4 mA VV1  0.4 - - V VOL LOW-level output voltage IOL = 4 mA - 0.4 V UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 - © NXP Semiconductors N.V. 2014. All rights reserved. 42 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 46. Static characteristics …continued Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ILO(off) off-state output leakage current VSCSN = VV1; VO = 0 V to VV1 5 - +5 A CAN transmit data input; pin TXD Vth(sw) switching threshold voltage 0.25VV1 - 0.75VV1 V Rpu pull-up resistance 40 60 80 k CAN receive data output; pin RXD VOH HIGH-level output voltage IOH = 4 mA VV1  0.4 - - V VOL LOW-level output voltage IOL = 4 mA - - 0.4 V Rpu pull-up resistance CAN Offline mode 40 60 80 k Local wake input; pin WAKE Vth(sw)r rising switching threshold voltage 2.8 - 4.1 V Vth(sw)f falling switching threshold voltage 2.4 - 3.75 V Vhys(i) input hysteresis voltage 250 - 800 mV Ii input current - - 1.5 A pin CANH 2.75 3.5 4.5 V pin CANL 0.5 1.5 2.25 V 400 - +400 mV 0.9VV1 - 1.1VV1 V CAN Active mode (dominant); VTXD = 0 V; VV1 = 4.75 V to 5.5 V; R(CANH-CANL) = 45  to 65  1.5 - 3.0 V CAN Active mode (recessive); CAN Listen-only mode; CAN Offline mode; VTXD = VV1; R(CANH-CANL) = no load 50 - +50 mV CAN Active mode; VTXD = VV1 R(CANH-CANL) = no load 2 0.5VV1 3 V CAN Offline mode; R(CANH-CANL) = no load 0.1 - +0.1 V CAN Offline Bias/Listen-only modes; R(CANH-CANL) = no load; VV1 = 0 V 2 2.5 3 V pin CANH; VCANH = 0 V 50 - - mA pin CANL; VCANL = 5 V - - 52 mA 3 - +3 mA Tvj = 40 C to +85 C High-speed CAN bus lines; pins CANH and CANL VO(dom) dominant output voltage CAN Active mode; VTXD = 0 V Vdom(TX)sym transmitter dominant voltage symmetry Vdom(TX)sym = VV1  VCANH  VCANL; VV1 = 5 V VTXsym transmitter voltage symmetry VTXsym = VCANH + VCANL; fTXD = 250 kHz; CSPLIT = 4.7 nF VO(dif)bus VO(rec) IO(dom) IO(rec) bus differential output voltage recessive output voltage dominant output current recessive output current UJA1167 Product data sheet [1] [2] CAN Active mode; VTXD = 0 V; VV1 = 5 V VCANL = VCANH = 27 V to +32 V; VTXD = VV1 All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 43 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 46. Static characteristics …continued Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Vth(RX)dif differential receiver threshold voltage CAN Active/Listen-only modes; VCANL = VCANH = 12 V to +12 V 0.5 0.7 0.9 V CAN Offline mode; VCANL = VCANH = 12 V to +12 V 0.4 0.7 1.15 V CAN Active/Listen-only modes; VCANL = VCANH = 12 V to +12 V 50 200 400 mV Vhys(RX)dif differential receiver hysteresis voltage Ri(cm) common-mode input resistance 9 15 28 k Ri input resistance deviation 1 - +1 % Ri(dif) differential input resistance 19 30 52 k Ci(cm) common-mode input capacitance [1] - - 20 pF Ci(dif) differential input capacitance [1] - - 10 pF ILI input leakage current 5 - +5 A VCANL = VCANH = 12 V to +12 V VBAT = VV1 = 0 V or VBAT = VV1 = shorted to ground via 47 k; VCANH = VCANL = 5 V Temperature protection Tth(act)otp overtemperature protection activation threshold temperature 167 177 187 C Tth(rel)otp overtemperature protection release threshold temperature 127 137 147 C Tth(warn)otp overtemperature protection warning threshold temperature 127 137 147 C 0 - 0.2VV1 V Reset output; pin RSTN VOL LOW-level output voltage VV1 = 1.0 V to 5.5 V; pull-up resistor to VV1  900  Rpu pull-up resistance 40 60 80 k Vth(sw) switching threshold voltage 0.25VV1 - 0.75VV1 V - - 200 - MTP non-volatile memory Ncy(W)MTP number of MTP write cycles [1] Not tested in production; guaranteed by design. [2] The test circuit used to measure the bus output voltage symmetry (which includes CSPLIT) is shown in Figure 16. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 44 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 10. Dynamic characteristics Table 47. Dynamic characteristics Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit from VBAT exceeding the power-on detection threshold until VV1 exceeds the 90 % undervoltage threshold; CV1 = 4.7 F - 2.8 4.7 ms 6 - 54 s Voltage source; pin V1 tstartup start-up time td(uvd) undervoltage detection delay time td(uvd-RSTNL) delay time from undervoltage detection to RSTN LOW undervoltage on V1 - - 63 s td(buswake-VOH) delay time from bus wake-up to HIGH-level output voltage HIGH = 0.8VO(V1); IV1  100 mA - - 5 ms Voltage source; pin VEXT td(uvd) undervoltage detection delay time 6 - 39 s td(ovd) overvoltage detection delay time 6 - 39 s Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO tcy(clk) clock cycle time 250 - - ns tSPILEAD SPI enable lead time 50 - - ns tSPILAG SPI enable lag time 50 - - ns tclk(H) clock HIGH time 125 - - ns tclk(L) clock LOW time 125 - - ns tsu(D) data input set-up time 50 - - ns th(D) data input hold time 50 - - ns tv(Q) data output valid time pin SDO; CL = 20 pF - - 50 ns tWH(S) chip select pulse width HIGH pin SCSN 250 - - ns tto(SPI) SPI time-out time after leaving Reset mode - - 40 s - - 255 ns - - 350 ns CAN transceiver timing; pins CANH, CANL, TXD and RXD td(TXD-RXD) delay time from TXD to RXD RL = 60 ; CL = 100 pF; 50 % VTXD to 50 % VRXD; CRXD = 15 pF; fTXD = 250 kHz RL = 120 ; CL = 200 pF; 50 % VTXD to 50 % VRXD; CRXD = 15 pF; fTXD = 250 kHz [1] td(TXD-busdom) delay time from TXD to bus dominant - 80 - ns td(TXD-busrec) delay time from TXD to bus recessive - 80 - ns td(busdom-RXD) delay time from bus dominant to RXD - 105 - ns UJA1167 Product data sheet CRXD = 15 pF All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 45 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 47. Dynamic characteristics …continued Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit td(busrec-RXD) delay time from bus recessive to RXD CRXD = 15 pF - 120 - ns tbit(RXD) bit time on pin RXD tbit(TXD) = 500 ns 400 - 550 ns twake(busdom) bus dominant wake-up time first pulse (after first recessive) for wake-up on pins CANH and CANL; CAN Offline mode 0.5 - 3.0 s second pulse for wake-up on pins CANH and CANL 0.5 - 3.0 s first pulse for wake-up on pins CANH and CANL; CAN Offline mode 0.5 - 3.0 s second pulse (after first dominant) for wake-up on pins CANH and CANL 0.5 - 3.0 s twake(busrec) bus recessive wake-up time [2] tto(wake) wake-up time-out time between first and second dominant pulses; CAN Offline mode 570 - 1200 s tto(dom)TXD TXD dominant time-out time CAN Active mode; VTXD = 0 V 2.7 - 3.3 ms tto(silence) bus silence time-out time recessive time measurement started in all CAN modes; RL = 120  0.95 - 1.17 s td(busact-bias) delay time from bus active to bias - - 200 s tstartup(CAN) CAN start-up time - - 220 s when switching to Active mode (CTS = 1) Pin RXD: event capture timing (valid in CAN Offline mode only) td(event) event capture delay time CAN Offline mode 0.9 - 1.1 ms tblank blanking time when switching from Offline to Active/Listen-only mode - - 25 s ttrig(wd)1 watchdog trigger time 1 Normal mode; watchdog Window mode only [3] 0.45  NWP[4] 0.55  ms NWP[4] ttrig(wd)2 watchdog trigger time 2 Normal/Standby mode [5] 0.9  NWP[4] 1.11  ms NWP[4] RLC = 00 20 - 25 ms RLC = 01 10 - 12.5 ms RLC = 10 3.6 - 5 ms RLC = 11 1 - 1.5 ms 18 - - s Watchdog Pin RSTN: reset pulse width tw(rst) reset pulse width output pulse width input pulse width UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 46 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog Table 47. Dynamic characteristics …continued Tvj = 40 C to +150 C; VBAT = 3 V to 28 V; R(CANH-CANL) = 60 ; all voltages are defined with respect to ground; positive currents flow into the IC; typical values are given at VBAT = 13 V; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 50 - - s 0.9 - 1.1 ms Pin WAKE twake wake-up time MTP non-volatile memory td(MTPNV) MTPNV delay time before factory presets are restored [1] Guaranteed by design. [2] See Figure 11. [3] A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog period (or in the first half of the watchdog period). [4] The nominal watchdog period is programmed via the NWP control bits. [5] The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than ttrig(wd)2 after the start of the watchdog period (watchdog overflows). +,*+ 7;' /2: &$1+ &$1/ GRPLQDQW 9 92GLIEXV 9 UHFHVVLYH +,*+ 5;' /2: WG7;'EXVGRP WG7;'EXVUHF WGEXVGRP5;' WG7;'5;' WGEXVUHF5;' WG7;'5;' DDD Fig 10. CAN transceiver timing diagram UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 47 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog  7;'   [WELW7;' WELW7;'  5;'  WELW5;' DDD Fig 11. Loop delay symmetry timing diagram 6&61 W63,/($' W63,/$* WF\FON WFON+ WFON/ WVX' WK' W:+6 6&. 6', 06% ; /6% ; WY4 IORDWLQJ 6'2 IORDWLQJ ; 06% /6% DDD Fig 12. SPI timing diagram UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 48 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 11. Application information 11.1 Application diagram HJRIIERDUGVHQVRUVXSSO\  %$7  —) %$7  Nȍ :$.( 9 9(;7    5671  Q)   8-$7.9;   *1' 5671     &$1+ 57   9&& 0,&52 &21752//(5 6&61 6'2 VWDQGDUG —&SRUWV 6&. 6', 5;' 7;' 5;' 7;' 966 &$1/ 57  HJ Q) DDD (1) Actual capacitance value must be a least 1.76 F with 5 V DC offset (recommended capacitor value is 4.7 F) (2) For bus line end nodes, RT = 60  in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’ termination of e.g. RT = 1.3 k can be used, if required by the OEM. Fig 13. Typical application using the UJA1167TK/VX UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 49 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog HJ,1+DVFRQWUROVLJQDOIRUYROWDJHUHJXODWRU 9 %$7 —) 9 ,1+  %$7 ,1+  Nȍ  9   :$.( 5671 5671  Q)   8-$7.   *1'     &$1+ 57   9&& 0,&52 &21752//(5 6&61 6'2 VWDQGDUG —&SRUWV 6&. 6', 5;' 7;' 5;' 7;' 966 &$1/ 57  HJ Q) DDD (1) Actual capacitance value must be a least 1.76 F with 5 V DC offset (recommended capacitor value is 4.7 F) (2) For bus line end nodes, RT = 60  in order to support the ‘split termination concept’. For sub-nodes, an optional ‘weak’ termination of e.g. RT = 1.3 k can be used, if required by the OEM. Fig 14. Typical application using the UJA1167TK 11.2 Application hints Further information on the application of the UJA1167 can be found in the NXP application hints document AH1306 Application Hints - Mini high speed CAN system basis chips UJA1163 / UJA1164 / UJA1167 / UJA1168. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 50 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 12. Test information BAT RXD CANH RL SBC 15 pF TXD 100 pF CANL GND 015aaa369 Fig 15. Timing test circuit for CAN transceiver 10 1 BAT TXD CANH 13 30 Ω f = 250 kHz CSPLIT 4.7 nF SBC 4 RXD CANL 30 Ω 12 GND 2 015aaa444 Fig 16. Test circuit for measuring transceiver driver symmetry 12.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 51 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 13. Package outline +9621SODVWLFWKHUPDOHQKDQFHGYHU\WKLQVPDOORXWOLQHSDFNDJHQROHDGV WHUPLQDOVERG\[[PP 627 ; % ' $ $ ( $ F WHUPLQDO LQGH[DUHD GHWDLO; H WHUPLQDO LQGH[DUHD H Y Z E   & & $ % & \ & \ / N (K   'K   'LPHQVLRQV 8QLW PP PP VFDOH $ $ E F PD[    QRP     PLQ    ' 'K ( (K H H               N / Y        Z \   \  VRW 5HIHUHQFHV 2XWOLQH YHUVLRQ ,(& -('(& -(,7$ 627  02  (XURSHDQ SURMHFWLRQ ,VVXHGDWH   Fig 17. Package outline SOT1086-2 (HVSON14) UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 52 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 53 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 18) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 48 and 49 Table 48. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 49. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 18. UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 54 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 18. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Soldering of HVSON packages Section 15 contains a brief introduction to the techniques most commonly used to solder Surface Mounted Devices (SMD). A more detailed discussion on soldering HVSON leadless package ICs can be found in the following application notes: • AN10365 ‘Surface mount reflow soldering description” • AN10366 “HVQFN application information” UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 55 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 17. Revision history Table 50. Revision history Document ID Release date Data sheet status Change notice Supersedes UJA1167 v.2 20140418 Product data sheet - UJA1167 v.1 Modifications: • • • • • • • • • • • • • • • • • • • UJA1167 v.1 UJA1167 Product data sheet Section 1: text revised (2nd paragraph added) Section 2.1: feature added (loop delay symmetry) Table 2: table note amended Section 6.1.1.4: last paragraph added Section 6.1.1.6: text revised (3rd paragraph) Section 6.1.1.7: text revised (4th paragraph) Table 3: row CAN revised Section 6.2.2: text revised Section 6.3.1: text revised Section 6.3.2: text revised Section 6.7: text and state diagram revised Table 14: description for bits CMC revised Table 15: description for bit CTS revised Section 6.10.3: note added at beginning of section Section 6.15.1: text revised (4rd last paragraph); last paragraph added Table 47: symbols and parameters revised for pins V1 and VEXT; parameters tto(SPI) and tbit(RXD) added; additional measurement for parameter td(TXD-RXD); parameter tfltr(rst) renamed to tw(rst) and value changed; parameter values changed: twake for pin WAKE Figure 11: added Section 11.2: added Section 12.1: text updated 20130805 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 - © NXP Semiconductors N.V. 2014. All rights reserved. 56 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. UJA1167 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 57 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 58 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 20. Contents 1 2 2.1 2.2 2.3 2.4 2.5 2.6 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.1.1 6.1.1.2 6.1.1.3 6.1.1.4 6.1.1.5 6.1.1.6 6.1.1.7 6.1.1.8 6.1.2 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.3 6.3.1 6.3.2 6.3.3 6.4 6.5 6.5.1 6.5.2 6.6 6.7 6.7.1 6.7.1.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Designed for automotive applications. . . . . . . . 1 Low-drop voltage regulator for 5 V microcontroller supply (V1) . . . . . . . . . . . . . . . . 2 Power Management . . . . . . . . . . . . . . . . . . . . . 2 System control and diagnostic features . . . . . . 2 Sensor supply voltage (pin VEXT of UJA1167TK/VX) . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 System controller . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . 6 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . . 9 Forced Normal mode . . . . . . . . . . . . . . . . . . . . 9 Hardware characterization for the UJA1167 operating modes . . . . . . . . . . . . . . . . . . . . . . . 10 System control registers . . . . . . . . . . . . . . . . . 10 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Software Development mode . . . . . . . . . . . . . 14 Watchdog behavior in Window mode . . . . . . . 14 Watchdog behavior in Timeout mode . . . . . . . 14 Watchdog behavior in Autonomous mode . . . 15 System reset. . . . . . . . . . . . . . . . . . . . . . . . . . 15 Characteristics of pin RSTN . . . . . . . . . . . . . . 15 Selecting the output reset pulse width . . . . . . 16 Reset sources. . . . . . . . . . . . . . . . . . . . . . . . . 16 Global temperature protection . . . . . . . . . . . . 17 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery supply voltage (VBAT) . . . . . . . . . . . . . 17 Low-drop voltage supply for 5 V microcontroller (V1) . . . . . . . . . . . . . . . . . . . . 17 High voltage output (UJA1167TK) and external sensor supply (UJA1167TK/VX) . . . . 18 High-speed CAN transceiver . . . . . . . . . . . . . 19 CAN operating modes . . . . . . . . . . . . . . . . . . 19 CAN Active mode . . . . . . . . . . . . . . . . . . . . . . 19 6.7.1.2 6.7.1.3 6.7.1.4 6.7.2 6.7.3 6.8 6.8.1 6.8.2 6.8.3 6.8.4 6.9 6.10 CAN Listen-only mode . . . . . . . . . . . . . . . . . . CAN Offline and Offline Bias modes . . . . . . . CAN Off mode . . . . . . . . . . . . . . . . . . . . . . . . CAN standard wake-up . . . . . . . . . . . . . . . . . CAN control and Transceiver status registers CAN fail-safe features . . . . . . . . . . . . . . . . . . TXD dominant timeout . . . . . . . . . . . . . . . . . . Pull-up on TXD pin. . . . . . . . . . . . . . . . . . . . . V1 undervoltage event . . . . . . . . . . . . . . . . . . Loss of power at pin BAT . . . . . . . . . . . . . . . . Local wake-up via WAKE pin . . . . . . . . . . . . . Wake-up and interrupt event diagnosis via pin RXD . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Interrupt/wake-up delay . . . . . . . . . . . . . . . . . 6.10.2 Sleep mode protection . . . . . . . . . . . . . . . . . . 6.10.3 Event status and event capture registers. . . . 6.11 Non-volatile SBC configuration . . . . . . . . . . . 6.11.1 Programming MTPNV cells . . . . . . . . . . . . . . 6.11.1.1 Calculating the CRC value for MTP programming . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 Restoring factory preset values . . . . . . . . . . . 6.12 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 Lock control register. . . . . . . . . . . . . . . . . . . . 6.14 General purpose memory . . . . . . . . . . . . . . . 6.15 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.3 Register configuration in UJA1167 operating modes . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics . . . . . . . . . . . . . . . . . 9 Static characteristics . . . . . . . . . . . . . . . . . . . 10 Dynamic characteristics. . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . 11.1 Application diagram . . . . . . . . . . . . . . . . . . . . 11.2 Application hints . . . . . . . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . 12.1 Quality information . . . . . . . . . . . . . . . . . . . . . 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 14 Handling information . . . . . . . . . . . . . . . . . . . 15 Soldering of SMD packages . . . . . . . . . . . . . . 15.1 Introduction to soldering. . . . . . . . . . . . . . . . . 15.2 Wave and reflow soldering. . . . . . . . . . . . . . . 15.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 15.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 16 Soldering of HVSON packages . . . . . . . . . . . 20 20 21 22 23 24 24 24 24 24 24 25 26 26 27 29 30 31 32 32 32 33 33 33 36 37 40 41 41 45 49 49 50 51 51 52 53 53 53 53 53 54 55 continued >> UJA1167 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 59 of 60 UJA1167 NXP Semiconductors Mini high-speed CAN system basis chip with Standby/Sleep modes & watchdog 17 18 18.1 18.2 18.3 18.4 19 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 57 57 57 57 58 58 59 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 April 2014 Document identifier: UJA1167 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: UJA1167TK/VX,118 UJA1167TK,118