XC56L307VL150

Freescale Semiconductor Product Brief Advance Information DSP56L307PB Rev. 2, 2/2005 DSP56L307 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area EFCOP Peripheral Expansion Area Address Generation Unit Six Channel DMA Unit X Data RAM 24 K × 24 bits YAB XAB PAB DAB Y Data RAM 24 K × 24 bits YM_EB ESSI XM_EB PIO_EB HI08 PM_EB Triple Timer SCI Program RAM 16 K × 24 bits or 15 K × 24 bits and Instruction Cache 1024 × 24 bits 24-Bit DSP56300 Core Bootstrap ROM External Address Bus Switch External Bus Interface and I - Cache Control 18 Address 13 The DSP56L307 is intended for applications requiring a large amount of internal memory, such as networking and wireless infrastructure applications. The EFCOP can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolutionbased algorithms. Control DDB YDB XDB PDB GDB Internal Data Bus Switch Clock PLL Generator EXTAL XTAL RESET PINIT/NMI Program Interrupt Controller Program Decode Controller Program Address Generator Data ALU 24 × 24 + 56 →56-bit MAC Two 56-bit Accumulators 56-bit Barrel Shifter External Data Bus Switch Power Management 24 Data 5 JTAG OnCE™ DE PCAP MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1. DSP56L307 Block Diagram The Freescale DSP56L307, a member of the DSP56300 DSP family, supports network applications with general filtering operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations, enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. Like the other DSP56300 family members, the DSP56L307 uses a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1). The DSP56L307 performs at 160 million multiply-accumulates per second (MMACS), attaining 320 MMACS when the EFCOP is in use. It operates with an internal 160 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. Note: This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2001, 2005. All rights reserved. Features Features Table 1 lists the features of the DSP56L307 device. Table 1. DSP56L307 Features Feature Description High-Performance DSP56300 Core • 160 million multiply-accumulates per second (MMACS) (321 MMACS using the EFCOP in filtering applications) with a 160 MHz clock at 1.8 V core and 3.3 V I/O • Object code compatible with the DSP56000 core with highly parallel instruction set • Data arithmetic logic unit (Data ALU) with fully pipelined 24 × 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control • Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware DO loops, and fast auto-return interrupts • Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, twoand three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals • Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock with skew elimination • Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG) test access port (TAP) • Internal 24 × 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core • Operation at the same frequency as the core (up to 160 MHz) • Support for a variety of filter modes, some of which are optimized for cellular base station applications: • Real finite impulse response (FIR) with real taps • Complex FIR with complex taps • Complex FIR generating pure real or pure imaginary outputs alternately • A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16 • Direct form 1 (DFI) Infinite Impulse Response (IIR) filter • Direct form 2 (DFII) IIR filter • Four scaling factors (1, 4, 8, 16) for IIR output • Adaptive FIR filter with true least mean square (LMS) coefficient updates • Adaptive FIR filter with delayed LMS coefficient updates Enhanced Filter Coprocessor (EFCOP) • Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs • Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows six-channel home theater) • Serial communications interface (SCI) with baud rate generator • Triple timer module • Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are enabled Internal Peripherals : • 192 × 24-bit bootstrap ROM • 192 K × 24-bit RAM total • Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable: Program RAM Size Internal Memories Instruction Cache Size X Data RAM Size* Y Data RAM Size* Instruction Switch MSW1 Cache Mode 16 K × 24-bit 0 24 K × 24-bit 24 K × 24-bit disabled disabled 0/1 0/1 15 K × 24-bit 1024 × 24-bit 24 K × 24-bit 24 K × 24-bit enabled disabled 0/1 0/1 0 MSW0 48 K × 24-bit 0 8 K × 24-bit 8 K × 24-bit disabled enabled 0 47 K × 24-bit 1024 × 24-bit 8 K × 24-bit 8 K × 24-bit enabled enabled 0 0 40 K × 24-bit 0 12 K × 24-bit 12 K × 24-bit disabled enabled 0 1 39 K × 24-bit 1024 × 24-bit 12 K × 24-bit 12 K × 24-bit enabled enabled 0 1 32 K × 24-bit 0 16 K × 24-bit 16 K × 24-bit disabled enabled 1 0 31 K × 24-bit 1024 × 24-bit 16 K × 24-bit 16 K × 24-bit enabled enabled 1 0 24 K × 24-bit 0 20 K × 24-bit 20 K × 24-bit disabled enabled 1 1 23 K × 24-bit 1024 × 24-bit 20 K × 24-bit 20 K × 24-bit enabled enabled 1 1 *Includes 4 K × 24-bit shared memory (that is, memory shared by the core and the EFCOP) DSP56L307 Product Brief, Rev. 2 2 Freescale Semiconductor Target Applications Table 1. DSP56L307 Features (Continued) Feature Description External Memory Expansion Power Dissipation Packaging • Data memory expansion to two 256 K × 24-bit word memory spaces using the standard external address lines • Program memory expansion to one 256 K × 24-bit words memory space using the standard external address lines • External memory expansion port • Chip select logic for glueless interface to static random access memory (SRAMs) • Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs) up to 100 MHz operating frequency • • • • Very low-power CMOS design Wait and Stop low-power standby modes Fully static design specified to operate down to 0 Hz (dc) Optimized power management circuitry (instruction-dependent, peripheral-dependent, and modedependent) • Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions. Target Applications • • • • • Wireless and wireline infrastructure applications Multi-channel wireless local loop systems DSP resource boards High-speed modem banks Packet telephony Product Documentation The documents listed in Table 2 are required for a complete description of the DSP56L307 device and are necessary to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation updates, visit the Freescale DSP website. See the contact information on the back cover of this document. Table 2. DSP56L307 Documentation Name Description Order Number DSP56L307 Technical Data Description, features list, and specifications of the DSP56L307 DSP56L307 DSP56L307 User’s Manual Detailed functional description of the DSP56L307 memory configuration, operation, and register programming DSP56L307UM DSP56300 Family Detailed description of the DSP56300 family processor core and instruction set Manual DSP56300FM Application Notes See the DSP56L307 product website Documents describing specific applications or optimized device operation including code examples DSP56L307 Product Brief, Rev. 2 Freescale Semiconductor 3 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations not listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GMBH Technical Information Center Schatzbogen 7 81829 München, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T. Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com DSP56L307PB Rev. 2 1/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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