ML2201

FEDL2201-01 1 Semiconductor ML2201-XXX Speech Synthesizer LSI with on-chip 384K Mask ROM This version: Mar. 2000 GENERAL DESCRIPTION The ML2201 is a PCM-based speech synthesizer LSI having an on-chip 384K Mask ROM, D/A Converter and Low Pass Filter. Utilizing the serial interface enables smaller footprint packaging, which makes the chip an ideal choice for a pre-recorded message subsystem used with today’s size-critical applications. FEATURES • Sampling Frequency (Selectable for each single phrase) 4.0/5.3/6.4/8.0/10.6/12.8/16.0 kHz • On-chip 384 Kbit Mask ROM • Maximum Playback Time (At fEXTCLK = 4.096 MHz) 12.0 sec At fSAM = 4.0 kHz 6.0 sec At fSAM = 8.0 kHz 3.0 sec At fSAM = 16.0 kHz • External Clock Frequency Range * fEXTCLK = 3.5 to 4.096 MHz (Typ.) to 17.0 MHz • On-chip Phrase Control Table • Maximum Number of Phrases: 31 Phrases • Built-in 10-bit Current-Output Type D/A Converter • Built-in LPF • Packaging: 8-pin Plastic SSOP (SSOP8-P-44-0.65-K) (Product Code: ML2201-XXX MBZ060) • Power Supply Voltage: +2.0 to +5.5 V * Note: As of February 2000, ceramic oscillation on this chip is under development and thus the chip is not functional with a ceramic oscillator. The manufacturer intends to add a ceramic oscillation option to the chip. For more information on availability in commercial quantity, contact your sales representative. 1/20 FEDL2201-01 Semiconductor 1 ML2201–XXX PIN LAYOUT (TOP VIEW) ST PI GND AOUT PDWN XT XT VDD 1 2 3 4 8 7 6 5 8-Pin Plastic SSOP BLOCK DIAGRAM 16 384 Kbit ROM ST PI PDWN Reset, Power Down Test ROM 2 Kbit Timing Controller PCM Synthesizer OSC Circuit 10 10 bit DAC LPF 8 PCM data Area 378 Kbit Serial Interface 8 5 16 bit Address controller 8 Address ROM 2 Kbit (Phrase Address Table) Edit ROM 2 Kbit (Phrase Control Table) XT XT VDD GND AOUT 2/20 FEDL2201-01 Semiconductor 1 ML2201–XXX PIN DESCRIPTION Pin No. Pin Name I/O The playback trigger pin. ST The number of pulses input to the PI pin, while this pin is held “L”, determines the Phrase Address for playback. At the ST’s rising edge, the phrase address data is loaded into the LSI and playback starts. When no pulse input to PI occurs while this pin is held “L”, the LSI recognizes it as the “Stop Code” that results in stopping playback. The address input pin. 2 PI I The number of pulses input to this pin, while the ST pin is held “L”, determines the Phrase Address for playback. When 32 pulses are input, the internal counter returns to its initial value, “0”. 3 GND — The ground pin. The analog output pin. Configured as N-MOS open drain, analog signal is output in the form of change in output (attraction) current. While the PDWN pin being held “H”, this pin is sustained at 1/2 level and thus the current keeps on flowing. When shifting to standby state and shifting back to ready state from standby, the pop-noise canceller is put to work. 5 VDD — The power supply pin. Insert a 0.1 µF bypass capacitor between this pin and the GND pin. The external clock input pin. 6 XT I The ceramic resonator connection pin for ceramic oscillation option under development. Keep this pin open. 7 XT O The LSI’s operations may become unstable if this pin includes any capacitive component. The ceramic resonator connection pin for ceramic oscillation option under development. 8 PDWN I The power down pin. The LSI stays standby state while the pin being held “L”. Description 1 I 4 AOUT O 3/20 FEDL2201-01 Semiconductor 1 ML2201–XXX ABSOLUTE MAXIMUM RATINGS (GND = 0 V) Parameter Power Supply Voltage Input Voltage Storage Temperature Power Drain Allowance Symbol VDD VIN TSTG Pd Condition Ta = 25°C — Ta = 25°C Rating –0.3 to +7.0 –0.3 to VDD +0.3 –55 to +150 250 Unit V V °C mW RECOMMENDED OPERATING CONDITIONS (GND = 0 V) Parameter Symbol Condition fEXTCLK = 3.5 to 4.5 MHz Power Supply Voltage VDD fEXTCLK = 3.5 to 13.5 MHz fEXTCLK = 3.5 to 17.0 MHz Min. VDD = 2.0 to 5.5 V External Clock Frequency fEXTCLK VDD = 2.6 to 5.5 V VDD = 2.7 to 5.5 V VDD = 3.0 to 5.5 V Operating Temperature TOP — 3.5 3.5 3.5 3.5 Range +2.0 to +5.5 +2.6 to +5.5 +3.0 to +5.5 Typ. 4.096 — — — –40 to +85 Max. 4.5 13.5 14.5 17.0 °C Unit V V V MHz 4/20 FEDL2201-01 Semiconductor 1 ML2201–XXX ELECTRICAL CHARACTERISTICS DC Characteristics VDD = 2.0 to 5.5 V, GND = 0 V, fEXTCLK = 4.096 MHz, Ta = –40 to +85°C (unless otherwise specified) Parameter Symbol Condition FEXTCLK > 14.5 MHz VDD = 3.0 to 5.5 V fEXTCLK ≤ 14.5 MHz “H” Input Voltage VIH VDD = 2.7 to 5.5 V fEXTCLK ≤ 13.5 MHz VDD = 2.6 to 2.7 V fEXTCLK ≤ 4.5 MHz VDD = 2.0 to 5.5 V FEXTCLK > 14.5 MHz VDD = 3.0 to 5.5 V fEXTCLK ≤ 14.5 MHz VDD = 2.7 to 5.5 V “L” Input Voltage VIL fEXTCLK ≤ 13.5 MHz VDD = 2.6 to 2.7 V fEXTCLK ≤ 4.5 MHz VDD = 2.0 to 5.5 V “H” Input Current “L” Input Current IIH IIL VIH = VDD VIL = GND VDD = 5.5 V fEXTCLK = 4.096 MHz VDD = 3.0 V fEXTCLK = 4.096 MHz Supply Current IDD Except AOUT output current VDD = 2.0 V fEXTCLK = 4.096 MHz VDD = 5.5 V fEXTCLK = 16 MHz VDD = 3.0 V fEXTCLK = 16 MHz Standby Current IDS Ta = –40 to +70°C Ta = –40 to +85°C VDD = 2.0 to 5.5 V AOUT Output Current IAOUT At max. output current VDD = 5.5 V VDD = 3.0 V VDD = 2.0 V — — VDD × 0.15 VDD × 0.2 10 — 3.9 2.1 1.4 12.0 6.5 10 50 10.0 10.0 3.9 2.2 V Min. VDD × 0.85 VDD × 0.8 VDD × 0.85 VDD × 0.8 — Typ. — — — — — Max. — — — — VDD × 0.15 VDD × 0.2 Unit V V V V V — — V — — –10 — — — — — — — 0.5 4.3 1.4 0.5 — — — 1.7 0.9 0.5 4.6 1.8 — — — 6.8 2.7 1.2 V µA µA mA mA mA mA mA µA µA mA mA mA mA 5/20 FEDL2201-01 Semiconductor 1 ML2201–XXX AC Characteristics VDD = 2.0 to 5.5 V, GND = 0 V, fEXTCLK = 4.096 MHz, Ta = –40 to +85°C (unless otherwise specified) Parameter Clock Oscillation Duty Cycle Reset Input Time after Powering Up PDWN Hold Time after Reset Input D/A Converter Transit Time (Pop-Noise Canceller Work Time) Note *1 PDWN – ST Setup Time ST – PI Setup Time PI Pulse Width PI Cycle Time ST – PI Hold Time ST – AOUT Setup Time Note *2 Phrase Stop Time Note *2 Silence Time between Phrases Note *2 Stop ST Pulse Width Phrase ST – Phrase ST Pulse Duration Note *2 Phrase ST – Stop ST Pulse Duration Note *2 Stop ST – Phrase ST Pulse Duration Note *2 Sampling Frequency Note *3 tPDSS tSPS tPW tPC tSPH tSAS tDPS tBLN tSSW tPP tPS tSP fSAM — — — — — At fSAM = 8.0 kHz At fSAM = 8.0 kHz At fSAM = 8.0 kHz — At fSAM = 8.0 kHz At fSAM = 8.0 kHz At fSAM = 8.0 kHz — 0.35 1050 1050 500 3.9 1 1 0.35 0.7 1 — — — — — — — — — — — — — — — 2000 4000 — 1050 700 700 2000 — — — 28.0 µs µs µs µs µs µs µs µs µs µs µs µs kHz tDAR, tDAF — 60 64 68 ms Symbol fDUTY tRST tPDH Condition — — — Min. 40 10 10 Typ. 50 — — Max. 60 — — Unit % µs µs Note *1: The value changes in proportion to the external clock frequency, fEXTCLK. Note *2: The value changes in proportion to the sampling frequency, fSAM. Note *3: The sampling frequency is determined by the external clock frequency, fEXTCLK, and the dividing factor that is selected for each phrase. 6/20 FEDL2201-01 Semiconductor 1 ML2201–XXX TIMING DIAGRAMS Timing Diagram at Powering On VDD PDWN tRST tPDH ST PI Reset Power Down NOTE: The LSI’s reset operation can be performed by using a level input combination of PDWN = “L”, ST = “L” and PI = “H”. After powering on, the initial reset operation is required at the above timing. Timing Diagram at Powering Up and Standby State PDWN 1/2 IAOUT AOUT tDAR tDAF Timing Diagram for Playback PDWN ST PI ...... tSPS tPW AOUT tPDSS tPC tSAS tSPH 7/20 FEDL2201-01 Semiconductor 1 ML2201–XXX Timing Diagram on Re-addressing while Playing ST PI AOUT tDPS tBLN tPP Stop playing the current phrase Start playing the next phrase Timing Diagram on Stop Code Input ST PI tSSW AOUT tDPS tPS Stop playing the current phrase tSP 8/20 FEDL2201-01 Semiconductor 1 ML2201–XXX FUNCTIONAL DESCRIPTION Sampling Frequency You can select a sampling frequency for each phrase address from the following list while you are working on sound data. Select a sampling frequency that satisfies fSAM = 3.9 to 28.0 kHz from the values obtained with the dividing factors as shown in the Table 1 below. Table 1 Sampling Frequency Sampling Frequency At fEXTCLK = 4.096 MHz 4.0 kHz 5.3 kHz 6.4 kHz 8.0 kHz 10.6 kHz 12.8 kHz 16.0 kHz Dividing Factor fEXTCLK/1024 fEXTCLK/768 fEXTCLK/640 fEXTCLK/512 fEXTCLK/384 fEXTCLK/320 fEXTCLK/256 Memory Allocation and Playback Time Length As shown in the Figure 1, the on-chip Mask ROM of ML2201 is partitioned into four areas, Phrase Control Table, Address Control Table, Test Data area and User’s Data area. The actual data area where user’s sound data can be stored is 378 Kbit, that is the total on-chip Mask ROM capacity minus 6 Kbit. Phrase Control Table Area Address Control Table Area Test Data Area 2 Kbit 2 Kbit 2 Kbit User’s Sound Data Area 378 Kbit Figure 1 On-chip Mask ROM (384 Kbit) Memory Allocation 9/20 FEDL2201-01 Semiconductor 1 ML2201–XXX You can calculate playback time length with memory size divided by a bit rate. The following formula can be used for 8-bit PCM-based ML2201; Playback Time (sec) = Memory Size (Bit) Bit Rate (bps) = Memory Size (Bit) Ext. Clock Frequency (Hz) × 8 For example, when you store all phrases at 8.0 kHz Sampling Frequency, the maximum playback time is calculated as follows; Playback Time (sec) = (384 – 6) × 1024 Bit ≅ 6.0 sec 8000 (Hz) × 8 Bit Playback Algorithm ML2201 uses OKI Non-Linear PCM algorithm, an advanced variation of PCM. In mid-range wave-form, this algorithm has precision and quality equivalent to those of 10-bit Straight PCM. Inserting Silence In addition to playing normal recorded sound phrases, ML2201 allows you to insert silence (a silent phrase) . You can define time length of silence freely in 32 ms steps, within the range of minimum 32 ms and maximum 992 ms at fEXTCLK = 4.096 MHz. Those time length vary in proportion to the external clock frequency, fEXTCLK. Phrase Control Table The user-definable on-chip Phrase Control Table feature enables you to play back multiple phrases in a single continuous session with just the same simple control as in a regular single phrase playback. You can assign up to 8 phrases including a silent phrase (s) to a single address. This allows you to get the most out of limited memory space because you can eliminate duplicate sound data. As an example, let’s assume you want to create several similar phrases like “It will be xxxxx today”. “xxxxx” can be “sunny”, “rainy” or “cloudy”. The common words such as “It”, “will be” and “today” are created separately as an independent phrase, and phrasing order information is stored in the Phrase Control Table, as shown in the Table 2 and Figure 2.1. From the external control, simply selecting an X address causes the LSI to play multiple phrases continuously. In this example shown in the Table 2, selecting [01] address starts to play “It will be fine today, while selecting [02] “It will be rainy today”. You can also insert a silent phrase to the Phrase Control Table without consuming any memory space. Minimum Time Length of Silence 32 ms Maximum Time length of Silence 992 ms Incremental Step 32 ms 10/20 FEDL2201-01 Semiconductor 1 ML2201–XXX Table 2 Phrase Control Table Data No. 1 2 3 : 30 31 X Address (HEX) 01 02 03 : 1E 1F [01] [01] [01] [02] [02] [02] Y Address (Phrasing Order) (Up to 8 phrases) Silence Silence [04] [04] [05] [09] [03] [03] [06] [0A] [05] [03] Playback It will be (Silence) fine today. It will be (Silence) rainy today. It will be fine, later cloudy, occasionally rainy. : Phrase Control Table Data Address Control Table Data No. 1 2 3 4 5 6 7 8 X Address 01 02 03 04 05 06 07 08 1 2 3 4 5 6 7 8 Phrasing Order [01] “It” [02] “Will be” Silence (64 ms) [05] “rainy” [03] “today” — — — No. 1 2 3 4 5 6 7 8 9 10 : : : Y Address 01 02 03 04 05 06 07 08 09 0A : : : Phrase It will be today fine rainy cloudy snowy occasionally later in some area : : : Set length of silence : : : : : : 1 2 : 31 1F 31 n (32 ms × n) Length of Silence 32 ms 64 ms : 992 ms 31 1F — Time unit of silence varies in proportion to the dividing factor of fEXTCLK. Figure 2.1 Phrase Data Combination for Use with Phrase Control Table 11/20 Semiconductor 1 VDD PDWN 2nd Phrase 3rd Phrase 1st Phrase Stop Code 1st Phrase ST PI AOUT It will be rainy today 2nd Phrase 3rd Phrase It will be fine today 1st Phrase It will be fine today, It will be………. later occasionally... 1st Phrase Power Down Reset Playing Playing Power Down Shifting to Standby Playing Stop playing the earlier phrase Playing Stop playing Shifting to Standby ML2201–XXX FEDL2201-01 Figure 2.2 Timing Diagram for Playback with Phrase Control Table Function 12/20 FEDL2201-01 Semiconductor 1 ML2201–XXX External Clock Input The Figure 3 shows wiring of an external timing source. (A type of the external clock should be determined at selecting chip options.) XT XT Keep this pin open An external timing source Figure 3 External Clock Input * Note: As of July 1999, ceramic oscillation on this chip is under development and thus the chip is not functional with a ceramic oscillator. The manufacturer intends to add a ceramic oscillation option to the chip. For more information on availability in commercial quantity, contact your sales representative. 13/20 FEDL2201-01 Semiconductor 1 ML2201–XXX Low Pass Filter ML2201’s analog output goes through the built-in Low Pass Filter. The Figure 4 below shows Frequency Characteristics and the Table 3 shows Cut-Off Frequency of the LPF. The LPF’s Frequency Characteristics and Cut-Off Frequency change in proportion to the sampling frequency. No analog output directly from the D/A converter is unavailable on this chip. [dB] 20 10 0 –10 –20 –30 –40 –50 –60 –70 –80 10 100 1k 10 k [Hz] Figure 4 LPF Frequency Characteristics (fSAM = 8.0 kHz) Table 3 LPF Cut-Off Frequency Sampling Frequency (kHz) (fSAM) 4.0 5.3 6.4 8.0 10.6 12.8 16.0 Cut-Off Frequency (kHz) (fCUT) 1.2 1.6 2.0 2.5 3.2 4.0 5.0 14/20 FEDL2201-01 Semiconductor 1 ML2201–XXX CONNECTING ML2201 TO A SPEAKER DRIVER ML2201 uses a D/A converter of current-output type. To connect ML2201 to a voltage-input type speaker driver, you should convert “Changes in Current” output to “Changes in Voltage” signal. The following samples show connections of ML2201 and MSC1157 (OKI Speaker Driver Amplifier) using a resistor (RL) for conversion. SAMPLE CIRCUIT 1: AT VDD = 5.0 V, MSC1157’S Ain AMPLIFICATION = 2.5 VP-P +5 V 0.1 µF +5 V 0.1 µF 430 Ω 47 µF 10 µF VDD P1.2 P1.1 P1.0 MCU CLK XT ST PI PDWN ML2201 XT GND AOUT VCC Ain SP SP MSC1157 STBY VR 4.7 µF SEL GND SAMPLE CIRCUIT 2: AT VDD = 3.0 V, MSC1157’S Ain AMPLIFICATION = 1.5 VP-P +3 V 0.1 µF +3 V 0.1 µF 510 Ω 47 µF 10 µF VDD P1.2 P1.1 P1.0 MCU CLK XT ST PI PDWN ML2201 XT GND AOUT VCC Ain SP SP MSC1157 STBY VR 4.7 µF SEL GND 15/20 FEDL2201-01 Semiconductor 1 ML2201–XXX Co-relationship between output voltage and the value of a resistor for current-voltage conversion is shown in the figure below. You may want to use the figure as a reference in determining a proper value for the resistor. AOUT Voltage VS. AOUT Output Current at VDD = 5.0 V 6 IAOUT (mA) 5 4 3 2 1 0 0 RL = 5 kΩ RL = 500 Ω RL = 200 Ω 1 2 3 VAOUT (V) 4 5 Shifting to Standby Power Down Power Down (2) At RL = 5 kΩ Distorted waveform and obvious pop-noise shown. Power Down Shifting to Standby Playing Ready Shifting to Standby Proper waveform output shown. Playing Ready (1) At RL = 200 Ω Power Down Shifting to Standby 16/20 FEDL2201-01 Semiconductor 1 ML2201–XXX A SAMPLE CHARACTERISTICS OF D/A CONVERTER OUTPUT CURRENT A Sample Characteristics : Power Supply Voltage VS. AOUT Output Current (Ta = 25°C, VAOUT = VDD, PCM at Max. level) 8 7 6 IAOUT (mA) 5 4 3 2 1 0 0 1 2 3 VDD (V) 4 5 6 A Sample Characteristics : Operating Temperature VS. AOUT Output Current (VAOUT = VDD, PCM at Max. level) 8 7 6 IAOUT (mA) 5 4 3 2 1 0 –40 –20 0 20 Ta (°C) 40 60 80 100 VDD = 3 V VDD = 5 V A Sample Characteristics: Voltage on AOUT Pin VS. AOUT Output Current (Ta = 25°C, PCM at Max. level) 6 VDD = 5 V 5 IAOUT (mA) 4 3 VDD = 3 V 2 1 0 0 1 2 VAOUT (V) 3 4 5 17/20 FEDL2201-01 Semiconductor 1 ML2201–XXX NOTES ON USAGE Type of the Built-in D/A Converter ML2201 has the built-in current-output type D/A converter and thus the design of analog output circuit is different from the one with a voltage-output type D/A converter (e.g. MSM6650 family). ML2201’s D/A converter is designed as current attraction type with the same circuit configuration with the one used on MSM9831. So, the analog output circuit is different from MSM9800 family that uses a current discharge type D/A converter. (See the table below) Product ML2201 MSM9831 MSM9800 Family MSM6650 Family D/A Converter Type Current Output Current Output Current Output Voltage Output D/A Converter Output Circuit N-MOS Open Drain N-MOS Open Drain P-MOS Open Drain — A sample circuit of connecting ML2201 and an amplifier chip A resistor for converting current to voltage VDD ML2201 D/A Converter AOUT AMP GND Direction of flowing current A sample circuit of connecting MSM9800 family and an amplifier chip VDD Direction of flowing current D/A Converter MSM9800 Family AOUT AMP GND A resistor for converting current to voltage 18/20 FEDL2201-01 Semiconductor 1 ML2201–XXX PACKAGE DIMENSIONS (Unit: mm) SSOP8-P-44-0.65-K 5 Notes for Mounting the Surface Mount Type Packages Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.044 TYP. 1/May.12,1999 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 19/20 FEDL2201-01 Semiconductor 1 ML2201–XXX NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 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The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 20/20