ML64168

FEDL64168-01 Semiconductor ML64168 GENERAL DESCRIPTION This version: Sep. 27,1999 Previous version: Jun. 22,1999 4-Bit Microcontroller with Built-in RC Oscillation Type A/D Converter and LCD Driver The ML64168 is a low power 4-bit microcontroller incorporating the Oki's original CPU core nX-4/30. The ML64168 provides a minimum instruction execution time of 4.3µs (@700kHz). The ML64168 contains 8160-byte program memory, 512-nibble data memory, three 4-bit input-output ports, 4-bit input port, 4-bit output port, 2-channel RC oscillation type A/D converter, LCD driver for up to 120 segments, and buzzer output port. The ML64P168 is the one-time-programmable ROM version of ML64168, having one-time PROM(OTP) as internal program memory. The ML64P168 is used to evaluate the software development. APPLICATION The ML64168 is best suited for low power, high precision thermometers and hygrometers. FEATURES ∙ Processing speed Minimum instruction execution time : 4.3 µs @700 kHz 91.6 µs @32.768 kHz ∙ Clock generation circuit Low-speed clock : 32.768 kHz crystal oscillator High-speed clock : 700 kHz RC oscillator ( with an external resistor ) CPU clock is selectable as Low-speed clock / High-speed clock by software. ∙ Operating voltage : 1.5 V spec. / 3.0 V spec. ( selectable by mask option ) 1.25 to 1.70 V (1.5 V spec.) 2.0 to 3.50 V (3.0 V spec.) 2.2 to 3.50 V (3.0 V spec., 1/2duty) ∙ Operating temperature : - 40 to +85°C ∙ Memory space Internal program memory : 8160 bytes Internal data memory : 512 nibbles ∙ RC oscillation type A/D converter : 2 channels Time division 2-channel method Counter A : 1 / ( 104 × 8 ) × 1 Counter B : 1 / 214 × 1 The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 1/49 FEDL64168-01 Semiconductor ML64168 : 3 ports × 4 bits : 1 port × 4 bits : 1 port × 4 bits ( 8 out of the 34 LCD driver outputs can be used as output-only ports by mask option. ) ∙ LCD driver : 34 outputs (1) At 1/4 duty and 1/3 bias : 120 segments (max.) (2) At 1/3 duty and 1/3 bias : 93 segments (max.) (3) At 1/2 duty and 1/2 bias : 64 segments (max.) Voltage Regulator for LCD Driver (selectable by mask option) The LCD panel display is stable regardless of temporary supply voltage drop, because the voltage generated by the voltage regulator for LCD driver is supplied to the bias voltage generator as a reference voltage. LCD Operating Voltage When the voltage regulator for LCD driver is used : 3.6 V ( Duty cycle = 1/4 or 1/3 ) : 2.4 V ( Duty cycle = 1/2 ) When the voltage regulator for LCD driver is not used : 4.5 V ( Duty cycle = 1/4 or 1/3 ) : 3.0 V ( Duty cycle = 1/2 ) ∙ Buzzer driver : 1 output ( 4 output modes selectable ) ∙ Serial port : Synchronous 8-bit transfer Selectable as external clock / internal clock Selectable as MSB first / LSB first ∙ Capture circuit : 2 channels ( 32Hz, 64Hz, 128Hz, 256Hz ) ∙ Battery check circuit : 1 ( incorporated into the input-only port ) ∙ Watchdog timer ∙ Interrupt External interrupt : 2 sources Internal interrupt : 8 sources ∙ Package: 80-pin plastic QFP ( QFP80-P-1420-0.80-BK ) : ( Product name : ML64168-xxxGP ) 80-pin plastic QFP ( QFP80-P-1414-0.65-K ) : ( Product name : ML64168-xxxGA ) 80-pin plastic TQFP ( TQFP80-P-1212-0.50-K ):( Product name : ML64168-xxxTB ) Chip : ( Product name : ML64168-xxx ) xxx indicates a code number. ∙ I/O port Input-output port Input port Output port PROGRAM DEVELOPMENT ENVIRONMENT ∙ Structured Assembler : SASM64K ∙ In Circuit Emulator : EASE64168 ∙ Debugger : DT64K ∙ OTP version product : ML64P168 ( replaces the built-in program memory with one-time PROM ) 2/49 FEDL64168-01 Semiconductor ML64168 BLOCK DIAGRAM CPU CORE: nX-4/30 DATA BUS ( 8 ) IR DECORDER IR PCM PCL ROMR ROM 8160 Bytes BSR MIEF HALT TR2 TR0 TR1 PCH C ALU BA DATA BUS ( 8 ) HL XY TIMING CONTROLLER SP RAM 512 Nibbles VDD1 VDD2 VDD3 C1 C2 L0 L1 to L33 CAPR VDDI P2 P3 P4 INT VDDI P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P4.3 to ADDRESS BUS BC INT OSC1 OSC2 XT XT RST TST1 TST2 5 2CLK TBC INT BD BD SIOP BIAS RSTC LCD TST VDDL VR INTC WDT INT IN0 CS0 RS0 CRT0 RT0 IN1 CS1 RS1 RT1 P1 ADC VDDI P0.0 P0.1 P0.2 P0.3 P0 INT INT 3/49 FEDL64168-01 Semiconductor ML64168 PIN CONFIGURATION (TOP VIEW) RESET OSC1 66 OSC2 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 VDDL 31 VSS 32 33 34 35 36 37 39 38 40 TST2 TST1 P0.3 P0.2 P0.1 P0.0 P1.3 P1.2 P1.1 P1.0 XT 69 VDD 67 XT 68 80 79 78 77 76 75 74 73 72 71 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 70 L33 / P6.3 L32 / P6.2 L31 / P6.1 L30 / P6.0 L29 / P5.3 L28 / P5.2 L27 / P5.1 L26 / P5.0 L25 L24 L23 L22 L21 L20 L19 L18 L17 C2 C1 VDD3 VDD2 VDDI VDD1 RT1 CRT0 P3.3 P4.0 P4.1 P4.2 P4.3 RS0 RT0 CS0 ( GP : QFP80-P-1420-0.80-BK ) 80-Pin Plastic QFP CS1 RS1 BD IN0 IN1 4/49 FEDL64168-01 Semiconductor ML64168 PIN CONFIGURATION (TOP VIEW) ( continued ) L33 / P6.3 62 L32 / P6.2 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 25 26 27 28 29 30 31 32 33 34 35 36 37 39 24 38 40 RESET OSC1 64 66 80 79 78 77 76 75 74 73 72 71 70 69 68 67 65 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 P2.0 P2.1 P2.2 P2.3 P3.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 63 OSC2 TST2 TST1 P0.3 P0.2 P0.1 P0.0 P1.3 P1.2 P1.1 P1.0 XT L1 L0 VDD XT L31 / P6.1 L30 / P6.0 L29 / P5.3 L28 / P5.2 L27 / P5.1 L26 / P5.0 L25 L24 L23 L22 L21 L20 L19 L18 L17 C2 C1 VDD3 VDD2 VDDI RS0 RS1 BD CRT0 VDDL ( GA : QFP80-P-1414-0.65-K ) , ( TB : TQFP80-P-1212-0.50-K ) 80-Pin Plastic QFP, TQFP VDD1 CS0 RT0 CS1 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 RT1 IN0 IN1 VSS 5/49 FEDL64168-01 Semiconductor ML64168 PAD CONFIGURATION Pad Layout 60 61 Y 41 40 X 80 1 20 21 6/49 FEDL64168-01 Semiconductor ML64168 Pad Coordinates Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CARD NAME L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 BD VDDL VSS RT0 CRT0 RS0 CS0 IN0 IN1 CS1 RS1 RT1 VDD1 X (um) -2115.0 -1843.5 -1575.0 -1365.0 -1155.0 -945.0 -735.0 -525.0 -315.0 -105.0 105.0 315.0 525.0 735.0 945.0 1155.0 1365.0 1575.0 1819.5 2110.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 2390.0 Y (um) -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2555.0 -2285.0 -2005.0 -1725.0 -1495.0 -1265.0 -1035.0 -805.0 -575.0 -345.0 -115.0 115.0 345.0 575.0 805.0 1035.0 1265.0 1495.0 1725.0 2005.0 2285.0 Pad No 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CARD NAME VDDI VDD2 VDD3 C1 C2 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 OSC2 OSC1 VDD XT XT RESET TST1 TST2 P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 L0 L1 X (um) 2110.0 1845.0 1575.0 1365.0 1155.0 945.0 765.0 585.0 405.0 225.0 45.0 -135.0 -315.0 -667.0 -987.0 -1307.0 -1487.0 -1697.0 -1907.0 -2117.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 -2390.0 Y (um) 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2555.0 2550.0 2508.0 2508.0 2508.0 2508.0 2508.0 2508.0 2508.0 2285.0 2005.0 1725.0 1495.0 1265.0 1035.0 805.0 575.0 345.0 115.0 -115.0 -345.0 -575.0 -805.0 -1035.0 -1265.0 -1495.0 -1725.0 -2005.0 -2285.0 7/49 FEDL64168-01 Semiconductor ML64168 PIN DESCRIPTIONS The basic functions of each pin of the ML64168 is described in Table 1. A symbol with a slash ( / ) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For Type, “ - ” denotes a power supply pin, “ I ” an input pin, “O” an output pin, and “I/O” an inputoutput pin. Table 1 Pin Descriptions ( Basic Functions ) Pin No. GP GA, TB Function Symbol VSS VDD VDD1 VDD2 VDD3 VDDI VDDL C1 C2 XT XT OSC1 OSC2 TST1 TST2 RESET Pad No. 30 65 40 42 43 41 29 44 45 67 66 64 63 69 70 68 Type I O I O I I I 0V power supply Description 32 67 42 44 45 43 31 46 47 69 68 66 65 71 72 70 30 65 40 42 43 41 29 44 45 67 66 64 63 69 70 68 Positive power supply Bias output for driving LCD (+1.5V, +1.2V* ) Bias output for driving LCD (+3.0V, +2.4V* ) Bias output for driving LCD (+4.5V, +3.6V* ) Positive power supply for I/O port interface Positive power supply for internal logic ( An internally generated constant voltage is present at this pin. ) Pins for connecting a capacitor for generating LCD driving bias Low-speed clock oscillation input and output pins. Connect to a crystal ( 32.768kHz ). High-speed clock oscillation input and output pins. Connect to an external resistor for oscillation ( ROS ). Input pins for testing. A pull-up resistor is internally connected to these pins. System reset input pin. Setting this pin to ″ L ″ level puts this device into a reset state. Then, setting this pin to ″ H ″ level starts executing an instruction from address 0000H. Power Supply Oscillation Test Reset * When the voltage regulator for LCD driver is used. 8/49 FEDL64168-01 Semiconductor ML64168 Table 1 Pin Descriptions ( Basic Functions ) ( continued ) Function Symbol P0.0/ INT1/ CAPIN0 P0.1/ INT1/ CAPIN1 P0.2/ INT1 P0.3/ INT1/ CMP P1.0 P1.1 P1.2 P1.3 P2.0/ INT0 P2.1/ INT0 P2.2/ INT0 P2.3/ INT0 P3.0/ INT0 P3.1/ INT0 P3.2/ INT0 P3.3/ INT0/ SIN P4.0/ INT0/ SOUT P4.1/ INT0/ SPR P4.2/ INT0/ SCLK P4.3/ INT0/ MON Pin No. GP GA, TB Pad No. 75 76 Type Description 4-bit input port ( Port 0 ) Selectable as pull-up resistor input, pull-down resistor input, or high impedance input by the port 01 control register ( P01CON ). 77 78 79 80 73 74 75 76 18 19 20 21 22 23 24 25 26 27 28 29 75 76 77 78 71 72 73 74 16 17 18 19 20 21 22 23 24 25 26 27 I 77 78 71 72 73 74 16 17 I/O 18 19 20 21 22 23 24 25 I/O 26 27 4-bit input-output port ( Port 4 ) Following can be specified for each bit by the port 4 control registers 0 to 3 ( P40CON to P43CON ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) NMOS open drain output or CMOS output I/O 4-bit input-output port ( Port 2 ) Fllowing can be specified for each bit by the port 2 control registers 0 to 3 ( P20CON to P23CON ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) NMOS open drain output or CMOS output 4-bit input-output port ( Port 3 ) Following can be specified for each bit by the port 3 control registers 0 to 3 ( P30CON to P33CON ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) NMOS open drain output or CMOS output O 4-bit output port ( Port 1 ) Selectable as NMOS open drain output or CMOS output by the port 01 control register ( P01CON ). P1.0 is a high current drive output port. Ports 9/49 FEDL64168-01 Semiconductor ML64168 Table 1 Pin Descriptions ( Basic Functions ) ( continued ) Function Buzzer Symbol BD RT0 CRT0 RS0 CS0 A/D Converter IN0 RT1 RS1 CS1 IN1 Pin No. GP GA, TB Pad No. 28 31 32 33 34 35 39 38 37 36 Type O O O O O I O O O I Description Output pin for the buzzer driver. Resistance temperature sensor connection pin ( for channel 0 ) Resistance/capacitance temperature sensor connection pin ( for channel 0 ) Reference resistor connection pin ( for channel 0 ) Reference capacitor connection pin ( for channel 0 ) Input pin for RC oscillator circuit ( for channel 0 ) Resistance temperature sensor connection pin ( for channel 1 ) Reference resistor connection pin ( for channel 1 ) Reference capacitor connection pin ( for channel 1 ) Input pin for RC oscillator circuit ( for channel 1 ) 30 33 34 35 36 37 41 40 39 38 28 31 32 33 34 35 39 38 37 36 10/49 FEDL64168-01 Semiconductor ML64168 Table 1 Pin Descriptions ( Basic Functions ) ( continued ) Function Symbol L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 LCD Driver L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 / P5.0 L27 / P5.1 L28 / P5.2 L29 / P5.3 L30 / P6.0 L31 / P6.1 L32 / P6.2 L33 / P6.3 Pin No. GP GA, TB Pad No. 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Description LCD segment and common signals output pins. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 LCD segment and common signals output pins. These pins can be configured to be output ports by a mask option. 11/49 FEDL64168-01 Semiconductor ML64168 Table 2 Pin Descriptions ( Secondary Functions ) Function Symbol P2.0/ INT0 P2.1/ INT0 P2.2/ INT0 P2.3/ INT0 P3.0/ INT0 P3.1/ INT0 P3.2/ INT0 P3.3/ INT0 P4.0/ INT0 P4.1/ INT0 P4.2/ INT0 P4.3/ INT0 P0.0/ INT1 P0.1/ INT1 P0.2/ INT1 P0.3/ INT1 P0.0/ CAPIN0 P0.1/ CAPIN1 P3.3/ SIN P4.0/ SOUT P4.1/ SPR P4.2/ SCLK Pin No. GP GA, TB Pad No. 16 17 Type Description Secondary functions of P2.0 to P2.3, P3.0 to P3.3, and P4.0 to P4.3: Level-triggered external 0 interrupt input pins. The change of input signal level causes an interrupt to occur. 18 19 20 21 22 23 24 25 26 27 28 29 77 78 79 80 77 78 25 26 27 28 16 17 18 19 20 21 22 23 24 25 26 27 75 76 77 78 75 76 23 24 25 26 I 18 19 20 21 I 22 23 24 25 I 26 27 75 76 I 77 78 75 I 76 23 24 25 26 I O O I/O External Interrupt Secondary functions of P0.0 to P0.3: Level-triggered external 1 interrupt input pins. The change of input signal level causes an interrupt to occur. Capture trigger Serial port Secondary functions of P0.0: This pin is assigned the capture circuit trigger input pin of CAPR0 function . Secondary functions of P0.1: This pin is assigned the capture circuit trigger input pin of CAPR1 function . Secondary functions of P3.3: This pin is assigned the data input of a serial port. Secondary functions of P4.0: This pin is assigned the data output of a serial port. Secondary functions of P4.1: This pin is assigned the ready output of a serial port. Secondary functions of P4.2: This pin is assigned the clock input-output of a serial port. 12/49 FEDL64168-01 Semiconductor ML64168 Table 2 Pin Descriptions ( Secondary Functions ) ( continued ) Function RC Oscillation Monitor Battery Check Symbol P4.3/ MON P0.3/ CMP Pin No. GP GA, TB Pad No. 27 Type Description Secondary functions of P4.3: This pin is a monitor output of the RC oscillation clock for an A/D converter and a 700kHz RC oscillation clock for a system clock. Secondary functions of P0.3: This pin is an analog comparator input pin for battery check circuit. 29 27 O 80 78 78 I 13/49 FEDL64168-01 Semiconductor ML64168 MEMORY MAPS Program Memory Test program area 1FFFH 1FE0H 32 bytes Contents of interrupt area 8160 bytes 003BH 0038H 0035H 0032H 002FH 002CH 0029H 0026H 0023H 0020H Watchdog interrupt External 0 interrupt Serial port interrupt External 1 interrupt A/D converter interrupt 256Hz interrupt 32Hz interrupt 16Hz interrupt 1Hz interrupt 0.1Hz interrupt 003EH Interrupt area 0020H CZP area 0010H 0000H Start address 8 bits Program Memory Map Address 0000H is the instruction execution start address by the system reset. The CZP area from address 0010H to address 001FH is the start address for the CZP subroutine of 1-byte call instruction. The start address of interrupt subroutine is assigned to the interrupt address from address 0020H to 003DH. The user area has 8160 bytes of address 0000H to 1FDFH. No program can be stored in the test program area. 14/49 FEDL64168-01 Semiconductor ML64168 Data Memory The data memory area consists of 8 banks and each bank has 256 nibbles ( 256 × 4 bits ). The data RAM is assigned to BANK 6, BANK 7 and peripheral ports are assigned to BANK 0. 7FFH 780H 700H 6FFH BANK7 Data RAM area ( 256 nibbles ) 512 nibbles BANK6 Data RAM area ( 256 nibbles ) Data / Stack area ( 128 nibbles ) 600H 07FH Contents of 000H to 07FH Inaccessible area SFR area 100H 0FFH 080H 07FH 000H Unused area BANK0 000H 4 bits Data Memory Map Half the BANK 7 of Data RAM area ( 128 nibbles ) is shared by the stack area. The stack is a memory starting from address 7FFH toward the low-order addresses where 4 nibbles are used by Subroutine Call Instruction and 8 nibbles are used by an interrupt. The addresses 080H to 0FFH of BANK 0 are not assigned as the data memory, so access to these addresses has no effect. Moreover, it is impossible to access BANK 1 to BANK 5. 15/49 FEDL64168-01 Semiconductor ML64168 ABSOLUTE MAXIMUM RATINGS ( 1.5 V Spec. ) (VSS = 0 V) Parameter Power supply voltage 1 Power supply voltage 2 Power supply voltage 3 Power supply voltage 4 Power supply voltage 5 Power supply voltage 6 Input voltage 1 Input voltage 2 Input voltage 3 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 Symbol VDD1 VDD2 VDD3 VDDL VDDI VDD VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 Condition Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C VDD input, Ta = 25°C VDDI input, Ta = 25°C VDDL input, Ta = 25°C VDD1 output, Ta = 25°C VDD2 output, Ta = 25°C VDD3 output, Ta = 25°C VDD output, Ta = 25°C VDDL output, Ta = 25°C VDDI output, Ta = 25°C Ta = -40 to + 85°C QFP80-P-1420-0.80-BK Ta = -40 to + 85°C QFP80-P-1414-0.65-K Ta = -40 to + 85°C TQFP80-P-1212-0.50-K Rating -0.3 to + 2.0 -0.3 to + 4.0 -0.3 to + 5.5 -0.3 to + 2.0 -0.3 to + 5.5 -0.3 to + 2.0 -0.3 to VDD+ 0.3 -0.3 to VDDI+ 0.3 -0.3 to VDDL+ 0.3 -0.3 to VDD1+ 0.3 -0.3 to VDD2+ 0.3 -0.3 to VDD3+ 0.3 -0.3 to VDD+ 0.3 -0.3 to VDDL+ 0.3 -0.3 to VDDL+ 0.3 191 167 149 -55 to + 150 Unit V V V V V V V V V V V V V V V mW mW mW °C Power Dissipation PD Storage temperature TSTG RECOMMENDED OPERATING CONDITIONS ( 1.5V Spec. ) (VSS = 0V) Parameter Operating Temperature* Operating Voltage* External 700kHz RC Oscillator Resistance* Crystal oscillation frequency* Symbol Top VDD VDDI ROS fXT Condition Rating -40 to + 85 1.25 to 1.7 VDD to 5.25 60 to 200 30 to 35 Unit °C V V kΩ kHz * : At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.38/49. 16/49 FEDL64168-01 Semiconductor ML64168 ELECTRICAL CHARACTERISTICS (1.5 V Spec. ) DC Characteristics (1.5 V Spec. ) (VSS=0V, VDD1=VDDI=VDD=1.5V, Ta=-40 to +85°C unless otherwise specified ) Parameter VDD2 Voltage* Symbol VDD2 Condition Ca, Cb, C12=0.1µF Ca, Cb, C12=0.1µF +100% -50% +100% -50% Min. 2.8 Typ. 3.0 Max. 3.2 Unit V Measuring Circuit VDD3 Voltage* VDDL Voltage Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detection Time Internal Crystal Oscillator Capacitance External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance Internal 700kHz RC Oscillator Capacitance 700kHz RC Oscillation Frequency POR Generation Voltage POR Non-generation Voltage Battery Check Reference Voltage VRB Temperature Variation VDD3 VDDL VSTA VHOLD TSTOP CG CGEX CD COS fOSC VPOR1 VPOR2 VRB ∆VRB 4.3 0.6 1.45 1.25 0.1 10 10 10 8 80 0 1.2 0.50 4.5 1.4 15 15 12 280 0.60 -2 4.7 1.5 1000 20 30 20 16 350 0.4 1.5 0.70 - V V V V ms pF pF pF pF kHz V V V mV/°C 2 1 Oscillation start time: within 5 seconds When external CG used External resistor ROS=160kΩ VDD1 = 1.25 to 1.7V When VDD is between VPOR1 and 1.5V No POR when VDD is between VPOR2 and 1.5V Ta = 25°C - - Notes: 1.”POR” denotes Power On Reset. 2.”TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. * : At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.38/49. 17/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics (1.5 V Spec. ) (Continued ) (VSS=0V, VDD1=VDDI=VDD=1.5V, Ta=-40 to +85°C unless otherwise specified ) MeasurMax Unit Condition Min. Typ. ing . Circuit CPU in halt state 2 5 µA (700kHz RC oscillation stop) CPU in operating state 5 15 µA (700kHz RC oscillation stop) CPU in operating state 60 100 µA (700kHz RC oscillation in operation) Serial transfer, fSCK=300kHz, CPU in operating state 7 50 µA 1 (700kHz RC oscillation stop) CPU in halt state 150 230 RT0=10kΩ µA (700kHz RC oscillation stop) RC oscillation for A/D 600 900 RT0=2kΩ µA converter is in operating state Battery check circuit in operating state, CPU 10 80 in operating state µA (700kHz RC oscillation stop) Parameter Supply current 1* Supply current 2* Supply current 3 Supply current 4 Symbol IDD1 IDD2 IDD3 IDD4 Supply current 5 IDD5 Supply current 6 IDD6 * : At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.38/49. 18/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics ( 1.5 V Spec. ) ( Continued ) (VSS=0V, VDD1=VDDI=VDD=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=-40 to +85°C unless otherwise specified ) Parameter Symbol IOH1 Output current 1 ( P1.0 ) IOL1 IOH1S IOL1S Output current 2 ( P1.1 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Output current 3 ( BD ) Output current 4 ( RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) Output current 5 ( When the pins L26 to L33 are configured as output ports ) Output current 6 ( OSC2 ) IOH2 IOL2 IOH2S IOL2S IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 IOH5S IOL5S IOH6 IOL6 IOH7 IOMH7 Output current 7 ( L0 to L33 ) IOMH7S IOML7 IOML7S IOL7 Output Leakage Current ( P1.0 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) (RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) IOOH Condition VOH1 = VDDI - 0.5V VOL1 = 0.5V VDDI = 5.0V, VOH1S = VDDI - 0.5V VDDI = 5.0V, VOL1S = 0.5V VOH2 = VDDI - 0.5V VOL2 = 0.5V VDDI = 5.0V, VOH2S = VDDI - 0.5V VDDI= 5.0V, VOL2S = 0.5V VOH3 = VDD - 0.7V VOL3 = 0.7V VOH4 = VDD - 0.1V VOL4 = 0.1V VOH5 = VDDI - 0.5V VOL5 = 0.5V VDDI = 5V, VOH5S = VDDI-0.5V VDDI=5V, VOL5S=0.5V VOH6=VDD-0.5V VOL6=0.5V VOH7 = VDD3 - 0.2V (VDD3 level) VOMH7 = VDD2 + 0.2V (VDD2 level) VOMH7S = VDD2 - 0.2V (VDD2 level) VOML7 = VDD1 + 0.2V (VDD1 level) VOML7S = VDD1 - 0.2V (VDD1 level) VOL7 = VSS + 0.2V (VSS level) VOH = VDD Min. -2.1 1 -9 4 -2.1 0.2 -9 1 -1.8 0.2 -1.1 0.3 -1.5 0.1 -2.0 0.2 -2.1 0.15 4 4 4 Typ. -0.7 3 -3 8 -0.7 0.7 -3 3 -0.6 2.0 -0.6 0.6 -0.5 0.5 -1 1 -0.7 0.7 Max. -0.2 9 -1 20 -0.2 2.1 -1 9 -0.1 4.0 -0.2 1.1 -0.1 1.5 -0.2 2.0 -0.15 2.1 -4 -4 -4 0.3 mA 2 Unit Measuring Circuit µA - IOOL VOL = VSS -0.3 - - 19/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics (1.5 V Spec. ) (Continued ) ( VSS=0V, VDD1=VDDI=VDD=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=-40 to +85°C unless otherwise specified ) Parameter Symbol IIH1 Input Current 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) IIL1 IIH1S IIL1S IIH1Z IIL1Z IIH2 Input Current 2 ( IN0, IN1 ) IIH2Z IIL2Z IIL3 Input Current 3 ( OSC1 ) Input Current 4 ( RESET, TST1, TST2 ) Input Voltage 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Input Voltage 2 ( IN0, IN1, OSC1 ) Input Voltage 3 ( RESET, TST1, TST2 ) IIH3Z IIL3Z IIH4 IIL4 VIH1 VIL1 VIH1S VIL1S VIH2 VIL2 VIH3 VIL3 VDDI=5.0V VDDI=5.0V Condition VIH1 = VDDI ( when pulled down ) VIL1=VSS ( when pulled up ) VIH1=VDDI=5V ( when pulled down ) VIL1=VSS, VDDI=5V ( when pulled up ) VIH1=VDDI ( in a high impedance ) VIL1=VSS (in a high impedance ) VIH2=VDD ( when pulled down ) VIH2=VDD ( in a high impedance ) VIL2=VSS ( in a high impedance ) VIL3=VSS ( when pulled up ) VIH3=VDD ( in a high impedance ) VIL3=VSS ( in a high impedance ) VIH=VDD VIL4=VSS Min. 2 -60 70 -660 0 -1 2 0 -1 -60 0 -1 0 -1.0 1.2 0 4 0 1.2 0 1.2 0 Typ. 10 -10 250 -250 8 -18 -0.3 Max. 60 -3 660 -70 1 0 60 1 0 -5 1 0 1 -0.05 1.5 0.3 5 1 1.5 0.3 1.5 0.3 V 4 mA Unit Measuring Circuit µA 3 20/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics (1.5 V Spec. ) ( Continued ) (VSS=0V, VDD1=VDDI=VDD=1.5V, VDD2=3.0V, VDD3=4.5V, Ta=-40 to +85°C unless otherwise specified ) Parameter Hysteresis Width ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Hysteresis Width ( RESET, TST1, TST2 ) Input Pin Capacitance ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Symbol ∆VT1 ∆VT1S VDDI=5.0V Condition Min. 0.05 0.25 Typ. 0.1 1.0 Max. 0.3 1.5 Unit Measuring Circuit V 4 ∆VT2 - 0.05 0.1 0.3 CIN - - - 5 pF 1 21/49 FEDL64168-01 Semiconductor ML64168 Measuring circuit 1 RT0 OSC1 ROS OSC2 RT0 CS0 CS0 RI0 IN0 XT XT C1 C2 C12 32.768kHz Crystal VDDL VSS CL V VDD A VDD1 CA V VDD2 CB V VDD3 CC V VDDI CA,CB,CC,C12,CL ROS RT0 CS0 RI0 : : : : : 0.1µF 160kΩ 10kΩ/2kΩ 820pF 10kΩ Measuring circuit 2 OUTPUT VIH *2 *1 VIL INPUT A VSS VDD1 VDD2 VDD3 VDD VDDI VDDL 22/49 FEDL64168-01 Semiconductor ML64168 Measuring circuit 3 *3 INPUT A VSS VDD1 VDD2 VDD3 VDD VDDI VDDL Measuring circuit 4 VIH INPUT OUTPUT VDD1 VDD2 VDD3 VDD VDDI VDDL *3 VIL VSS *1 Input logic circuit to determine the specified measuring conditions. *2 Measured at the specified output pins. *3 Measured at the specified input pins. OUTPUT Waveform Monitoring 23/49 FEDL64168-01 Semiconductor ML64168 A/D Converter Characteristics ( 1.5V Spec. ) ( VSS=0V, VDD1=VDDI=VDD=1.5V, Ta=-40 to +85°C unless otherwise specified ) MeasurCondition Min. Typ. Max. Unit ing Circuit Parameter Symbol Resistor for Oscillation Input Current Limiting Resistor Oscillation Frequency RS0, RS1, RT0, RT0-1, RT1 RI0, RI1 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 CS0, CT0, CS1 ≥ 740pF 2 - - kΩ Resistor for oscillation =2 kΩ Resistor for oscillation =10 kΩ Resistor for oscillation =200 kΩ RT0, RT0-1, RT1 = 2 kΩ RT0, RT0-1, RT1 = 10 kΩ RT0, RT0-1, RT1 = 200 kΩ 1 165 41.8 2.55 3.89 0.990 0.0561 10 221 52.2 3.04 4.18 1.000 0.0584 256 60.6 3.53 4.35 1.010 0.0637 kΩ kHz kHz kHz - 5 RS•RT Oscillation Frequency Ratio (*) * Kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor in the same condition. Kfx= fOSCX(RT0 - CS0 Oscillation) fOSCX(RS0 - CS0 Oscillation) , (X = 1, 2, 3) fOSCX(RT0-1 - CS0 Oscillation) fOSCX(RS0 - CS0 Oscillation) , fOSCX(RT1 - CS1 Oscillation) fOSCX(RS1 - CS1 Oscillation) 24/49 FEDL64168-01 Semiconductor ML64168 Measuring circuit 5 (CROSC1) RT1 RI1 RS1 CS1 RI0 CS0 (CROSC0) RT0-1 CT0 RT0 RS0 Oscillation Mode Designation RT1 RS1 CS1 IN1 RESET TST1 TST2 P0.0 P0.1 P0.2 P0.3 VSS IN0 CS0 RS0 CRT0 RT0 P4.3 Frequency Measurement (fOSCX) RT0,RT0-1,RT1=2kΩ/10kΩ/200kΩ RS0,RS1=10kΩ RI0,RI1=10kΩ CS0,CT0,CS1=820pF CL=0.1µF D.U.T VDDL CL VDD VDDI 25/49 FEDL64168-01 Semiconductor ML64168 AC Characteristics (1.5 V Spec.) (Serial Interface) ( VSS=0v, VDDI=5.0V, VDD=1.5V , Ta=-40 to +85°C unless otherwise specified Parameter Symbol Condition Min. Typ. Max. ) Unit SCLK Input Fall Time SCLK Input Rise Time SCLK Input “L” Level Pulse Width SCLK Input “H” Level Pulse Width SCLK Input Cycle Time SCLK Output Cycle Time SCLK Output Cycle Time SOUT Output Delay Time SIN Input Setup Time SIN Input Hold Time tf tr tCWL tCWH tCYC tCYC1(O) tCYC2(O) tDDR tDS tDH CPU is operating at 32.768kHz CPU is operating at 700kHz CL=10pF - 0.8 0.8 2.0 0.5 0.8 15 15 30.5 1.43 - 50 50 0.4 - ns ns µs µs µs µs µs µs µs µs Synchronous communication timing ( “H” level = 4.0V, “L” level = 1.0V ) tCYC SCLK (P4.2) tr tDDR SOUT (P4.0) tDS SIN (P3.3) tDH tDS 5V tCWH tf tDDR 5V tCWL 5V 26/49 FEDL64168-01 Semiconductor ML64168 ABSOLUTE MAXIMUM RATINGS (3.0 V Spec. ) (VSS = 0V) Parameter Power supply voltage 1 Power supply voltage 2 Power supply voltage 3 Power supply voltage 4 Power supply voltage 5 Power supply voltage 6 Input voltage 1 Input voltage 2 Input voltage 3 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 Symbol VDD1 VDD2 VDD3 VDDL VDDI VDD VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 Condition Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C VDD input, Ta = 25°C VDDI input, Ta = 25°C VDDL input, Ta = 25°C VDD1 output, Ta = 25°C VDD2 output, Ta = 25°C VDD3 output, Ta = 25°C VDD output, Ta = 25°C VDDL output, Ta = 25°C VDDI output, Ta = 25°C Ta = -40 to + 85°C QFP80-P-1420-0.80-BK Ta = -40 to + 85°C QFP80-P-1414-0.65-K Ta = -40 to + 85°C TQFP80-P-1212-0.50-K Rating -0.3 to + 2.0 -0.3 to + 4.0 -0.3 to + 5.5 -0.3 to + 2.0 -0.3 to + 5.5 -0.3 to + 2.0 -0.3 to VDD+ 0.3 -0.3 to VDDI+ 0.3 -0.3 to VDDL+ 0.3 -0.3 to VDD1+ 0.3 -0.3 to VDD2+ 0.3 -0.3 to VDD3+ 0.3 -0.3 to VDD+ 0.3 -0.3 to VDDL+ 0.3 -0.3 to VDDL+ 0.3 191 167 149 -55 to + 150 Unit V V V V V V V V V V V V V V V mW mW mW °C Power Dissipation PD Storage temperature TSTG RECOMMENDED OPERATING CONDITIONS ( 3.0V Spec. ) (VSS = 0V) Parameter Operating Temperature*1 Symbol Top VDD Operating Voltage*1 VDDI External 700kHz RC oscillator Resistance*1 Crystal oscillation frequency*1 ROS fXT Condition Using LCD driver with “duty 1/2” Except using LCD driver with “duty 1/2” Rating -40 to + 85 2.2 to 3.5 2.0 to 3.5 VDD to 5.25 60 to 200 30 to 66 Unit °C V V V kΩ kHz *1: At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.38/49. 27/49 FEDL64168-01 Semiconductor ML64168 ELECTRICAL CHARACTERISTICS (3.0 V Spec.) DC Characteristics (3.0 V Spec.) (VSS=0V, VDD2=VDDI=VDD=3.0V, Ta=-40 to +85°C unless otherwise specified ) Parameter VDD1 Voltage* Symbol VDD1 Condition Ca, Cb, C12=0.1µF Ca, Cb, C12=0.1µF +100% -50% +100% -50% Min. 1.3 Typ. 1.5 Max. 1.7 Unit V Measuring Circuit VDD3 Voltage* VDDL Voltage Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detection Time Internal Crystal Oscillator Capacitance External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance Internal 700kHz RC Oscillator Capacitance 700kHz RC Oscillation Frequency POR Generation Voltage POR Non-generation Voltage Battery Check Reference Voltage VRB Temperature Variation VDD3 VDDL VSTA VHOLD TSTOP CG CGEX CD COS fOSC VPOR1 VPOR2 VRB ∆VRB 4.3 0.6 2.0 2.0 0.1 10 10 10 8 600 0 2 0.50 - 4.5 1.4 15 15 12 700 0.60 -2 4.7 2.0 1000 20 30 20 16 1000 0.7 3 0.70 - V V V V ms pF pF pF pF kHz V V V mV/°C 2 1 Oscillation start time: within 5 seconds When external CG used External resistor ROS=60kΩ VDD2 = 2.0 to 3.5V When VDD2 is between VPOR1 and 3.0V No POR when VDD2 is between VPOR2 and 3.0V Ta = 25°C Notes: 1.”POR” denotes Power On Reset. 2.”TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. *: At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.38/49. 28/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics (3.0 V Spec.) (Continued ) (VSS=0V, VDD2=VDDI=VDD=3.0V, Ta=-40 to +85°C unless otherwise specified ) Measuring Condition Min. Typ. Max. Unit Circuit CPU in halt state 2 5 µA (700kHz RC oscillation stop) CPU in operating state 5 15 µA (700kHz RC oscillation stop) CPU in operating state 400 800 µA (700kHz RC oscillation in operation) Serial transfer, fSCK=300kHz, 7 50 CPU in operating state µA 1 (700kHz RC oscillation stop) CPU in halt state 300 450 RT0=10kΩ µA (700kHz RC oscillation stop) RC oscillation for A/D 1300 2000 RT0=2kΩ µA converter is in operating state Battery check circuit in operating state, CPU in operating state 15 100 µA (700kHz RC oscillation stop) Parameter Supply current 1* Supply current 2* Supply current 3 Supply current 4 Symbol IDD1 IDD2 IDD3 IDD4 Supply current 5 IDD5 Supply current 6 IDD6 *: At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.38/49. 29/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics (3.0 V Spec.) (Continued ) ( VSS=0V, VDD1=1.5V, VDD2=VDDI=VDD=3.0V, VDD3=4.5V, Ta=-40 to +85°C unless otherwise specified ) Parameter Symbol IOH1 Output current 1 ( P1.0 ) IOL1 IOH1S IOL1S Output current 2 ( P1.1 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Output current 3 ( BD ) Output current 4 ( RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) Output current 5 ( When the pins L26 to L33 are configured as output ports ) Output current 6 ( OSC2 ) IOH2 IOL2 IOH2S IOL2S IOH3 IOL3 IOH4 IOL4 IOH5 IOL5 IOH5S IOL5S IOH6 IOL6 IOH7 IOMH7 Output current 7 ( L0 to L33 ) IOMH7S IOML7 IOML7S IOL7 Output Leakage Current ( P1.0 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) (RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) IOOH Condition VOH1 = VDDI - 0.5V VOL1 = 0.5V VDDI = 5.0V, VOH1S = VDDI - 0.5V VDDI = 5.0V, VOL1S = 0.5V VOH2 = VDDI - 0.5V VOL2 = 0.5V VDDI = 5.0V, VOH2S = VDDI - 0.5V VDDI = 5.0V, VOL2S = 0.5V VOH3 = VDD - 0.7V VOL3 = 0.7V VOH4 = VDD - 0.1V VOL4 = 0.1V VOH5 = VDDI - 0.5V VOL5 = 0.5V VDDI = 5V, VOH5S = VDDI - 0.5V VDDI = 5V, VOL5S = 0.5V VOH6 = VDD - 0.5V VOL6 = 0.5V VOH7 = VDD3 - 0.2V (VDD3 level) VOMH7 = VDD2 + 0.2V (VDD2 level) VOMH7S = VDD2 - 0.2V (VDD2 level) VOML7 = VDD1 + 0.2V (VDD1 level) VOML7S = VDD1 - 0.2V (VDD1 level) VOL7 = VSS + 0.2V (VSS level) VOH = VDD Min. -6.0 2 -9 4 -6.0 0.7 -9 1 -6.0 0.7 -2.5 0.7 -1.5 0.15 -2.0 0.2 -4.0 0.7 4 4 4 Typ. -2.0 5 -3 8 -2.0 2.0 -3 3 -2.0 6.0 -0.8 1.3 -0.8 1.0 -1.0 1.0 -0.8 2.0 Max. -0.7 20 -1 25 -0.7 6.0 -1 9 -0.7 10.0 -0.3 2.5 -0.15 4.0 -0.2 5.0 -0.3 6.0 -4 -4 -4 0.3 mA 2 Unit Measuring Circuit µA - IOOL VOL = VSS -0.3 - - 30/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics (3.0 V Spec.) (Continued) (VSS=0V, VDD1=1.5V, VDD2=VDDI=VDD=3.0V, VDD3=4.5V, Ta=-40 to +85°C unless otherwise specified ) Parameter Symbol IIH1 Input Current 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) IIL1 IIH1S IIL1S IIH1Z IIL1Z IIH2 Input Current 2 ( IN0, IN1 ) IIH2Z IIL2Z IIL3 Input Current 3 ( OSC1 ) Input Current 4 ( RESET, TST1, TST2 ) Input Voltage 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Input Voltage 2 ( IN0, IN1, OSC1 ) Input Voltage 3 ( RESET, TST1, TST2 ) IIH3Z IIL3Z IIH4 IIL4 VIH1 VIL1 VIH1S VIL1S VIH2 VIL2 VIH3 VIL3 VDDI=5.0V VDDI=5.0V Condition VIH1 = VDDI ( when pulled down ) VIL1=VSS ( when pulled up ) VIH1=VDDI=5V ( when pulled down ) VIL1=VSS, VDDI=5V ( when pulled up ) VIH1=VDDI ( in a high impedance ) VIL1=VSS (in a high impedance ) VIH2=VDD ( when pulled down ) VIH2=VDD ( in a high impedance ) VIL2=VSS ( in a high impedance ) VIL3=VSS ( when pulled up ) VIH3=VDD ( in a high impedance ) VIL3=VSS ( in a high impedance ) VIH4=VDD VIL4=VSS Min. 30 -300 80 -800 0 -1 30 0 -1 -300 0 -1 0 -3.00 2.4 0 4 0 2.4 0 2.4 0 Typ. 90 -90 250 -250 90 -110 -1.50 Max. 300 -30 800 -80 1 0 300 1 0 -10 1 0 1 -0.75 3.0 0.6 5 1 3.0 0.6 3.0 0.6 V 4 mA Unit Measuring Circuit µA 3 31/49 FEDL64168-01 Semiconductor ML64168 DC Characteristics ( 3.0V Spec. ) ( Continued ) (VSS=0V, VDD1=1.5V, VDD2=VDDI=VDD=3.0V, VDD3=4.5V, Ta=-40 to +85°C unless otherwise specified) Measuring Symbol Condition Min. Typ. Max. Unit Circuit ∆VT1 ∆VT1S VDDI=5.0V 0.2 0.25 0.5 1.00 1.0 1.50 Parameter Hysteresis Width ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Hysteresis Width ( RESET, TST1, TST2 ) Input Pin Capacitance ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) V 4 ∆VT2 - 0.2 0.5 1.0 CIN - - - 5 pF 1 32/49 FEDL64168-01 Semiconductor ML64168 Measuring circuit 1 RT0 OSC1 ROS OSC2 RT0 CS0 CS0 RI0 IN0 XT XT C1 C2 VDD2 CB V VDD3 VDDI CC V CA ,CC ,CB ,C12 CL ROS RT0 CS0 RI0 : : : : : : 0.1µF 0.47µF 60kΩ 10kΩ/2kΩ 820pF 10kΩ C12 32.768kHz Crystal VDDL VSS VDD VDD1 CL A V CA V Measuring circuit 2 VIH OUTPUT *1 INPUT *2 A VIL VSS VDD1 VDD2 VDD3 VDD VDDI VDDL 33/49 FEDL64168-01 Semiconductor ML64168 Measuring circuit 3 *3 INPUT A VSS VDD1 VDD2 VDD3 VDD VDDI VDDL Measuring circuit 4 VIH INPUT OUTPUT VDD1 VDD2 VDD3 VDD VDDI VDDL *3 VIL VSS *1 Input logic circuit to determine the specified measuring conditions. *2 Measured at the specified output pins. *3 Measured at the specified input pins. OUTPUT Waveform Monitoring 34/49 FEDL64168-01 Semiconductor ML64168 A/D Converter Characteristics (3.0 V Spec.) ( VSS=0V, VDD2=VDD=3.0V, Ta=-40 to +85°C unless otherwise specified) MeasurCondition Min. Typ. Max. Unit ing Circuit Parameter Symbol Resistor for Oscillation Input Current Limiting Resistor Oscillation Frequency RS0, RS1, RT0, RT0-1, RT1 RI0, RI1 fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 CS0, CT0, CS1 ≥ 740pF 1 - - kΩ Resistor for oscillation =2 kΩ Resistor for oscillation =10 kΩ Resistor for oscillation =200 kΩ RT0, RT0-1, RT1 = 2 kΩ RT0, RT0-1, RT1 = 10 kΩ RT0, RT0-1, RT1 = 200 kΩ 1 200 46.5 2.79 4.272 0.990 0.0573 10 239 55.4 3.32 4.380 1.000 0.0616 277 64.3 3.85 4.490 1.010 0.0659 kΩ kHz kHz kHz - 5 RS•RT Oscillation Frequency Ratio(*) * Kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor in the same condition. Kfx= fOSCx(RT0 - CS0 Oscillation) fOSCx(RS0 - CS0 Oscillation) , (X = 1, 2, 3) fOSCx(RT0-1 - CS0 Oscillation) fOSCx(RS0 - CS0 Oscillation) , fOSCx(RT1 - CS1 Oscillation) fOSCx(RS1 - CS1 Oscillation) 35/49 FEDL64168-01 Semiconductor ML64168 Measuring circuit 5 (CROSC1) RT1 RI1 RS1 CS1 RI0 CS0 (CROSC0) RT0-1 CT0 RT0 RT0 P4.3 Frequency Measurement (fOSCX) RT0,RT0-1,RT1=2kΩ/10kΩ/200kΩ RS0,RS1=10kΩ RI0,RI1=10kΩ CS0,CT0,CS1=820pF CL=0.1µF VDDI RS0 Oscillation Mode Designation RT1 RS1 CS1 IN1 RESET TST1 TST2 P0.0 P0.1 P0.2 P0.3 VSS IN0 CS0 RS0 CRT0 D.U.T VDDL CL VDD 36/49 FEDL64168-01 Semiconductor ML64168 AC Characteristics ( 3.0V Spec. ) ( Serial Interface ) ( VSS=0V, VDD=3.0V, VDDI=5.0V , Ta=-40 to +85°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCLK Input Fall Time SCLK Input Rise Time SCLK Input “L” Level Pulse Width SCLK Input “H” Level Pulse Width SCLK Input Cycle Time SCLK Output Cycle Time SCLK Output Cycle Time SOUT Output Delay Time SIN Input Setup Time SIN Input Hold Time tf tr tCWL tCWH tCYC tCYC1(O) tCYC2(O) tDDR tDS tDH CPU is operating at 32.768kHz CPU is operating at 700kHz CL=10pF - 0.8 0.8 2.0 0.5 0.8 15 15 30.5 1.43 - 50 50 0.4 - ns ns µs µs µs µs µs µs µs µs Synchronous communication timing ( “H” level = 4.0V, “L” level = 1.0V ) tCYC SCLK (P4.2) tr tDDR SOUT (P4.0) tDS SIN (P3.3) tDH tDS 5V tCWH tf tDDR 5V tCWL 5V 37/49 FEDL64168-01 Semiconductor ML64168 RECOMMENDED OPERATING CONDITIONS ( When Voltage Regulator for LCD Driver Used ) (VSS = 0V) Parameter Operating Temperature Operating Voltage Crystal oscillation frequency Symbol Top VDD fXT Condition Rating -40 to + 85 1.25 to 3.5 30 to 66 Unit °C V kHz ELECTRICAL CHARACTERISTICS ( When Voltage Regulator for LCD Driver Used ) DC Characteristics (VSS=0V, VDD=3.0V, Ta=-40 to +85°C unless otherwise specified ) Parameter VDD1 Voltage VDD2 Voltage VDD3 Voltage Supply Current 1 Symbol VDD1 ∆VDD1 VDD2 VDD3 IDD1 Condition VDD=1.25 to 3.5, Ta=25°C VDD=1.25 to 3.5 VDD=1.25 to 3.5 VDD=1.5V, CPU in halt state VDD=3.0V, CPU in halt state VDD=1.5V, CPU in operating state VDD=3.0V, CPU in operating state Min. 1.00 Typ. - 0.1 Typ. - 0.2 Typ. 1.2 -4 2×VDD1 3×VDD1 Max. 1.40 Typ. + 0.1 Typ. + 0.2 Unit V mV/°C V Measuring Circuit - 2 2 5 5 5 5 15 15 1 µA Supply Current 2 IDD2 Notes: The other electrical characteristics are the same as those for the 1.5V and 3.0V specifications. 38/49 FEDL64168-01 Semiconductor ML64168 Power Supply Circuit VDDI VDD C1 C2 ML64168 VDD3 VDD2 VDD1 VDDL VSS ML64168 1.5V Version VDDI VDD C1 C2 ML64168 VDD3 VDD2 VDD1 VDDL VSS ML64168 1.5V Version.(The LCD bias is regulated.) VDDI VDD C1 C2 ML64168 VDD3 VDD2 VDD1 VDDL VSS ML64168 3.0V Version VDDI VDD C1 C2 ML64168 VDD3 VDD2 VDD1 VDDL VSS ML64168 3.0V Version.(The LCD bias is regulated.) Note:CA,CB,CC,CS,CL,CI,C12:0.1µF +100% -50% CL:0.47µF C12 CC CB CA CL 3.0V CS CI CA CL 3.0V C12 CC CS CI C12 CC CB CA CL 1.5V 5V CS CI CL 1.5V 5V C12 CC CB CS CI 39/49 FEDL64168-01 Semiconductor ML64168 FUNCTIONAL DESCRIPTION CPU Peripheral Function ∙ A/D converter ( ADC ) The ML64168 has a built-in two-channel RC oscillation A/D converter. The A/D converter is composed of a two-cannel oscillation circuit, Counter A ( CNTA0-4, a 4.8-digit decade counter ), Counter B ( CNTB0-3, a 14-bit binary counter ), and A/D Converter Control Registers 0 and 1 ( ADCON0, ADCON1 ). By counting oscillation frequencies that vary depending on a resistor or capacitor connected to the RC oscillation circuit, the A/D converter converts resistance values or capacitance values to corresponding digital values. By using a thermistor or humidity sensor as a resistance, a thermometer or a hygrometer can be constructed. By applying a separate sensor to each cannel of the 2-channel RC oscillation circuit, it is also possible to extend measure ranges or measure at two places. ∙ Serial port ( SIOP ) The ML64168 has an 8-bit synchronous serial port. Receive/transmit operation of the serial port is performed simultaneously and the serial transfer clock can select either internal or external mode. Direction of transfer data can be big endian or little endian. Each pin of the serial port is assigned as secondary functions of P3.3 and P4.0 to P4.2. Setting each bit of SIN,SOUT, SPR and SCLK of P33CON and P40CON to P42CON to “1” makes each pin valid. ∙ LCD driver ( LCD ) The ML64168 has a built-in LCD driver for 34 outputs. The LCD driver consists of 31× 4-bit display registers ( DSPR0-30 ), the Display Control Register ( DSPCON ), a 34-output LCD driver circuit, and a bias generation circuit ( BIAS ). The bias generation circuit for LCD driver ( BIAS ) generates bias voltages for the LCD driver by rising or dropping the power supply voltage by externally installing capacitors. Alternatively, it generates bias voltages by rising the constant voltage ( VDD1 = 1.2V ) generated by the voltage regulator for LCD driver. Which way is to be used is specified by mask option. There are three types of driving methods: 1/4duty, 1/3duty and 1/2duty. Software selects the duty mode. A mask option can select either a common driver or a segment driver for each LCD driver pin. A mask option can also specify assignment of each bit of the display register to each segment. All the display registers must be selected by a mask option. L26 to L33 of the LCD driver can be configured to be output ports by a mask option. The relationship between the duty, the bias method, and the maximum segment number follows: 1/4duty, 1/3 bias method ----------- 120 segments 1/3duty, 1/3 bias method ----------- 93 segments 1/2duty, 1/2 bias method ----------- 64 segments ∙ Buzzer driver ( BD ) The ML64168 has a built-in buzzer driver with 15 buzzer output frequencies and 4 buzzer output modes. Each buzzer output is selected by the Buzzer Control Register ( BDCON ) and the Buzzer Frequency Control Register ( BFCON ). 40/49 FEDL64168-01 Semiconductor ML64168 ∙ Capture circuit ( CAPR ) The ML64168 captures 32Hz to 256Hz output of the time base counter at the falling of Port 0.0 or Port 0.1 ( P0.0 or P0.1 ) to “L” level when the pull-up resistor input is chosen, or at the rising to “H” level when the pull-down resistor input is chosen. The capture circuit is composed of the Capture Control Register ( CAPCON ) and the Capture Registers ( CAPR0, CAPR1 ) that fetch output from the time base counter. ∙ Watchdog timer ( WDT ) The ML64168 has a built-in watchdog timer to detect CPU malfunction. The watchdog timer is composed of a 6-bit watchdog timer counter ( WDTC ) to count a 16Hz output and a watchdog timer control register ( WDTCON ) to reset WDTC. ∙ Clock generation circuit ( 2CLK ) The clock generation circuit ( 2CLK ) in the ML64168 contains a 32.768kHz crystal oscillation circuit, a 700kHz RC oscillation circuit, and a clock control port. This circuit generates the system clock ( CLK ) and the time base clock ( 32.768kHz ). The system clock drives the CPU while the time base clock drives the time base counter and the buzzer driver. Via the contents of the Frequency Control Register ( FCON ), the system clock can be switched between 32.768kHz ( the output of the crystal oscillation circuit ) and 700kHz ( the output of the RC oscillation circuit ). Note: The oscillation frequency of the RC oscillation circuit varies depending on the value of an external resistor ( ROS ), operating power supply voltage ( VDD ), and ambient temperatures (Ta). ∙ Time base counter ( TBC ) The ML64168 has a built-in time base counter ( TBC ) that generates clocks to be supplied to internal peripheral circuit. The time base counter is composed of 15 binary counters, and a 1/10 frequency dividing circuit. The count clock of the time base is driven by the oscillation clock ( 32.768kHz ) of the crystal oscillation circuit. The output of the time base counter is used for the buzzer driver, the system reset circuit, the watchdog timer, the time base interrupt, the sampling clocks of each port, and the capture circuit. ∙ I/O port Input-output ports ( P2, P3, P4 ) : 3 ports × 4bits Pull-up ( pull-down ) resistor input or high-impedance input, CMOS output or NMOS open drain output: these can be specified for each bit; external 0 interrupt Input port ( P0 ) : 1 port × 4bits Pull-up ( pull-down ) resistor input or high-impedance input; external 1 interrupt Output port ( P1 ) : 1 port × 4bits CMOS output or NMOS open drain output 41/49 FEDL64168-01 Semiconductor ML64168 ∙ Interrupt ( INTC ) The ML64168 has 10 interrupt sources ( 10 vector address ), of which two are external interrupts from ports and eight are internal interrupts. Of the ten interrupt sources, only the watchdog timer interrupt cannot be disabled ( non-maskable interrupt ). The other nine interrupts are controlled by the master interrupt enable flag ( MI ) and the interrupt enable registers ( IE0, IE1, and IE2 ). When an interrupt condition is met, the CPU branches to a vector address corresponding to the interrupt source. ∙ Battery check circuit ( BC ) The battery check circuit ( BC ) detects the level of the supply voltage by comparing the voltage generated by an external supply-voltage dividing resistor ( RBLD ) with the internal reference voltage ( Vrb ). 42/49 FEDL64168-01 Semiconductor LCD ROS L33 L0 OSC2 OSC1 32.768 kHz C12 CC CB CS CI 1.5V 5V APPLICATION CIRCUITS (1.5 V Spec.) CGEX ML 64168-xxxGA/GP/TB ML 64168-xxx (1.5V Spec.) VDD1 VSS VDDL TST2 TST1 IN0 CS0 RS0 CRT0 RT0 P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 IN1 CS1 RS1 RT1 BD CL XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 VDDI VDD C2 C1 VDD3 VDD2 - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External Switch matrix ( 4 x 4 ) RT1 RS1 CS1 RI1 RT0 RS0 CS0 RI0 1.5V Spec. Application Circuit ( Voltage Regulator for LCD Driver not Used ) Buzzer RBLD ML64168 43/49 FEDL64168-01 Semiconductor LCD ROS L33 L0 OSC2 OSC1 32.768 kHz C12 CC CB CA CL CS CI 1.5V 5V APPLICATION CIRCUITS (1.5 V Spec.) (continued) CGEX ML 64168-xxxGA/GP/TB ML 64168-xxx (1.5V Spec.) VDDI VDD C2 C1 VDD3 VDD2 VDD1 VSS VDDL TST2 TST1 XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 IN0 CS0 RS0 CRT0 RT0 P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 IN1 CS1 RS1 RT1 BD - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External Switch matrix ( 4 x 4 ) RT1RS1CS1 RI1 RT0 RS0 CS0 RI0 1.5V Spec. Application Circuit ( Voltage Regulator for LCD Driver Used ) Buzzer RBLD ML64168 44/49 FEDL64168-01 LCD Semiconductor ROS L33 L0 OSC2 OSC1 32.768 kHz C12 CC CA CL 3V CS CI APPLICATION CIRCUITS (3.0 V Spec.) CGEX ML 64168-xxxGA/GP/TB ML 64168-xxx (3.0V Spec.) VDDI VDD C2 C1 VDD3 VDD2 VDD1 VSS VDDL 5V XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 TST2 TST1 IN0 CS0 RS0 CRT0 RT0 P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 IN1 CS1 RS1 RT1 BD - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External Switch matrix ( 4 x 4 ) RT1RS1CS1 RI1 RT0 RS0CS0 RI0 3.0V Spec. Application Circuit ( Voltage Regulator for LCD Driver not Used ) Buzzer OSC monitor SCLK To the serial communication interface SPR ( 5V ( VDDI ) system ) SOUT SIN RBLD ML64168 45/49 FEDL64168-01 LCD Semiconductor ROS L33 L0 OSC2 OSC1 32.768 kHz C12 CC CB CA CL 3V CS CI 5V VDDI VDD C2 C1 VDD3 VDD2 VDD1 VSS VDDL TST2 TST1 APPLICATION CIRCUITS (3.0 V Spec.) (continued) CGEX XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 ML 64168-xxxGA/GP/TB ML 64168-xxx (3.0V Spec.) IN0 CS0 RS0 CRT0 RT0 P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 IN1 CS1 RS1 RT1 BD P0.3 Switch matrix ( 4 x 4 ) - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External RT1RS1CS1 RI1 RT0 RS0 CS0 RI0 3.0V Spec. Application Circuit ( Voltage Regulator for LCD Driver Used ) Buzzer OSC monitor SCLK To the serial communication interface SPR ( 5V ( V DDI ) system ) SOUT SIN RBLD ML64168 46/49 FEDL64168-01 Semiconductor ML64168 PACKAGE DIMENSIONS ML64168-XXXGP 25.0±0.2 20.0±0.2 64 41 40 0.17±0.05 0.12 1.0TYP. 65 SEATING PLANE 2.5TYP. 19.0±0.2 14.0±0.2 2.5MAX. 2.1±0.2 0.05~0.35 25 1 24 0.25 80 0~10° 1.3TYP. 1.38±0.15 INDEX MARK 0.8TYP. 0.8 0.32 -0.07 +0.08 0.16 M Figure C-1 80-Pin QFP:GP Package Dimension Diagram Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 47/49 FEDL64168-01 Semiconductor ML64168 PACKAGE DIMENSIONS ML64168-XXXGA 60 61 41 40 0.17±0.05 0.83TYP. 0.10 SEATING PLANE 16.8±0.2 14.0±0.1 1.4±0.2 2.4MAX. 2.1±0.2 80 1 20 0~0.25 0.25 21 0~10° 0.6TYP. 0.67±0.15 INDEX MARK 0.83TYP. 0.65 0.32 -0.07 +0.08 0.13 M Figure C-2 80-Pin QFP:GA Package Dimension Diagram Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 48/49 FEDL64168-01 Semiconductor ML64168 PACKAGE DIMENSIONS ML64168-XXXTB 0.17±0.05 40 61 60 41 19.0±0.2 14.0±0.1 1.25TYP. 0.10 SEATING PLANE 1.0±0.2 1.2MAX. 1.0±0.05 0~0.25 0.25 80 INDEX MARK 1 20 21 0~10° 0.5±0.2 0.6TYP. 1.25TYP. 0.5 0.22 -0.07 +0.08 0.10 M Figure C-3 80-Pin QFP:TB Package Dimension Diagram Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 49/49