ML66525

OKI Semiconductor ML66525 Family 16-Bit Microcontroller FEDL66525-02 Issue Date: July 19, 2002 GENERAL DESCRIPTION The ML66525 family devices are high-performance 16-bit CMOS microcontrollers that utilize the nX-8/500S, Oki’s proprietary CPU core. Data from a personal computer with a USB connector can be automatically, quickly written or read to and from NAND type Flash Memory via USB I/F and NAND Flash Memory I/F. The ML66525 family devices support clock gear functions, a sub-clock and HALT/STOP mode, which are suitable for low power applications. The ML66525 family devices are provided with interfaces to external devices such as a 4-channel multi-functional serial interface with internal 32-byte FIFO and a high-speed bus interface that has separate address and data buses and does not require external address latches. A wide variety of internal multi-functional timers enable various timing controls such as periodic and timed measurements. With a 16-bit CPU core that enables high-speed arithmetic computations and a variety of bit processing functions, these general-purpose microcontrollers are optimally suited for Digital Audio devices such as MP3 players, voice recorders, handy games, and PC peripheral control systems (to control devices that can be connected to USB and store data into memory). The ML66525 family devices also include the flash ROM version device (ML66Q525B) that is programmable with a single 3 V power supply (2.4 to 3.6 V). [ Note ] ML66525A/ML66Q525A are supplied as stock lasts. APPLICATIONS • Small-sized handy systems that require USB control and Storage control (Digital Audio players, etc) • PC Peripheral Control Systems ORDERING INFORMATION Order Code or Product Name ML66525B-xxTB *1 ML66Q525B-NTB *2 ML66525B-xxLA *1 Package 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) 144-pin plastic LFBGA Remark mask ROM version (2.4 to 3.6 V) ML66525B flash ROM version (2.4 to 3.6 V) ML66525B BGA package version (2.4 to 3.6 V) (P-LFBGA144-1111-0.80) ML66Q525B-NLA *2 ML66Q525B BGA package version (2.4 to 3.6 V) *1 : The “xx” of “-xx” stands for the code number. *2 : The “N” of “-N” stands for the flash ROM blank version. When OKI programs and ship the flash ROM, the part number is changed from ”–N” to ”–XX” (code number ) , for example, ML66Q525B-999TB. 1/27 FEDL66525-02 OKI Semiconductor ML66525 Family FEATURES Parameter Operating temperature Power supply voltage/ Maximum operating frequency Minimum instruction execution time Internal ROM size (max. external) Internal RAM size (max. external) I/O ports 83 nsec@24 MHz 61 µsec@32.768 kHz 128 KB (1 MB) 6 KB (1 MB) 64 I/O pins (with programmable pull-up resistors) 6 input-only pins 1 output-only pin 16-bit auto-reload timer × 2ch 8-bit auto-reload timer × 1ch 8-bit auto-reload timer 8-bit auto-reload timer (also functions as watchdog timer) × 1ch Watch timer × 1ch 8-bit PWM × 2ch (can also be used as 16-bit PWM × 1ch) Synchronous (with 32-byte FIFO) × 1ch Synchronous (Shift register type) × 1ch Synchronous/UART × 2ch 10-bit × 4ch Non-maskable × 1ch Maskable × 6ch Compliant with USB spec. version 1.1 High-speed transfer at 12 Mbps Internal PLL(x2 , x3 , x4) -> 48 MHz Internal transceiver Vbus detection circuit (connection to USB host : detect/non-detect) Bus power available EP0 (IN 32 bytes, OUT 32 bytes), control transfer EP1 (64 bytes × 2), bulk/interrupt transfer EP2 (64 bytes × 2), bulk/interrupt transfer EP3 (32 bytes), bulk/interrupt transfer EP4 (64 bytes × 2), bulk/isochronous/interrupt transfer EP5 (64 bytes × 2), bulk/isochronous/interrupt transfer Automatic, high-speed data transfer ECC circuit Automatic, high-speed 512-byte data transfer 3 levels External bus Interface (separate address and data buses) Dual clocks function Clock gear function Different power available among USB, CPU core, and I/O port ML66Q525B ML66525B –30 to +70°C VDD = 2.4 to 3.6 V / f = 24 MHz Timers Serial port A/D converter External interrupts USB control NAND Flash Memory control Interrupt priority Others Flash ROM version 2/27 FEDL66525-02 OKI Semiconductor ML66525 Family FUNCTIONAL DESCRIPTION 1. High-performance CPU The ML66525 family devices include the high-performance CPU, powerful bit manipulation instruction set, a variety of symmetrical addressing modes, and ROM WINDOW function, and also supports the best-optimized C compiler. 2. A variety of power saving modes Attaching a 32.768-kHz crystal produces a real time clock signal from the internal clock timer. A single clock can be used in place of dual clocks. Switching the CPU clock to the dual clocks (1/2 or 1/4 of the main clock) enables operation in a low power consumption mode. The clock gear function allows a 1/2 or 1/4 clock signal of the main clock to be selected as the CPU operating clock. The ML66525 family devices are provided with a wide range of standby control functions such as the STOP mode that stops the oscillation circuit, the quick restart STOP mode that stops the CPU and peripherals while the oscillation circuit is operating, and the HALT mode that shuts down the CPU while peripherals are operating. 3. USB control The family include USB controller which compliant with USB specification version 1.1 and can be transferred data with 12Mbps circuit. Also, USB controller have 6 kinds of endpoint and apply for control/bulk/isochronous/interrupt transfer. With NAND Flash Memory control circuit, high speed data transfer is possible. 4. NAND Flash Memory control The family include control circuit of NAND Flash Memory. Automatically data read from and write to outside NAND Flash Memory with 528 byte. Also, include ECC circuit which detect data error and correct data error. 5. ML66Q525B with flash memory programmable with single power supply In addition to mask ROM version devices, the ML66525 family devices include the ML66Q525B with internal 128 Kbytes of flash memory that can be programmed with a single power supply. The flash memory of the ML66Q525B can be programmed with a low power supply (2.4 to 3.6 V) using the internal voltage booster circuit. 6. Multifunctional, high-precision analog-to-digital converter The family devices include a high-precision 10-bit analog-to-digital converter with four channels and are ideal for such analog control functions as processing audio signals, processing sensor inputs, detecting key switch states, and controlling battery use in portable equipment. Each channel has its own result register readily accessible from the software. 3/27 FEDL66525-02 OKI Semiconductor ML66525 Family 7. Multifunctional PWM The family devices support both 8- and 16-bit PWM operations. Choosing between the time base counter output and the overflow from an 8-bit auto-reload time as the PWM counter clock source provides a great number of possibilities over a broad frequency range. The 16-bit PWM configuration supports a high-speed synchronization mode that generates a high-precision output signal with less ripple suitable for digital-to-analog applications. 8. Programmable pull-up resistors Building the pull-up resistors into the chip contributes overall design compactness. Making them programmable on a per-bit basis allows complete flexibility in circuit board layout and system design. These programmable pull-up resistors are available for all I/O pins except ports that have specific functions such as oscillator connection pins. 9. High-speed bus interface The interface to external devices uses separate data and address buses. This arrangement permits a rapid bus access for controlling the system from the microcontroller. 10. A variety of external interrupts There are a total of seven interrupt channels for use in communicating with external devices; six channels for maskable interrupts and one channel for non-maskable interrupts. 4/27 FEDL66525-02 OKI Semiconductor ML66525 Family BLOCK DIAGRAM NMI EXINT0 to EXINT4 EXINT8/9 Interrupt CPU Core System 16-bit Timer0 RXD1 TXD1 RXC1 TXC1 Control RESn OSC0 OSC1n XT0 XT1n SIO1 (UART/SYNC) 8-bit Timer4/BRG ALU Control Registers ALU Control ACC SSP LRB PSW PC RXD6 TXD6 RXC6 TXC6 SIO6 (UART/SYNC) 8-bit Timer3/BRG DSR TSR CSR SIOI3 SIOO3 SIOCK3 SIO3 (SYNC) 8-bit Timer5/BRG Memory Control Pointing Registers Local Registers Instruction Decoder SIOI4 SIOO4 SIOCK4 SIO4 (32-byte FIFO SYNC) 8-bit Timer6/WDT 16-bit Timer7 + 2Kbyte Also functions as transfer RAM Bus Port Control RAM 4Kbyte ROM 128 Kbyte EAn PSENn RDn WRn D0 to D7 A0 to A19 P0 (8 bit) P1 (8 bit) P2 (4 bit) P3 (3 bit) P4 (8 bit) P6 (4 bit) PWMOUT0 PWMOUT1 8-bit PWM0 8-bit PWM1 8-bit Timer9 TBC Port Control RTC VREF AGND AI0 to AI3 10-bit A/D Converter USB DMA transfer FLASH media DMA transfer bus P7 (2 bit) P8 (4 bit) P9 (1 bit) P10 (6 bit) P12 (4 bit) P13 (2 bit) P15 (4 bit) P20 (8 bit) P21 (5 bit) PUCTL D+/D– USB (Compliant with ver1.1) DMA (USB ↔ Transfer RAM) Transfer RAM (512 bytes × 4 banks) Flash media control DMA (Media ↔ Transfer RAM) FD0 to FD7 FRDn FWRn FCLE FALE FRB 5/27 FEDL66525-02 OKI Semiconductor ML66525 Family PIN CONFIGURATION (TOP VIEW) Dñ D+ PUCTL GND P20_7/FD7 P20_6/FD6 P20_5/FD5 P20_4/FD4 P20_3/FD3 P20_2/FD2 P20_1/FD1 P20_0/FD0 VDD_IO GND P21_4/FRB P21_3/FALE P21_2/FCLE P21_1/FWRn P21_0/FRDn AGND AI3/P12_3 AI2/P12_2 AI1/P12_1 AI0/P12_0 VREF 95 90 85 VBUS P9_0/VBUSIN P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P7_6/PWM0OUT P7_7/PWM1OUT FLAMOD P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 GND VDD_IO P10_0/SIOCK3 P10_1/SIOI3 P10_2/SIOO3 P10_3/SIOCK4 P10_4/SIOO4 P10_5/SIOI4 P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6 100 80 1 75 5 70 10 65 15 60 20 55 25 30 35 40 45 50 VDD_CORE P2_3/A19 P2_2/A18 P2_1/A17 P2_0/A16 VTM P1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 P4_7/A7 P4_6/A6 P4_5/A5 P4_4/A4 P4_3/A3 P4_2/A2 P4_1/A1 P4_0/A0 VDD_CORE GND VDD_IO A symbol with “n” suffixed indicates an active Low pin. VDD_CORE RESn NMI EAn VDD_IO XT0 XT1n GND TEST OSC0 OSC1n VDD_IO P13_0/EXINT8 P13_1/EXINT9 P0_0/D0 P0_1/D1 P0_2/D2 P0_3/D3 P0_4/D4 P0_5/D5 P0_6/D6 P0_7/D7 P3_1/PSENn P3_2/RDn P3_3/WRn 100-pin Plastic TQFP 6/27 FEDL66525-02 OKI Semiconductor ML66525 Family PIN CONFIGURATION (TOP VIEW) NC VDD_IO P3_3/ WRn NC P3_2/ RDn P3_1/ PSENn VDD_ CORE P4_1/ A1 P4_3/ A3 P1_0/ A8 P1_2/ A10 P1_3/ A11 P1_7/ A15 VTM NC P0_4/ D4 P0_7/ D7 NC P0_5/ D5 P0_2/ D2 P0_6/ D6 NC P0_3/ D3 P0_1/ D1 P0_0/ D0 NC P13_1/ OSC0 EXINT9 VDD_IO OSC1n P13_0/ EXINT8 NC GND XT0 NMI VDD_ CORE P15.2/ RXC6 NC P15_3/ TXC6 N GND P4_0/ A0 P4_2/ A2 P4_4/ A4 P4_6/ A6 NC P1_5/ A13 NC TEST XT1n VDD_IO M NC NC EAn RESn P15_0/ P15_1/ RXD6 TXD6 L NC P4_5/ A5 P4_7/ A7 P1_1/ A9 P1_4/ A12 NC P1_6/ A14 P2_0/ A16 P2_2/ A18 VDD_ CORE 12 NC NC NC P10_4/ P10_2/ P10_5/ SIOO4 SIOO3 SIOI4 P10_3/ SIOCK4 VDD_IO P8_3/ TXC1 P8_1/ TXD1 NC NC K NC NC J NC NC P10_0/ P10_1/ SIOCK3 SIOI3 P8_2/ RXC1 P8_0/ RXD1 GND H NC NC G NC NC NC F NC NC P7_6/ P7_7/ FLAMO PWM0O PWM1O E D UT UT P6_2/ EXINT2 P6_0/ EXINT0 NC P6_3/ EXINT3 P6_1/ EXINT1 D NC P2_1/ A17 P2_3/ A19 NC 13 NC NC NC NC NC NC NC VREF P12_1/ P12_3/ P21_4/ P20_1/ P20_7/ VDD_IO AI1 AI3 FRB FD1 FD7 AGND P21_1/ P21_3/ FWRn FALE P21_2 /FCLE 8 GND P20_0 /FD0 7 NC NC C NC P20_2/ P20_3/ P20_5/ PUCTL FD2 FD3 FD5 P20_4/ P20_6/ FD4 FD6 6 5 GND 4 D+ 3 D- P9_0/ VBUSIN B NC 1 A P12_0/ P12_2/ P21_0/ AI0 AI2 FRDn 11 10 9 VBUS 2 144-pin Plastic LFBGA A symbol with “n” suffixed indicates an active Low pin. [Note] Don’t connect NC pins with others. 7/27 FEDL66525-02 OKI Semiconductor ML66525 Family PIN DESCRIPTIONS In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin. A symbol with “n” suffixed indicates an active Low pin. Classification Port Symbol Type P0_0/D0 to P0_7/D7 P1_0/A8 to P1_7/A15 P2_0/A16 to P2_3/A19 P3_1/PSENn I/O Primary function 8-bit I/O port Pull-up resistors can be specified for each bit. I/O 8-bit I/O port Pull-up resistors can be specified for each bit. I/O 4-bit I/O port Pull-up resistors can be specified for each bit. I/O 1-bit I/O port Pull-up resistors can be specified. P3_2/RDn P3_3/WRn O I/O 1-bit output port 1-bit I/O port Pull-up resistors can be specified. P4_0/A0 to P4_7/A7 P6_0/EXINT0 P6_1/EXINT1 P6_2/EXINT2 P6_3/EXINT3 P7_6/PWM0OUT P7_7/PWM1OUT P8_0/RXD1 P8_1/TXD1 P8_2/RXC1 P8_3/TXC1 I/O I/O 2-bit I/O port Pull-up resistors can be specified for each bit. 4-bit I/O port Pull-up resistors can be specified for each bit. I/O 8-bit I/O port Pull-up resistors can be specified for each bit. I/O 4-bit I/O port Pull-up resistors can be specified for each bit. Description Type I/O Secondary function External memory access data I/O port External memory access address output port External memory access address output port External program memory access read strobe output pin External data memory access read strobe output pin External data memory access write strobe output pin External memory access address output port External interrupt 0 input pin External interrupt 1 input pin External interrupt 2 input pin External interrupt 3 input pin PWM0 output pin PWM1 output pin SIO1 receive data input pin SIO1 transmit data output pin SIO1 receive clock I/O pin SIO1 transmit clock I/O pin O O O O O O I I I I O O I O I/O I/O 8/27 FEDL66525-02 OKI Semiconductor ML66525 Family Classification Port Symbol P9_0/VBUSIN Description Type I/O Primary function 1-bit I/O port Pull-up resistors can be specified. Type I Secondary function Vbus detect external interrupt input pin (5V tolerant input) SIO3 transmit-receive clock I/O pin SIO3 receive data input pin SIO3 transmit data input pin SIO4 (with internal 32-byte FIFO) transmit-receive clock I/O pin SIO4 (with internal 32-byte FIFO) transmit data output pin SIO4 (with internal 32-byte FIFO) receive data output pin A/D converter analog input port External interrupt 8 input pin External interrupt 9 input pin SIO6 receive data input pin SIO6 transmit data output pin SIO6 receive clock I/O pin SIO6 transmit clock I/O pin NAND Flash Memory access data I/O port NAND Flash Memory access read strobe output pin NAND Flash Memory access write strobe output pin NAND Flash Memory access CLE strobe output pin NAND Flash Memory access ALE strobe output pin NAND Flash Memory access Ready/Busy input pin P10_0/SIOCK3 P10_1/SIOI3 P10_2/SIOO3 P10_3/SIOCK4 P10_4/SIOO4 P10_5/SIOI4 P12_0/AI0 to P12_3/AI3 P13_0/EXINT8 P13_1/EXINT9 P15_0/RXD6 P15_1/TXD6 P15_2/RXC6 P15_3/TXC6 P20_0/FD0 to P20_7/FD7 P21_0/FRDn P21_1/FWRn P21_2/FCLE P21_3/FALE P21_4/FRB I/O 6-bit I/O port Pull-up resistors can be specified for each bit. I/O I O I/O O I I I I/O 4-bit input port 2-bit input port 4-bit I/O port Pull-up resistors can be specified for each bit. I/O 8-bit I/O port Pull-up resistors can be specified for each bit. I/O I/O I/O I/O I/O 5-bit I/O port Pull-up resistors can be specified for each bit. O O O O I I I I I O I/O I/O I/O 9/27 FEDL66525-02 OKI Semiconductor ML66525 Family Classification Power supply Symbol VDD_IO VDD_CORE VBUS GND VREF AGND Type I I I I I I I O IO Power supply pin Connect all the VDD _IO pins.* Core Power supply pin Description Connect all the VDD _CORE pins.* USB Power supply pin (Vbus input pin) GND pin Connect all the GND pins to GND.* Analog reference voltage pin (Connect to the VDD pin when A/D converter is not used.) Analog GND pin (Connect to the GND pin when A/D converter is not used.) Sub-clock oscillation input pin Connect to a crystal of f = 32.768 kHz. XT1n Sub-clock oscillation output pin Connect to a crystal of f = 32.768 kHz. The clock output is opposite in phase to XT0. OSC0 I Main clock oscillation input pin Connect to a crystal or ceramic oscillator. When an external clock is used, this pin is configured to be clock input. OSC1n O Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clock is used. USB I/F D+ D– PUCTL Reset Others RESn NMI TEST VTM FLAMOD I/O I/O O I I I I I D+ pin D– pin External control output pin Reset input pin Non-maskable interrupt input pin Test pin Connect to the GND pin for normal operation. Test pin Connect to the GND pin for normal operation. Flash ROM programming mode input pin When the FLAMOD pin is set to “L”, the device enters a programming mode. Connect to the VDD_IO pin when using as normal operation. EAn I External program memory access input pin When the EA pin is enabled (low level), the internal program memory is masked and the CPU executes the program code in external program memory through all address space. Oscillation XT0 * Connect all VDD_IO pins, all VDD_CORE pins and all GND pins. If a device has one or more VDD_IO, VDD_CORE, or GND pins to which the power supply or the ground potential is not connected, the family devices are not guaranteed to have normal operations. 10/27 FEDL66525-02 OKI Semiconductor ML66525 Family ABSOLUTE MAXIMUM RATINGS Parameter Digital power supply voltage Symbol VDD_CORE VDD_IO VBUS VI VO VREF VAI PD TSTG Ta = 70°C per package 100-pin TQFP 144-pin LFBGA — Condition GND = AGND = 0 V Ta = 25°C Other than P9_0 P9_0 (5 V tolerant input) Rated value –0.3 to +4.6 –0.3 to VDD_IO + 0.3 –0.3 to +0.6 –0.3 to VDD_IO + 0.3 –0.3 to +4.6 –0.3 to VREF 680 595 –50 to +150 Unit V V V V V V mW mW °C Input voltage Output voltage Analog reference voltage Analog input voltage Power dissipation Storage temperature RECOMMENDED OPERATING CONDITIONS Parameter Digital power supply voltage Analog reference voltage Analog input voltage VBUS input voltage Memory hold voltage Operating frequency Ambient temperature Symbol VDD_CORE VDD_IO VREF VAI VBUS VDDH fOSC fXT Ta Condition fOSC ≤ 24 MHz VDD_CORE ≤ VDD_IO VDD_CORE ≤ VREF — — fOSC = 0 Hz USB is used USB is unused — — MOS load P7, P10_0 to P10_2 Fan out N P0, P1, P2, P3, P4, TTL load P6, P8, P9, P10_3 to P10_5, P15, P20, P21 1 — Range 2.4 to 3.6 2.4 to 3.6 AGND to VREF 3.0 to 3.6 2.0 to 3.6 12, 16, 24 2 to 24 32.768 –30 to +70 20 6 Unit V V V V V MHz kHz °C — — 11/27 FEDL66525-02 OKI Semiconductor ML66525 Family ALLOWABLE OUTPUT CURRENT VALUES (VDD_IO = 2.4 to 3.6 V, Ta = –30 to +70°C) Parameter “H” output pin (1 pin) “H” output pins (sum total) “L” output pin (1 pin) Pin All output pins Sum total of all output pins All output pins Sum total of P0, P3 Sum total of P1, P2, P4 “L” output pins (sum total) Sum total of P6, P7, P8, P9 Sum total of P10, P15 Sum total of P20, P21 Sum total of all output pins ∑ IOL — — 70 160 35 mA Symbol IOH ∑ IOH IOL Min. — — — Typ. — — — Max. –10 –70 10 Unit [Note] Connect all VDD_CORE and VDD_IO pins to the power supply voltage and all GND pins to the ground voltage. If there is a pin or pins that are not connected to the power supply voltage on ground voltage, the device cannot be guaranteed for normal operation. INTERNAL FLASH ROM PROGRAMMING CONDITIONS Parameter Supply voltage Ambient temperature Endurance Blocks size Symbol VDD_CORE VDD_IO Ta CEP — Condition VDD_CORE ≤ VDD_IO During Read During Programming — — Rating 2.4 to 3.6 –30 to +70 +0 to +50 100 128 Unit V °C °C Cycles bytes 12/27 FEDL66525-02 OKI Semiconductor ML66525 Family ELECTRICAL CHARACTERISTICS DC Characteristics 1 (Except USB port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter “H” input voltage “H” input voltage “L” input voltage *1 Symbol VIH VIL Condition — — IO = –400 µA “H” output voltage *2 IO = –2.0 mA VOH IO = –200 µA “H” output voltage *3 IO = –1.0 mA “L” output voltage “L” output voltage Input leakage current Input current Input current Output leakage current Pull-up resistance Input capacitance Output capacitance Analog reference supply current *2 VOL *3 *4, *6 *5 *7 *2, *3 ILO Rpull CI CO IREF VO = VDD/0 V VI = 0 V fOSC = 1 MHz, Ta = 25°C During A/D operation IIH/IIL VI = VDD/0 V IO = 3.2 mA IO = 5.0 mA IO = 1.6 mA IO = 2.5 mA Min. 0.80 VDD 0.80 VDD –0.3 VDD – 0.4 VDD – 0.8 VDD – 0.4 VDD – 0.8 — — — — — — — — 40 — — — Typ. — — — — — — — — — — — — — — — 100 5 7 1.8 Max. 5.5 VDD + 0.3 0.2VDD — — — — 0.5 0.9 0.5 0.9 1/–1 1/–90 15/–15 ±10 200 — — 5 µA kΩ pF mA µA µA V Unit When A/D is stopped — — 5 VDD = VDD_IO *1. Applicable to P9_0 (5 V tolerant input) *2. Applicable to P7 and P10_0 to P10_2 *3. Applicable to P0, P1, P2, P3, P4, P6, P8, P9, P10_3 to P10_5, P15, P20 and P21 *4. Applicable to P12 and P13 *5. Applicable to RESn and FLAMOD *6. Applicable to EAn, NMI, and TEST *7. Applicable to OSC0 13/27 FEDL66525-02 OKI Semiconductor ML66525 Family Supply Current • Mask ROM version (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, VBUS = 3.0 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Mode Symbol Condition fosc = 24 MHz, No load fosc = 24 MHz, DMA/media CPU operation mode IDD control stopped. No load fXT = 32.768 kHz, DMA/media control stopped. No load USB operation mode HALT mode STOP mode Suspend current IBUS IDDH IDDS ISUSP Setting of 48 MHz for multiplication selection. No Load fosc = 24 MHz, DMA/media control stopped. No load OSC is stopped *1 XT is used *2 XT is not used *2 *1 — Min. — Typ. 28 18 100 Max. 60 50 300 mA VDD_CORE + VDD_IO Unit Applicable power supply µA — — — — — 25 9 15 10 1 45 18 160 150 100 mA mA µA µA VBUS VDD_CORE + VDD_IO VDD_CORE + VDD_IO VBUS Suspend state OSC is stopped, XT is not used * 1 The values in the Typ. Column indicate reference values at 25°C and 3.0 V (The VBUS currents indicate values at 3.3 V). *1: The temperature condition ranges from –30 to +50°C *2: The ports used as inputs are at VDD_IO or 0 V. Other ports are unloaded. • Flash ROM version (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, VBUS = 3.0 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Mode Symbol Condition fosc = 24 MHz, No load fosc = 24 MHz, DMA/media CPU operation mode IDD control stopped. No load fXT = 32.768 kHz, DMA/media control stopped. No load USB operation mode HALT mode STOP mode Suspend current IBUS IDDH IDDS ISUSP Setting of 48 MHz for multiplication selection No Load fosc = 24 MHz, DMA/media control stopped. No load OSC is stopped *1 XT is used *2 XT is not used *2 *1 — Min. — Typ. 28 18 100 Max. 60 50 300 mA VDD_CORE + VDD_IO Unit Applicable power supply µA — — — — — 25 10 15 10 1 45 20 160 150 100 mA mA µA µA VBUS VDD_CORE + VDD_IO VDD_CORE + VDD_IO VBUS Suspend state, D+/D– fixed OSC is stopped, XT is not used * 1 The values in the Typ. Column indicate reference values at 25°C and 3.0 V (The VBUS currents indicate values at 3.3 V). *1: The temperature condition ranges from –30 to +50°C *2: The ports used as inputs are at VDD_IO or 0 V. Other ports are unloaded. 14/27 FEDL66525-02 OKI Semiconductor ML66525 Family DC Characteristics 2 (USB port) (VBUS = 3.0 to 3.6V, Ta = –30 to +70°C) Parameter Differential input sensitivity Differential common mode range Single ended receiver threshold Symbol VDI VCM VSE 15 kΩ to GND Condition |(D+) – (D–)| Includes VDI Min. 0.2 0.8 0.8 2.8 VBUS – 0.2 2.4 — — — Typ. — — — — — — — — — Max. — 2.5 2.0 — — Unit Applicable pin V D+, D– V V D+, D– PUCTL D+, D– D+, D– “H” output voltage VOH IOH = –100 µA IOH = –4 mA — 0.3 ±10 µA ±10 PUCTL V “L” output voltage VOL 1.5 kΩ to 3.6 V VO = VBUS/0 Output leakage current ILO V VO = VBUS/0 V 15/27 FEDL66525-02 OKI Semiconductor ML66525 Family AC Characteristics (Except USB port) (1) External program memory control (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) PSENn pulse width PSENn pulse delay time Address setup time Address hold time Instruction setup time Instruction hold time Read data access time Symbol tcyc tφWH tφWL tPW tPD tAS tAH tIS tIH tACC VDD_CORE = CL = 50 pF Condition fOSC = 24 MHz Min. 41.67 16.25 16.25 (2 + 2n)tφ – 25 — 2tφ – 25 –10 40 0 — Max. — — — — 55 — — — — (3 + 2n)tφ – 50 ns Unit (Note) tφ = tcyc/2 n = 0 to 3 ( n wait cycles inserted) tcyc CPUCLK tφWH PSENn tPD A0 to A19 tAS D0 to D7 tACC INST0 to 7 tIS tIH PC0 to 19 tAH tPW tφWL Bus timing during no wait cycle time 16/27 FEDL66525-02 OKI Semiconductor ML66525 Family (2) External data memory control (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Clock pulse width (HIGH level) Clock pulse width (LOW level) RDn pulse width WRn pulse width RDn pulse delay time WRn pulse delay time Address setup time Address hold time Read data setup time Read data hold time Read data access time Write data setup time Write data hold time Symbol tcyc tφWH tφWL tRW tWW tRD tWD tAS tAH tRS tRH tACC tWS tWH CL = 50 pF Condition fOSC = 24 MHz Min. 41.67 16.25 16.25 (2 + 2n)tφ – 25 (2 + 2n)tφ – 25 — — tφ – 20 tφ – 20 40 0 — 2tφ – 30 tφ – 6 Max. — — — — — 55 55 — — — — (3 + 2n)tφ – 50 — — ns Unit (Note) tφ = tcyc/2 n = 0 to 7 ( n wait cycles inserted) tcyc CPUCLK tφWH RDn tRD A0 to A19 tAS D0 to D7 tACC WRn tWD A0 to A19 tAS D0 to D7 tWW RAP0 to 19 tAH DOUT0 to 7 tWS Bus timing during no wait cycle time tWH DIN0 to 7 tRS tRH tRW RAP0 to 19 tAH tφWL 17/27 FEDL66525-02 OKI Semiconductor ML66525 Family (3) Serial port control 1. Serial port 1, 6 (SIO1, 6) Master mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 24 MHz Min. 41.67 4 tcyc 2tφ – 10 5tφ – 20 21 0 Max. — — — — — — ns Unit (Note) tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS 18/27 FEDL66525-02 OKI Semiconductor ML66525 Family Slave mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 24 MHz Min. 41.67 4tcyc 2tφ – 30 4tφ – 20 21 7 Max. — — — — — — ns Unit (Note) tφ = tcyc/2 tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS 19/27 FEDL66525-02 OKI Semiconductor ML66525 Family 2. Serial port 4 (SIO4) Master mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 24 MHz Min. 41.67 400 190 130 21 0 Max. — — — — — — ns Unit tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS 20/27 FEDL66525-02 OKI Semiconductor ML66525 Family Slave mode (Clock synchronous serial port) (VDD_CORE = VDD_IO = VREF = 2.4 to 3.6 V, GND = AGND = 0 V, Ta = –30 to +70°C) Parameter Cycle time Serial clock cycle time Output data setup time Output data hold time Input data setup time Input data hold time Symbol tcyc tSCKC tSTMXS tSTMXH tSRMXS tSRMXH CL = 50 pF Condition fOSC = 24 MHz Min. 41.67 400 70 180 21 7 Max. — — — — — — ns Unit tcyc CPUCLK TXC/RXC tSCKC SDOUT (TXD) tSTMXH SDIN (RXD) tSRMXS tSRMXH tSTMXS Measurement points for AC timing (except the serial port) VDD_IO 0V 0.44VDD_IO 0.16VDD_IO 0.44VDD_IO 0.16VDD_IO Measurement points for AC timing (the serial port) VDD_IO 0V 0.8VDD_IO 0.2VDD_IO 0.8VDD_IO 0.2VDD_IO 21/27 FEDL66525-02 OKI Semiconductor ML66525 Family A/D Converter Characteristics (Ta = –30 to +70°C, VREF = 2.4 to 3.6 V, AGND = GND = 0 V) Parameter Resolution Linearity error Differential Linearity error Zero scale error Full-scale error Cross talk Conversion time Symbol n EL ED EZS EFS ECT tCONV Condition Refer to measurement circuit 1 Analog input source impedance RI ≤ 5 kΩ Refer to measurement circuit 2 Set according to ADTM set data Min. — — — — — — 16 Typ. 10 — — — — — — Max. — ±3 ±2 +3 –3 ±1 3906.3 µs/ch LSB Unit Bit Reference voltage 0.1 µF – + VREF 47 µF + VDD_IO + 0.1 µF GND 47 µF +3 V RI AI0 to AI3 AGND CI 0V Analog input RI (impedance of analog input source) ≤ 5 kΩ CI ≅ 0.1 µF Measurement Circuit 1 22/27 FEDL66525-02 OKI Semiconductor ML66525 Family – + 5 kΩ AI0 AI1 0.1 µF to AI3 Analog input Cross talk is the difference between the A/D conversion results when the same analog input is applied to AI0 through AI3 and the A/D conversion results of the circuit to the left. VREF or AGND Measurement Circuit 2 Definition of Terminology 1. Resolution Resolution is the value of minimum discernible analog input. With 10 bits, since 210 = 1024, resolution of (VREF – AGND) ÷ 1024 is possible. 2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between VREF and AGND into 1024 equal steps. 3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the range of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB = (VREF – AGND) ÷ 1024. Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the conversion range. 4. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H. 5. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH. 23/27 FEDL66525-02 OKI Semiconductor ML66525 Family PACKAGE DIMENSIONS (Unit: mm) TQFP100-P-1414-0.50-K Mirror finish 5 Notes for Mounting the Surface Mount Type Packages Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (≥5µm) 0.55 TYP. 4/Oct. 28, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/27 FEDL66525-02 OKI Semiconductor ML66525 Family PACKAGE DIMENSIONS (Unit: mm) P-LFBGA144-1111-0.80 5 Notes for Mounting the Surface Mount Type Packages Package material Ball material Package weight (g) Rev. No./Last Revised Epoxy resin Sn/Pb 0.30 TYP. 1/Aug. 25, 1999 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/27 FEDL66525-02 OKI Semiconductor ML66525 Family REVISION HISTORY Document No. PEDL66525-01 Date Oct. 2000 Page Previous Current Edition Edition – – Description Preliminary edition 1 - Modified contents of P3_2 and P3_3 in the table on Page 8. - Added contents of P9_0 in the table on Page 9. - Modified contents of PUCTL in the table on Page 10. - Partially added contents of “ABSOLUTE MAXIMUM RATINGS”. - Partially added contents of “RECOMMENDED OPERATING CONDITIONS”. - Partially added contents of “ALLOWABLE OUTPUT CURRENT VALUES”. - Partially added contents of “INTERNAL FLASH ROM PROGRAMMING CONDITIONS”. - Partially added contents of “ELECTRICAL CHARACTERISTICS”. - Changed the name from ML66525 to ML66525A. - Changed the name from ML66Q525 to ML66Q525A. - Modified supply current values for ML66Q525 on Page 14. - Modified contents of the table on Page 21. - Changed the name from ML66525A to ML66525B. - Changed the name from ML66Q525A to ML66Q525B. PEDL66525-02 Mar. 2001 – – FEDL66525-01 Oct. 2001 – – FEDL66525-02 Jul. 19, 2002 – – 26/27 FEDL66525-02 OKI Semiconductor ML66525 Family NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 3. 4. 5. 6. 7. 8. 27/27