MSC1212-01

E2C0021-27-Y3 ¡ Semiconductor ¡ Semiconductor MSC1212-01 48-Bit Grid/Anode Driver This version: Nov. 1997 MSC1212-01 Previous version: Jul. 1996 GENERAL DESCRIPTION The MSC1212-01 is a driver IC for VFD implemented in BiCMOS technology. The circuit consists of a 48-bit shift register and a 48-bit latch; they control display data, which is output from the display drivers. Since a 64-pin plastic QFP package is used, the display unit size can be reduced. FEATURES • Logic supply voltage (VCC) • Driver supply voltage (VDISP) • Operating temperature range • Driver output current : : : : 4.5 to 5.5 V 8 to 18 V –40 to +105°C IO2-1 = –6 mA (for only one driver on state) IO2-2 = –50 mA (total current for all drivers on state) IO2-3 = 0.2 mA • Built-in 48-bit output Driver (with latch) • Built-in 48-bit shift register • Clock frequency : 0.5 MHz • Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSC1212-01GS-BK) 1/11 ¡ Semiconductor MSC1212-01 BLOCK DIAGRAM VDISP VCC CL CHG VCC LS DIN CLK C SI I1 48-BIT LATCH I48 O48 HVO48 DOUT L O1 HVO 1 PO1 48-BIT S/R L-GND D-GND PO48 SO 2/11 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) ,  HVO 17 HVO 16 HVO 15 HVO 14 HVO 13 HVO 12 HVO 11 HVO 10 HVO 9 HVO 8 HVO 7 HVO 6 HVO 5 HVO 4 HVO 3 HVO 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MSC1212-01 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC HVO 18 HVO 19 HVO 20 HVO 21 HVO 22 HVO 23 HVO 24 HVO 25 HVO 26 HVO 27 HVO 28 HVO 29 HVO 30 HVO 31 NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HVO 32 HVO 33 HVO 34 HVO 35 HVO 36 HVO 37 HVO 38 HVO 39 HVO 40 HVO 41 HVO 42 HVO 43 HVO 44 HVO 45 HVO 46 HVO 47 HVO1 NC VDISP D-GND L-GND DIN CLK LS CL CHG VCC DOUT D-GND VDISP NC HVO 48 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC: No-connection pin 64-Pin Plastic QFP 3/11 ¡ Semiconductor MSC1212-01 INPUT AND OUTPUT CONFIGURATION • Schematic Diagrams of Logic Portion Input Circuit VDISP VCC INPUT GND GND • Schematic Diagrams of Logic Portion Input • Schematic Diagrams of Logic Portion Input Circuit (Pull-down) Circuit (Pull-up) VDISP VCC VDISP VCC INPUT INPUT GND GND GND GND • Schematic Diagrams of Logic Portion Output • Schematic Diagrams of Driver Output Circuit Circuit VCC VCC VDISP VDISP OUTPUT OUTPUT GND GND GND GND 4/11 ¡ Semiconductor MSC1212-01 PIN DESCRIPTION Function Driver Output Pin 1 to 17 32 to 48 50 to 63 Driver Power Supply Logic Power Supply Driver GND Logic GND Data Input 19, 30 27 20, 29 21 22 Symbol HVO1 to HVO48 VDISP VCC D-GND L-GND DIN Power supply pins for driver circuit. Both Pin 19 and 30 should be connected externally. Power supply pin for logic. GND pins for the driver circuit. Both Pin 20 and 29 should be connected externally. GND pin for the logic circuit. Input pin without pull-up or pull-down resistor. Input pin of shift register. Display data input is synchronized with clock signal. (positive logic) Input pin without pull-up or pull-down resistor. Clock Input 23 CLK Data of shift register is shifted from one stage to the next on application of each clock rising edge. Input pin without pull-up or pull-down resistor. Latch Strobe Input 24 LS When LS is at "H" level, the latch is shunted and the shift register output becomes the lacth output. When LS is at "L" level, the lacth holds the shift register output just bafore LS goes to "L" level. Clear input pin with pull-up resistor. Normally "L" Clear Input 25 CL level. In this condition, driver output changes to "H" or "L" according to latch output level. When CL is "H", all driver output pins are fixed to "L". Test input pin with pull-down resistor. Normally "L" level, but here, if CL="H", then driver output changes Test Input 26 CHG to "H" or "L" according to latch output level. If CL = "L" when CHG is at "H" level, all driver output is fixed to "H" for test. Data Output 28 DOUT Serial output pin of shift register. Description Driver output pins, applicable to each bit of shift register. 5/11 ¡ Semiconductor MSC1212-01 ABSOLUTE MAXIMUM RATINGS Parameter Logic Supply Voltage Input Voltage Data Output Voltage Power Dissipation Thermal Resistance Storage Temperature *3 *1 *1 *1 Driver Supply Voltage *1, *2 Symbol VCC VDISP VIN VO1 VO2 PD Rj-a TSTG Condition — — Applicable to all input pins Applicable to data output pin Applicable to driver output pin Ta £ 25°C — — Rating –0.3 to +6.5 –0.3 to +20 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VDISP +0.3 1.0 120 –55 to +150 Unit V V V V V W °C/W °C Driver Output Voltage *1 *1 Maximum supply voltage with respect to L-GND and D-GND *2 Catastrophic breakdown may occur if the applied voltage is more than the rating. *3 Thermal resistance of package (between junction and atmosphere) The junction temperature (Tj) given by the following formula should not exceed 150°C. Tj = P ¥ Rj-a + Ta (P is the maximum power dissipation) 6/11 ¡ Semiconductor MSC1212-01 RECOMMENDED OPERATING CONDITIONS Parameter Logic Supply Voltage Driver Supply Voltage High Level Input Voltage Low Level Input Voltage Logic Output Current Driver High Level Output Current Driver High Level Output Current Driver Low Level Output Current CLK Frequency Data Setup Time Data Hold Time LS Pulse Width CHG Pulse Width CL Pulse Width CLK Pulse Width CLK-LS Delay Time LS-CLK Delay Time LS-CHG Delay Time LS-CL Delay Time Operating Temperature Symbol VCC VDISP VIH VIL IO1 IO2-1 IO2-2 IO2-3 fCLK tDS tDH tWLS tWCHG tWCL tWCLK tDCLK-LS tWLS-CLK tWLS-CHG tWLS-CL Top Condition Applicable to logic supply voltage pin Applicable to driver supply voltage pin Min. 4.5 8 0.8 VCC — –0.1 — — — — 400 300 125 10 10 500 525 0 0 0 –40 Max. 5.5 18 — 0.2 VCC 0.1 –6 –50 0.2 0.5 — — — — — — — — — — 105 Unit V V V V mA mA mA mA MHz ns ns ns ms ms ns ns ns ns ns °C Applicable to all input pins Applicable to all input pins Applicable to DOUT pin Only one driver is ON state Total current at all driver outputs are ON state Applicable to all driver output pins See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram — 7/11 ¡ Semiconductor MSC1212-01 ELECTRICAL CHARACTERISTICS DC Characteristics (VCC = 4.5 to 5.5 V, VDISP = 8 to 18 V, Ta = –40 to +105°C) Parameter Logic Power Supply Current Driver Power Supply Current High Level Input Threshold Voltage Low Level Input Threshold Voltage Hysteresis Voltage High Level Input Current Low Level Input Current High Level Data Output Current Low Level Data Output Current Driver High Level Output Current Driver Low Level Output Current Voltage Difference Between GND Pins IOL1 IOH2 IOL2 VGND Symbol ICC1 ICC2 IDISP VP VN VH IIH1 IIH2 IIL1 IIL2 IOH1 No Load No Load All input pins All input pins All input pins VI = VCC VI = 0V CHG pin Input pins except CHG pin CL pin Input pins except CL pin VCC = 4.5 V VCC = 5.5 V VCC = 4.5 V VCC = 5.5 V Condition fCLK = 0 Hz fCLK = 0.5 MHz Min. — — — 2.4 2.9 — — 0.3 100 –1 –600 –1 –0.1 0.1 –6 0.2 –0.1 Typ. 2 4 — 2.75 3.25 1.75 2.25 1 — — — — — — — — 0 Max. 4 6 5 — — 2.1 2.6 — 600 1 –100 1 — — — — 0.1 Unit mA mA V V V V V mA mA mA mA mA mA mA mA V VCC–VOH1 = 1.0 V VOL1 = 1.0 V Only one driver is ON state VDISP–VOH2 = 1.0 V VOL2 = 1.0 V Voltage difference between D-GND and L-GND *1 *1 Pin D-GND and Pin L-GND are not connected internally. Therefore, set the voltage between D-GND and L-GND at the same level by connecting both pins externally. AC Characteristics (VCC = 4.5 to 5.5 V, VDISP = 8 to 18 V, Ta = –40 to +105°C) Parameter CLK-Dout Delay Time Delay Time Low Æ High Transit Time Low Æ High Delay Time High Æ Low Transit Time High Æ Low Symbol tPD tDLH tTLH tDHL tTHL Condition See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram See Timing Diagram Min. 0.3 — — — — Typ. — 1.0 2.0 1.0 2.0 Max. 1.6 2.0 5.0 2.0 5.0 Unit ms ms ms ms ms 8/11 tWCLK 1/fCLK CLK T1/2 T3/4 T47/48 T1/2 T3/4 TIMING DIAGRAM tDS tDH ¡ Semiconductor DIN tPD tPD DOUT tDCLK-LS tDLS-CLK LS tWLS tDLS-CHG tWCHG tWCHG CHG tDLS-CL tWCL tWCL CL tDLH tDLH tDHL tDHL HVO (1, 2, 47, and 48) HVO (Others) tTLH tTLH tTHL tTHL MSC1212-01 9/11 ¡ Semiconductor MSC1212-01 FUNCTIONAL DESCRIPTION Function Table CLOCK DIN H L CL H L L L L CHG X H L L L PO1 PO2 H L PO3 PO4 . . . . . . . . . . . . . . . . . . . . . . . . . PO46 PO47 PO48 DOUT PO1k PO2k PO1k PO2k LS X X H H L POn X X H L X PO3k . . . . . . . . . . . . . . . . . . . . . . . . . PO45k PO46k PO47k PO47k PO3k . . . . . . . . . . . . . . . . . . . . . . . . . PO45k PO47k PO47k PO47k HVOn L H H L NC L: Low Level, H: High Level, X: Don't Care, NC: No Change 10/11 ¡ Semiconductor MSC1212-01 PACKAGE DIMENSIONS (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 11/11