MSC2313258D-XXBS2

This version: Feb. 23. 1999 Semiconductor MSC2313258D-xxBS2/DS2 1,048,576-word x 32-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The MSC2313258D-xxBS2/DS2 is a fully decoded, 1,048,576-word x 32-bit CMOS dynamic random access memory module composed of two 16Mb DRAMs in SOJ packages mounted with four decoupling capacitors on a 72-pin glass epoxy single-inline package. This module supports any application where high density and large capacity of storage memory are required. FEATURES · 1,048,576-word x 32-bit organization · 72-pin socket insertable module MSC2313258D-xxBS2 : Gold tab MSC2313258D-xxDS2 : Solder tab · Single +5V supply ± 10% tolerance · Input : TTL compatible · Output : TTL compatible, 3-state · Refresh : 1024cycles/16ms · /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability · Fast page mode capability PRODUCT FAMILY Access Time (Max.) Family tRAC MSC2313258D-60BS2/DS2 MSC2313258D-70BS2/DS2 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns Cycle Time (Min.) Operating(Max.) Standby(Max.) Power Dissipation 104ns 124ns 1375mW 11mW 1265mW Semiconductor MSC2313258D MODULE OUTLINE MSC2313258D-xxBS2/DS2 107.95±0.2*1 101.19Typ. (Unit : mm) 5.28Max. 3.38Typ.  3.18 19.0±0.2 Typ. Typ. 10.16 6.35 2.03Typ. 6.35Typ. 6.0Min. 1 1.27±0.1 R1.57 6.35 95.25 1.04Typ. 72 +0.1 1.27 -0.08 *1 The common size difference of the board width 12.5mm of its height is specified as ±0.2. The value above 12.5mm is specified as ±0.5. Semiconductor MSC2313258D PIN CONFIGURATION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 NC /RAS2 NC NC Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin Name NC NC VSS /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 NC NC /WE NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS Presence Detect Pins MSC2313258D -60BS2/DS2 VSS VSS NC NC MSC2313258D -70BS2/DS2 VSS VSS VSS NC Pin No. 67 68 69 70 Pin Name PD1 PD2 PD3 PD4 Semiconductor MSC2313258D BLOCK DIAGRAM A0-A9 /CAS0 /CAS1 /WE A0-A9 /RAS0 /RAS /LCAS /UCAS /WE /OE VSS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A9 /RAS2 /RAS /LCAS /UCAS /WE /OE VSS /CAS2 /CAS3 VCC C1-C4 VSS DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 VCC DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Semiconductor MSC2313258D ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings ( Ta = 25°C ) Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD TOPR TSTG Rating -1.0 to +7.0 -1.0 to +7.0 50 2 0 to +70 -40 to +125 Unit V V mA W °C °C Recommended Operating Conditions ( Ta = 0°C to +70°C ) Parameter Power Supply Voltage VSS Input High Voltage Input Low Voltage VIH VIL 0 2.4 -1.0 0 0 6.5 0.8 V V V Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V Capacitance ( VCC = 5V ± 10%, Ta = 25°C, f = 1 MHz ) Parameter Input Capacitance (A0 - A9) Input Capacitance (/WE) Input Capacitance (/RAS0, /RAS2) Input Capacitance (/CAS0- /CAS3) I/O Capacitance (DQ0 - DQ31) Symbol CIN1 CIN2 CIN3 CIN4 CDQ Typ. Max. 21 20 13 13 18 Unit pF pF pF pF pF Note: Capacitance measured with Boonton Meter. Semiconductor MSC2313258D DC Characteristics (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Symbo l MSC2313258D -60BS2/DS2 Min. Input Leakage Current ILI 0V ≤ VIN ≤ 6.5V: All other pins not under test = 0V Data out is disable 0V ≤ VOUT ≤ 5.5V IOH = -5.0mA IOL = 4.2mA /RAS cycling, /CAS cycling, tRC = m in. /RAS = VIH /CAS = VIH /RAS cycling, /CAS = VIH, tRC = m in. tRC = m in. /RAS = VIL, /CAS cycling, tPC = m in. TTL MOS -20 Max. 20 MSC2313258D -70BS2/DS2 Min. -20 Max. 20 µA Parameter Condition Unit Note Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Power supply current (Standby) Average Power Supply Current (/RAS only refresh) Average Power Supply Current (/CAS before /RAS refresh) Average Power Supply Current (Fast Page Mode) ILO VOH VOL ICC1 -10 2.4 0 - 10 VCC 0.4 250 4 2 250 -10 2.4 0 - 10 VCC 0.4 230 4 2 230 µA V V mA mA mA mA 1, 2 1 1 1, 2 ICC2 ICC3 ICC6 - 250 - 230 mA 1, 2 ICC7 - 250 - 230 mA 1, 3 Notes: 1. ICC is dependent on output loading and cycles rates. Specified values are obtained with the output open. 2. Address can be changed once or less while /RAS = VIL. 3. Address can be changed once or less while /CAS = VIH. Semiconductor MSC2313258D AC Characteristics (1/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3 Parameter Symbol MSC2313258D -60BS2/DS2 Min. Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from /CAS Precharge Output Low Impedance Time from /CAS Data Output Hold After /CAS Low /CAS to Data Output Buffer Turn-off Delay Time /RAS to Data Output Buffer Turn-off Delay Time /WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode with EDO) /RAS Hold Time /CAS Precharge Time (Fast Page Mode with EDO) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to /RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS tRC tHPC tRAC tCAC tAA t CPA tCLZ tDOH tCEZ tREZ tWEZ tT tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH 104 25 0 5 0 0 0 1 40 60 60 10 10 10 40 5 35 14 12 0 10 0 10 30 0 0 0 Max. 60 15 30 35 15 15 15 50 16 10K 100K 10K 45 30 MSC2313258D -70BS2/DS2 Min. 124 30 0 5 0 0 0 1 50 70 70 13 10 13 45 5 40 14 12 0 10 0 13 35 0 0 0 Max. 70 20 35 40 20 20 20 50 16 10K 100K 10K 50 35 ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 5 6 7, 8 7, 8 7 3 4, 5, 6 4, 5 4, 6 4 4 Unit Note Semiconductor MSC2313258D AC Characteristics (2/2) (VCC = 5V ± 10%, Ta = 0°C to +70°C ) Note: 1, 2, 3 Parameter Symbol MSC2313258D -60BS2/DS2 Min. Write Command Set-up Time Write Command Hold Time Write Command Pulse Width /WE Pulse Width (DQ Disable) Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Set-up Time Data-in Hold Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) tWCS tWCH tWP tWPE tRWL tCWL tDS tDH tRPC tCSR 0 10 10 10 10 10 0 10 5 5 Max. MSC2313258D -70BS2/DS2 Min. 0 13 10 10 13 13 0 13 5 5 Max. ns ns ns ns ns ns ns ns ns ns Unit Note tCHR 10 - 10 - ns Semiconductor MSC2313258D Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assumes tT = 2ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition time (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tCEZ(Max.), tREZ(Max.) and tWEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle.