MSC2323258A-XXBS4

¡ Semiconductor MSC2323258A-xxBS4/DS4 DESCRIPTION ¡ Semiconductor MSC2323258A-xxBS4/DS4 2,097,152-Word ¥ 32-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO 1 The Oki MSC2323258A-xxBS4/DS4 is a fully decoded 2,097,152-word ¥ 32-bit CMOS dynamic random access memory composed of two 16-Mb (1M ¥ 16) DRAMs in SOJ. The mounting of two DRAMs together with decoupling capacitors on a 72-pin glass epoxy SIMM Package supports any application where high density and large capacity of storage memory are required. FEATURES • 2,097,152-word ¥ 32-bit organization • 72-pin SIMM MSC2323258A-xxBS4 : Gold tab MSC2323258A-xxDS4 : Solder tab • Single 5 V supply ± 10% tolerance • Input : TTL compatible • Output : TTL compatible, 3-state, nonlatch • Refresh : 1024 cycles/16 ms • CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability • Fast Page Mode with EDO capability PRODUCT FAMILY Family MSC2323258A-60BS4/DS4 MSC2323258A-70BS4/DS4 Access Time (Max.) tRAC 60 ns 70 ns tAA 30 ns 35 ns tCAC 15 ns 20 ns Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) 110 ns 130 ns 2475 mW 2255 mW 22 mW 77 MSC2323258A-xxBS4/DS4 ¡ Semiconductor PIN CONFIGURATION MSC2323258A-xxBS4/DS4 (Unit : mm) *1 107.95 ±0.2 101.19 Typ. 9.3 Max. 3.38 Typ. f 3.18 19.0 ±0.2 Typ. Typ. 10.16 6.35 2.03 Typ. 1.27 ±0.2 6.35 Typ. 1 R1.57 6.35 95.25 1.04 Typ. 72 6.0 Min. +0.1 1.27 –0.08 *1 The common size difference of the board width 12.5 mm of its height is specified as ±0.2. The value above 12.5 mm is specified as ±0.5. Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 Pin No. Pin Name 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC Vcc Pin No. Pin Name 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 A8 A9 RAS3 RAS2 NC NC NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 Pin No. Pin Name 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 NC WE NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 Pin No. Pin Name 61 62 63 64 65 66 67 68 69 70 71 72 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS Presence Detect Pins Pin No. 67 68 69 70 Pin Name PD1 PD2 PD3 PD4 MSC2323258A -60BS4/DS4 NC NC NC NC MSC2323258A -70BS4/DS4 NC NC VSS NC 78 ¡ Semiconductor MSC2323258A-xxBS4/DS4 BLOCK DIAGRAM A0 - A9 CAS0 CAS1 WE 1 A0 - A9 RAS0 RAS LCAS UCAS WE OE DQ0 DQ1 DQ2 DQ0 DQ1 DQ2 DQ0 DQ1 DQ2 A0 - A9 RAS LCAS UCAS WE RAS1 DQ15 VSS VCC DQ15 DQ15 VCC VSS OE A0 - A9 RAS2 RAS LCAS UCAS WE OE DQ0 DQ1 DQ2 DQ16 DQ17 DQ18 DQ0 DQ1 DQ2 A0 - A9 RAS LCAS UCAS WE RAS3 DQ15 VSS VCC DQ31 DQ15 VCC VSS OE CAS2 CAS3 VCC C1 VSS C8 79 MSC2323258A-xxBS4/DS4 ¡ Semiconductor ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD Topr Tstg Rating –1.0 to 7.0 –1.0 to 7.0 50 4 0 to 70 –40 to 125 Unit V V mA W °C °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (Ta = 0°C to 70°C) Min. 4.5 0 2.4 –1.0 Typ. 5.0 0 — — Max. 5.5 0 6.5 0.8 Unit V V V V Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Capacitance Parameter Input Capacitance (A0 - A9) Input Capacitance (WE) Input Capacitance (RAS0 - RAS3) Input Capacitance (CAS0 - CAS3) I/O Capacitance (DQ0 - DQ31) Symbol CIN1 CIN2 CIN3 CIN4 CDQ Typ. — — — — — Max. 27 35 13 20 20 (Ta = 25°C, f = 1 MHz) Unit pF pF pF pF pF Note : Capacitance measured with Boonton Meter. 80 ¡ Semiconductor MSC2323258A-xxBS4/DS4 DC Characteristics MSC2323258A Parameter Symbol (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSC2323258A -70BS4/DS4 Min. –40 Max. 40 Unit Note Condition 0 V £ VI £ 6.5 V; -60BS4/DS4 Min. Max. 40 1 Input Leakage Current ILI All other pins not under test = 0 V DOUT disable 0 V £ VO £ 5.5 V IOH = –5.0 mA IOL = 4.2 mA RAS, CAS cycling, tRC = Min. RAS, CAS = VIH –40 µA Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ILO VOH VOL ICC1 –20 2.4 0 — — — 20 VCC 0.4 450 8 4 –20 2.4 0 — — — 20 VCC 0.4 410 8 4 µA V V mA mA mA 1, 2 1 1 ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS cycling, — 450 — 410 mA 1, 2 ICC6 CAS before RAS, tRC = Min. RAS = VIL, — 450 — 410 mA 1, 2 ICC7 CAS cycling, tHPC = Min. — 450 — 410 mA 1, 3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. Address can be changed once or less while RAS=VIL. 3. Address can be changed once or less while CAS=VIH. 81 MSC2323258A-xxBS4/DS4 ¡ Semiconductor AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSC2323258A MSC2323258A -70BS4/DS4 Min. Max. 130 30 — — — — 0 5 0 0 0 3 — 50 70 70 20 10 10 45 5 40 20 15 70 0 10 0 15 45 35 — — 70 20 35 40 — — 15 15 15 50 16 — 10k 100k — — 10k — — — 50 35 — — — — — — — Symbol Note 1,2,3 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 7, 8 7, 8 7 3 4, 5, 6 4, 5 4, 6 4 4 Parameter Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Output Low Impedance Time from CAS Output Hold Time from CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Precharge Time CAS Pulse Width RAS Low to CAS High Delay Time CAS High to RAS Low Delay Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time RAS to Second CAS Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time -60BS4/DS4 Min. Max. 110 25 — — — — 0 5 0 0 0 3 — 40 60 60 15 10 10 40 5 35 20 15 60 0 10 0 15 40 30 — — 60 15 30 35 — — 15 15 15 50 16 — 10k 100k — — 10k — — — 45 30 — — — — — — — tRC tHPC tRAC tCAC tAA tCPA tCLZ tDOH tCEZ tREZ tWEZ tT tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tRSCD tASR tRAH tASC tCAH tAR tRAL 82 ¡ Semiconductor MSC2323258A-xxBS4/DS4 AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSC2323258A MSC2323258A -70BS4/DS4 Min. Max. 0 0 0 0 15 45 15 10 20 20 0 15 45 5 5 15 — — — — — — — — — — — — — — — — Symbol Note 1,2,3 Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS -60BS4/DS4 Min. Max. 0 0 0 0 10 40 10 5 15 15 0 15 40 5 5 10 — — — — — — — — — — — — — — — — tRCS tRCH tRRH tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR 1 9 9 Write Command Pulse Width (Output Disable) tWPE CAS Active Delay Time from RAS Precharge tRPC RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) tCHR 83 MSC2323258A-xxBS4/DS4 Notes: ¡ Semiconductor 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.) and tWEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. See ADDENDUM H for AC Timing Waveforms 84