MSC23409CL-XXDS9

E2H0093-15-90 ¡ Semiconductor ¡ Semiconductor MSC23409C/CL-xxDS9 DESCRIPTION This version: Sep. 1995 MSC23409C/CL-xxDS9 4,194,304-Word ¥ 9-Bit DRAM MODULE : FAST PAGE MODE TYPE The OKI MSC23409C/CL-xxDS9 is a fully decoded 4,194,304-word ¥ 9-bit CMOS Dynamic Random Access Memory Module composed of nine 4-Mb DRAMs (4M ¥ 1) in SOJ packages mounted with nine decoupling capacitors on a 30-pin glass epoxy single-inline package. This module is generally used for memory expansion in parity applications such as workstations. The low-power version (CL) offers reduced power consumption for mobile computing applications like laptops and palmtops. FEATURES • 4-Meg ¥ 9-bit organization • 30-Pin Socket Insertable Module MSC23409C/CL-xxDS9 : Solder tab • Single 5 V supply ± 10% tolerance • Access times : 60, 70, 80 ns • Input : TTL compatible • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms (128 ms : L-version) • CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Fast Page Mode capability PRODUCT FAMILY Family MSC23409C/CL-60DS9 MSC23409C/CL-70DS9 MSC23409C/CL-80DS9 Access Time (Max.) tRAC 60 ns 70 ns 80 ns tAA 30 ns 35 ns 40 ns tCAC 15 ns 20 ns 20 ns Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) 110 ns 130 ns 150 ns 4950 mW 4455 mW 3960 mW 49.5 mW/ 9.9 mW (L-version) 1/13 ¡ Semiconductor MSC23409C/CL-xxDS9 PIN CONFIGURATION MSC23409C/CL-xxDS9 3.38 Tpy. f 3.18 20.45 Max. Typ. 10.16 Typ. 6.35 88.9 ±0.2 82.14 Typ. *1 5.28 Max. 1 5.59 Typ. 2.54 ±0.1 73.66 1.78 Typ. 30 2.54 Min. +0.1 1.27 –0.08 2.03 Typ. *1 The common size difference of the board width 12.5 mm of its height is specified as ±0.2. The value above 12.5 mm is specified as ±0.5. Pin No. 1 2 3 4 5 6 7 8 9 10 Pin Name VCC CAS DQ0 A0 A1 DQ1 A2 A3 VSS DQ2 Pin No. 11 12 13 14 15 16 17 18 19 20 Pin Name A4 A5 DQ3 A6 A7 DQ4 A8 A9 A10 DQ5 Pin No. 21 22 23 24 25 26 27 28 29 30 Pin Name WE VSS DQ6 NC DQ7 Q8 RAS CAS8 D8 VCC 2/13 ¡ Semiconductor MSC23409C/CL-xxDS9 BLOCK DIAGRAM A0 - A10 RAS0 CAS0 WE A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS DQ0 A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS A0 - A10 RAS D CAS Q WE VCC VSS DQ4 DQ1 DQ5 DQ2 DQ6 DQ3 DQ7 CAS8 D8 Q8 VCC VSS C1 C9 3/13 ¡ Semiconductor MSC23409C/CL-xxDS9 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD Topr Tstg Rating –1.0 to 7.0 –1.0 to 7.0 50 9 0 to 70 –40 to 125 Unit V V mA W °C °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 –1.0 Typ. 5.0 0 — — Max. 5.5 0 6.5 0.8 (Ta = 0°C to 70°C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A10) Input Capacitance (RAS, CAS, WE) I/O Capacitance (DQ0 - DQ7) Input Capacitance (CAS8) Input Capacitance (D8) Output Capacitance (Q8) Symbol CIN1 CIN2 CDQ CIN3 CIN4 COUT Typ. — — — — — — Max. 64 73 19 13 12 13 (Ta = 25°C, f = 1 MHz) Unit pF pF pF pF pF pF Note : Capacitance measured with Boonton Meter. 4/13 ¡ Semiconductor DC Characteristics MSC23409C/CL-xxDS9 (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSC23409C/CL MSC23409C/CL MSC23409C/CL Symbol Parameter Condition 0 V £ VI £ 6.5 V; -60DS9 -70DS9 -80DS9 Unit Note Min. Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) ICC7 ICC6 ICC3 ICC2 ICC1 ILO VOH VOL DOUT disable 0 V £ VO £ 5.5 V IOH = –5.0 mA IOL = 4.2 mA RAS, CAS cycling, tRC = Min. RAS, CAS = VIH RAS, CAS ≥ VCC –0.2 V RAS cycling, CAS = VIH, tRC = Min. RAS cycling, CAS before RAS, tRC = Min. RAS = VIL, CAS cycling, tPC = Min. tRC = 125 µs, ICC10 CAS before RAS cycling — — — — –10 2.4 0 — — — — –90 Max. 90 Min. –90 Max. 90 Min. –90 Max. 90 µA 10 VCC 0.4 900 18 9 1.8 900 –10 2.4 0 — — — — — 10 VCC 0.4 810 18 9 1.8 810 –10 2.4 0 — — — — — 10 VCC 0.4 720 18 9 1.8 720 µA V V mA 1, 2 mA mA 1 1 mA 1, 5 mA 1, 2 900 — 810 — 720 mA 1, 2 720 — 630 — 540 mA 1, 3 2.7 — 2.7 — 2.7 mA 1, 2 4, 5 Notes: 1. 2. 3. 4. 5. Specified values are obtained with the output open. Address can be changed once or less while RAS=VIL. Address can be changed once or less while CAS=VIH. VCC - 0.2 V ≤ VIH ≤ 6.5 V, -1.0 V ≤ VIL ≤ 0.2 V. L-version. 5/13 ¡ Semiconductor AC Characteristics (1/2) MSC23409C/CL-xxDS9 (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol -60DS9 -70DS9 -80DS9 Note 1,2,3,9,10 Unit Note ns ns ns 4, 5, 6 ns 4, 5 ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4, 6 4 4 7 3 MSC23409C/CL MSC23409C/CL MSC23409C/CL Parameter Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Output Low Impedance Time from CAS Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Precharge Time CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Min. tRC tPC tRAC tCAC tAA tCPA tCLZ tOFF tT tREF tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL 110 40 — — — — 0 0 3 — — 40 60 60 15 10 15 60 5 20 15 0 10 0 15 50 30 Max. — — 60 15 30 35 — 15 50 16 128 — 10K 100K — — 10K — — 45 30 — — — — — — Min. 130 45 — — — — 0 0 3 — — 50 70 70 20 10 20 70 5 20 15 0 10 0 15 55 35 Max. — — 70 20 35 40 — 20 50 16 128 — 10K 100K — — 10K — — 50 35 — — — — — — Min. 150 50 — — — — 0 0 3 — — 60 80 80 20 10 20 80 5 20 15 0 10 0 15 60 40 Max. — — 80 20 40 45 — 20 50 16 128 — 10K 100K — — 10K — — 60 40 — — — — — — 6/13 ¡ Semiconductor AC Characteristics (2/2) MSC23409C/CL-xxDS9 (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3,9,10 MSC23409C/CL MSC23409C/CL MSC23409C/CL Symbol -60DS9 -70DS9 -80DS9 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 Min. tRCS tRCH tRRH tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR 0 0 0 0 10 45 10 15 15 0 15 50 5 5 10 30 10 10 10 10 Max. Min. — — — — — — — — — — — — — — — — — — — — 0 0 0 0 10 50 10 20 20 0 15 55 5 5 10 35 10 10 10 10 Max. — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 10 60 10 20 20 0 15 60 5 5 10 40 10 10 10 10 Max. — — — — — — — — — — — — — — — — — — — — CAS Active Delay Time from RAS Precharge tRPC RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) CAS Precharge Time (Refresh Counter Test) tCHR tCPT WE to RAS Precharge Time (CAS before RAS) tWRP WE Hold Time from RAS (CAS before RAS) tWRH RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tWTS tWTH 7/13 ¡ Semiconductor Notes: MSC23409C/CL-xxDS9 1. A start-up delay of 200 µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. 2. AC mesurement assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times are measured between VIH and VIL. 4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tOFF (Max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. RA10, CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin will indicate a high level. If any internal bits are not equal, then data output pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operational state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 10. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. 8/13 ¡ Semiconductor MSC23409C/CL-xxDS9 TIMING WAVEFORM Read Cycle tRC VIH – RAS V – IL tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – tRCD tRAS tCSH tRSH tCAS tRP tCRP Row WE VIH – VIL – DQ0-7 VOH – Q8 VOL – Write Cycle (Early Write) VIH – RAS V – IL tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – Row VIH – WE VIL – DQ0-7 VIH – D8 VIL – ,, ,,, tRAD tRAH tASC tRAL tCAH Column tAR tRCS tRRH tRCH tCAC tAA tRAC tCLZ tOFF Open Valid Data-out "H" or "L" tRC tRAS tRP tCSH tRCD tAR tRSH tCRP tCAS tRAD tRAH tASC tRAL tCAH Column tWCR tCWL tWCS tWCH tWP tDHR tRWL tDS tDH Valid Data-in Note: Q8 = "Open" "H" or "L" 9/13 ¡ Semiconductor Fast Page Mode Read Cycle tRASP RAS VIH – VIL – tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – tRAH Row MSC23409C/CL-xxDS9 tRP tCSH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tCRP WE VIH – VIL – DQ0-7 VOH – Q8 VOL – Fast Page Mode Write Cycle (Early Write) RAS VIH – VIL – tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – tRAH Row VIH – WE VIL – DQ0-7 VIH – D8 VIL – , ,, tCAH tASC tCAH tASC tRAL tCAH Column Column Column tRAD tRCH tRCS tRCS tRCH tRRH tRCS tRCH tCAC tCAC tCAC tAA tAA tAA tRAC tCPA tCPA Valid Data-out tCLZ tOFF tCLZ Valid Data-out tOFF tCLZ Valid Data-out tOFF "H" or "L" tRASP tRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tCRP tCSH tAR tASC tCAH tASC tCAH tASC tRAL tCAH Column Column Column tWCR tRWL tWCS tCWL tWCH tWP tDH tWCS tCWL tWCH tWP tDH tWCS tCWL tWCH tWP tDH tDS tDS tDS Valid Data-in Valid Data-in Valid Data-in tDHR Note: Q8 = "Open" "H" or "L" tAR tASC 10/13 ¡ Semiconductor RAS-Only Refresh Cycle RAS VIH – VIL – tCRP tRAS CAS VIH – CAS8 VIL – tASR tRAH Address VIH – VIL – tOFF DQ0-7 VOH – Q8 VOL – Row CAS before RAS Refresh Cycle RAS VIH – VIL – tRPC tCP tCSR tCHR CAS VIH – CAS8 VIL – tWRP WE VIH – VIL – tOFF DQ0-7 VOH – Q8 VOL – tWRH Open Note: Address = "H" or "L" , ,, MSC23409C/CL-xxDS9 tRC tRP tRPC Open Note: WE = "H" or "L" "H" or "L" tRC tRAS tRP tRPC tWRP "H" or "L" 11/13 ¡ Semiconductor Hidden Refresh Read Cycle RAS VIH – VIL – tCRP VIH – VIL – tASR CAS CAS8 Address VIH – VIL – Row WE DQ0-7 Q8 VIH – VIL – VOH – VOL – Hidden Refresh Write Cycle V– RAS IH VIL – tCRP CAS VIH – CAS8 VIL – tASR Address VIH – VIL – Row WE VIH – VIL – DQ0-7 VIH – D8 VIL – ,,, ,,, tRC tRAS tRP tRAS tRCD tRSH tCHR tRAD tRAH tASC tRAL tCAH Column tRCS tAR tRRH tWRP tWRH tCAC tRAC tAA tOFF Valid Data-out tCLZ "H" or "L" tRC tRAS tRP tRAS tRCD tRSH tCHR tRAD tAR tRAH tASC tRAL tCAH Column tWCR tWCS tRWL tWCH tWP tWRP tWRH tDS tDH Valid Data-in tDHR Note: Q8 = "Open" "H" or "L" MSC23409C/CL-xxDS9 12/13 ¡ Semiconductor CAS before RAS Refresh Counter Test Cycle tRAS VIH – VIL – tCSR CAS VIH – CAS8 VIL – V– Address IH VIL – Read Cycle DQ0-7 VOH – Q8 VOL – WE VIH – VIL – tWRP RAS tWRP Write Cycle WE VIH – VIL – DQ0-7 VIH – D8 VIL – Q8 VOH – VOL – WE • CAS before RAS Refresh Cycle tRP RAS VIH – VIL – CAS VIH – CAS8 VIL – WE VIH – VIL – DQ0-7 VOH – Q8 VOL – ,, ,, , tRP tRSH tCHR tCPT tCAS tASC tCAH Column tCAC tRAL tAA tOFF Open Valid Data-out tWRH tRCS tCLZ tRRH tRCH tWRH tWCS tRWL tCWL tWCH tWP tDS tDH Valid Data-in Open "H" or "L" tRC tRAS tRPC tCP tCSR tCHR tWTS tWTH tOFF Open Note : Address = "H" or "L" "H" or "L" MSC23409C/CL-xxDS9 13/13