MSC23S4721E-8BS18

MSC23S4721E-8BS18 (98.07.17) Semiconductor MSC23S4721E-8BS18 4,194,304 Word x 72 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK): DESCRIPTION The Oki MSC23S4721E-8BS18 is a fully decoded, 4,194,304 x 72bit synchronous dynamic random access memory composed of eighteen 16Mb DRAMs (2Mx8) in TSOP packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line Package supports any application where high density and large capacity of storage memory are required, like for example PCs or servers. FEATURES • • • • • • • • 4-Meg Word x 72-Bit (2Bank 8 Byte) organization 168-pin Dual Inline Memory Module All DQ Pins have 10Ω Damping Resister Single 3.3V power supply, ±0.3V tolerance Input :LVTTL compatible Output :LVTTL compatible Refresh : 4,096 cycles/64 ms Programmable data transfer mode • /CAS latency (2, 3) • Burst length (1, 2, 4, 8, Full) • Data scramble(sequential, interleave) CBR auto-refresh, Self-refresh capability Serial Presence Detect (SPD) With EEPROM • • PRODUCT ORGANIZATION Product Name Operation Frequency (Max.) 125MHz Access Time (Max.) tAC2 tAC3 10.0ns 6.0ns MSC23S4721E-8BS18 Note. Specification are subject to change without notice. Page 1/11 MSC23S4721E-8BS18 (98.07.17) BLOCK DIAGRAM CKE1 CKE0 /CS0 DQMB0 DQ0 DQ7 DQMB1 DQ8 DQ15 DQMB4 DQ32 DQ39 DQMB5 DQ40 DQ47 DQMB1 CB0 CB7 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 /CS1 DQM /CS CKE DQ0 /CS2 DQMB2 DQ16 DQ23 DQMB3 DQ24 DQ31 DQMB6 DQ48 DQ55 DQMB7 DQ56 DQ63 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 DQM /CS CKE DQ0 /CS3 DQM /CS CKE DQ0 10KΩ 1 DQ7 DQ7 10 DQ7 6 DQ7 15 2 DQ7 DQ7 11 DQ7 7 DQ7 16 3 DQ7 DQ7 12 DQ7 8 DQ7 17 4 DQ7 DQ7 DQMB5 DQM /CS CKE DQ0 13 DQ7 9 DQ7 Serial PD SCL 18 DQM /CS CKE DQ0 19 A0 A1 A2 SA0 SA1 SA2 47KΩ 5 DQ7 DQ7 14 SDA WP 1 2 CLK0 10 11 CLK1  7 CLK2 15 16 CLK3 3 4 5 12 13 14 8 9 3.3pF 17 18 3.3pF /RAS,/CAS,/WE A0-A11 1 á Vcc 18 Vss 0.1uF 0.33uF Two Decoupling Capacitors per SDRAM Note. The Value of all resistors is 10Ω expect WP and CKE1 MODULE OUTLINE (Front) (Back) 1 85 10 11 94 95 40 41 124 125 84 168 Page 2/11 MSC23S4721E-8BS18 (98.07.17) PIN CONFIGURATION Front side Pin No. Pin name 1 VSS 2 DQ0 3 DQ1 4 DQ2 5 DQ3 6 VCC 7 DQ4 8 DQ5 9 DQ6 10 DQ7 11 DQ8 12 VSS 13 DQ9 14 DQ10 15 DQ11 16 DQ12 17 DQ13 18 VCC 19 DQ14 20 DQ15 21 CB0 22 CB1 23 VSS 24 N.C 25 N.C 26 VCC 27 /WE 28 DQMB0 29 DQMB1 30 /CS0 31 N.C 32 VSS 33 A0 34 A2 35 A4 36 A6 37 A8 38 A10 39 N.C 40 VCC 41 VCC 42 CLK0 Pin Name VCC VSS CLK# /CS# CKE# A0-A10 A11 /RAS /CAS Back side Pin No. Pin name 85 VSS 86 DQ32 87 DQ33 88 DQ34 89 DQ35 90 VCC 91 DQ36 92 DQ37 93 DQ38 94 DQ39 95 DQ40 96 VSS 97 DQ41 98 DQ42 99 DQ43 100 DQ44 101 DQ45 102 VCC 103 DQ46 104 DQ47 105 CB4 106 CB5 107 VSS 108 N.C 109 N.C 110 VCC 111 /CAS 112 DQMB4 113 DQMB5 114 /CS1 115 /RAS 116 VSS 117 A1 118 A3 119 A5 120 A7 121 A9 122 A11(BA0) 123 N.C 124 VCC 125 CLK1 126 N.C Front side Pin No. Pin name 43 VSS 44 N.C 45 /CS2 46 DQMB2 47 DQMB3 48 N.C 49 VCC 50 N.C 51 N.C 52 CB2 53 CB3 54 VSS 55 DQ16 56 DQ17 57 DQ18 58 DQ19 59 VCC 60 DQ20 61 N.C 62 N.C 63 CKE1 64 VSS 65 DQ21 66 DQ22 67 DQ23 68 VSS 69 DQ24 70 DQ25 71 DQ26 72 DQ27 73 VCC 74 DQ28 75 DQ29 76 DQ30 77 DQ31 78 VSS 79 CLK2 80 N.C 81 WP 82 SDA 83 SCL 84 VCC Pin Name /WE DQMB# DQ#, CB# WP SDA SCL SA# N.C Back side Pin No. Pin name 127 VSS 128 CKE0 129 /CS3 130 DQMB6 131 DQMB7 132 N.C 133 VCC 134 N.C 135 N.C 136 CB6 137 CB7 138 VSS 139 DQ48 140 DQ49 141 DQ50 142 DQ51 143 VCC 144 DQ52 145 N.C 146 N.C 147 N.C 148 VSS 149 DQ53 150 DQ54 151 DQ55 152 VSS 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 VCC 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 VSS 163 CLK3 164 N.C 165 SA0 166 SA1 167 SA2 168 VCC Function Power Supply (3.3V) Ground (0V) System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Function Write Enable Data Input/Output Mask Data Input/Output Write Protect Data I/O for SPD CLK input for SPD Socket Position Address for SPD No Connection Page 3/11 MSC23S4721E-8BS18 (98.07.17) SERIAL PRESENCE DETECT Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90 SPD Hex Value 80 08 04 0B 09 02 48 00 01 80 60 02 80 08 08 01 8F 02 06 01 01 00 06 C0 A0 00 00 14 14 14 30 04 20 10 20 10 00-00 12 3F 41,45,20,20,20,20,20,20 01 / 06 Remark Defines the number of bytes written into SPD memory Total number of bytes of SPD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width of this assembly ... Data width continuation Voltage interface level Cycle time (CL=3) Access time from CLK (CL=3) DIMM configuration type Refresh rate / type Primary SDRAM width Error checking SDRAM width Minimum CLK delay Burst lengths supported Number of banks on each SDRAM /CAS latency /CS latency /WE latency SDRAM module attributes SDRAM device attributes : General Cycle time (CL=2) Access time from CLK (CL=2) Cycle time (CL=1) Access time from CLK (CL=1) Minimum ROW precharge time /RAS to /RAS bank delay /RAS to /CAS delay Minimum /RAS pulse width Density of each bank on module 128 byte Notes 256 byte SDRAM 11 rows 9 columns 2 bank 72 bits 0 LVTTL CL=3 tCC=8ns CL=3 tAC3=6ns Non Parity Normal / Self x8 tCCD: 1 CLK 1, 2, 4, 8, F 2 banks 2, 3 0 0 CL=2 tCC2=12ns CL=2 tAC2=10ns Not support Not support tRP=20ns tRRD=20ns tRCD=20ns tRAS=48ns 16MB Command and address signal input setup time 2ns Command and address signal input hold time 1ns Data signal input setup time 2ns Data signal input hold time 1ns R.F.U SPD data revision code 1.2 Checksum for byte 0-62 Manufacturer’s JEDEC ID code Manufacturing location C23S4721E-8BS18 43,32,33,53,34,37,32,31,45, 2D,38,42,53,31,38,20,20,20 20, 20 91, 92 00-00 93-125 64 126 F5 127 FF-FF 128-255 Manufacturer’s part number Revision code R.F.U Intel specification frequency Intel specification /CAS latency Unused storage locations 100MHz CLK0-3, CL=3 Page 4/11 MSC23S4721E-8BS18 (98.07.17) ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Rating Voltage on any pin relative to Vss Vcc supply voltage Storage temperature Power dissipation Short circuit current Operating temperature Symbol VIN, VOUT Vcc, VccQ Tstg PD* Ios Topr Value -0.5 to VCC+0.5 -0.5 to 4.6 - 55 to 125 18 50 0 to 70 Unit V V °C W mA °C *: Ta=25°C Recommended Operating Conditions Parameter Power supply voltage Input high voltage Input low voltage Symbol Vcc, VccQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 (Voltages referenced to Vss = 0V) Max. Unit 3.6 VCC+0.3 0.8 V V V Capacitance Parameter Input capacitance(A0-A11, /RAS, /CAS, /WE) Input capacitance(/CS0, /CS1, /CS2, /CS3) Input capacitance(DQMB0-DQMB7) Input capacitance(CKE0, CKE1) I/O capacitance(DQ0-DQ63, CB0- CB7) Input capacitance(CLK0, CLK1, CLK2, CLK3) (Vcc=3.3V ± 0.3V, Ta=25°C f=1MHz) Symbol Max. Unit CIN1 104 pF CIN2 34 pF CIN3 22 pF CIN4 58 pF CI/O 25 pF CCLK 50 pF Page 5/11 MSC23S4721E-8BS18 (98.07.17) DC CHARACTERISTICS Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Average Power Supply Current (Operating) Symbol Bank ILI ILO VOH VOL One Bank Active Condition CKE (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Module Note Unit Spec. Others IOH = -2mA IOL = 2mA tCC=min. tRC=min No Burst tCC=min. tRC=min tRRD=min No Burst tCC=min. Min -180 -20 2.4 Max 180 20 0.4 uA uA V V ICC1 CKE ≥ VIH - 1125 mA 1, 2 ICC1D Power Supply Current (Stand by) Average Power Supply Current (Clock Suspenson) Average Power Supply Current (Active Stand by) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power down) NOTE: 1. 2. 3. Both Banks Active Both Banks Precharge Both Banks Active One CKE ≥ VIH - 1395 mA 1, 2 ICC2 CKE ≥ VIH tCC=min. CKE ≤ VIL - 720 mA 3 ICC3S - 387 mA 2 ICC3 ICC4 Banks Active Both Banks Active One Bank Active Both Banks Precharge Both Banks Precharge CKE ≥ VIH tCC=min. - 765 mA 3 CKE ≥ VIH tCC=min. tCC=min. tRC=min - 1305 mA 1, 2 ICC5 CKE ≥ VIH - 1080 mA 2 ICC6 CKE ≤ VIL tCC=min. - 36 mA ICC7 CKE ≤ VIL tCC=min. - 36 mA Measured with the output open. The address and data can be changed once or left uncharged during one cycle. The address and data can be changed once or left unchanged during two cycles. Page 6/11 MSC23S4721E-8BS18 (98.07.17) MODE SET ADDRESS KEYS A6 0 0 0 0 1 1 1 1 /CAS Latency A5 A4 CL 0 0 Reserved 0 1 Reserved 1 0 2 1 1 3 0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Note: A7, A8, A9, Burst Type A3 BT 0 Sequential 1 Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 BT=0 0 1 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Full Page BT=1 1 2 4 8 Reserved Reserved Reserved Reserved A10 and A11 should stay "L" during mode set cycle. POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and start the system clock. 2. After the VCC voltage has reached the specified level, pause for 200us or more with the input kept in NOP state. 3. Issue the precharge all bank command. 4. Apply a CBR auto-refresh eight or more times. 5. Enter the mode register setting command. Page 7/11 MSC23S4721E-8BS18 (98.07.17) AC CHARACTERISTIC Parameter Clock Cycle Time Access Time from Clock Clock "H" Pulse Time Clock "L" Pulse Time Input Setup Time(CLK, ADD, DIN) Input Hold Time(CLK, ADD, DIN) Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock /RAS Cycle Time /RAS Precharge Time /RAS Active Time /RAS to /CAS Delay Time Write Recovery Time Write Command Input Time from Output /RAS to /RAS Bank Active Delay Time Refresh Time Power-down Exit Set-up Time Input Level Transition Time /CAS to /CAS Delay Time (Min) Clock Disable Time from CKE Data Output High Impedance Time from DQM Data Input Mask Time from DQMB Data Input Time from Write Command Data Output High Inpedance Time Active Command Input Time from MODE NOTES: 1) 2) 3) 4) 5) CL=3 CL=2 CL=3 CL=2 Symbol tCC tAC tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tOWD tRRD tREF tPDE tT ICCD ICKE IDOZ IDOD IDWD IROH IMRD (VCC = 3.3 ± 0.3V, Ta = 0 ~70°C) NOTE 1, 2 Module Spec. Unit Note Min. 8 12 3 3 2 1 3 3 70 20 48 20 8 20 20 10 1 1 2 0 0 CL 3 Max. 6 10 9 100,000 64 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle . 3, 4 3, 4 AC measurements assume that tT=1ns. The reference level for timing of input signals is 1.4V. This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF (RLoad is 50ohm). An access time is measured at 1.4V. If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL. 1.4v 50Ω OUTPUT OUTPUT LOAD 50pF Page 8/11 MSC23S4721E-8BS18 (98.07.17) FUNCTION TRUTH TABLE (Table1)(1/2) Current State Idle /CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L /RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L /CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L /WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X BA BA BA BA BA X X X BA BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X Action NOP NOP 2 ILLEGAL 2 ILLEGAL Row Active 4 NOP 5 Auto-Refresh or Self-Refresh Mode Register write NOP NOP Read Write 2 ILLEGAL Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Reserved Term Burst, start new Burst Read Term Burst, start new Burst Write 2 ILLEGAL Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) 2 ILLEGAL Term Burst, start new Burst Read Term Burst, start new Burst Write 2 ILLEGAL Term Burst, execute Row Precharge ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) Row Active Read Write Read with Auto Precharge ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) 2 Write with Auto Precharge ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL ILLEGAL 2 Page 9/11 MSC23S4721E-8BS18 (98.07.17) FUNCTION TRUTH TABLE (Table1)(2/2) Current State Precharge /CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L /RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L /CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X /WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X Action NOP Idle after tRP NOP Idle after tRP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 4 NOP ILLEGAL NOP NOP 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Row Active after tRCD NOP Row Active after tRCD 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL NOP Idle after tRC NOP Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Æ Æ Write Recovery Row Active Refresh Æ Æ Mode Resister Access ABBREVIATIONS RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No Operation command Notes: 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. Page 10/11 MSC23S4721E-8BS18 (98.07.17) FUNCTION TRUTH TABLE (CKE) (Table2) Current State (n) Self Refresh CKEn-1 H L L L L L L H L L L L L L H H H H H H H H L H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X H L L L L L L X X X X X /RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X /CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X /WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self Refresh ABI Exit Self Refresh ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down ABI Exit Power Down ABI ILLEGAL ILLEGAL 6 ILLEGAL NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension Æ Æ Power Down Æ Æ All Banks idle (ABI) 6 Any State Other than Listed Above Notes: 6. Power-down and self refresh can be entered only when all the banks are in an idle state. Page 11/11