MSM511000CL-70ZS

E2G0009-17-41 ¡ Semiconductor MSM511000C/CL ¡ Semiconductor This version: Jan. 1998 MSM511000C/CL Previous version: May 1997 1,048,576-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM511000C/CL is a 1,048,576-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM511000C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM511000C/CL is available in a 26/20-pin plastic SOJ or 20-pin plastic ZIP. The MSM511000CL (the low-power version) is specially designed for lowerpower applications. FEATURES • 1,048,576-word ¥ 1-bit configuration • Single 5 V power supply, ± 10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM511000C/CL-xxJS) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM511000C/CL-xxZS) xx indicates speed rank. PRODUCT FAMILY Family MSM511000C/CL-45 MSM511000C/CL-50 MSM511000C/CL-60 MSM511000C/CL-70 Access Time (Max.) tRAC 45 ns 50 ns 60 ns 70 ns tAA 24 ns 26 ns 30 ns 35 ns tCAC 14 ns 14 ns 15 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 100 ns 120 ns 130 ns 468 mW 440 mW 385 mW 330 mW 5.5 mW/ 1.1 mW (L-version) 1/15 ¡ Semiconductor PIN CONFIGURATION (TOP VIEW) DIN 1 WE 2 RAS 3 NC 4 NC 5 A0 9 A1 10 A2 11 A3 12 VCC 13 , 26 VSS 25 DOUT 24 CAS 23 NC 22 A9 18 A8 17 A7 16 A6 15 A5 14 A4 Pin Name A0 - A9 RAS CAS DIN DOUT WE VCC VSS NC MSM511000C/CL A9 1 DOUT 3 DIN 5 RAS 7 NC 9 A0 11 A2 13 VCC 15 A5 17 A7 19 2 CAS 4 VSS 6 WE 8 NC NO LEAD 12 A1 14 A3 16 A4 18 A6 20 A8 26/20-Pin Plastic SOJ 20-Pin Plastic ZIP Function Address Input Row Address Strobe Column Address Strobe Data Input Data Output Write Enable Power Supply (5 V) Ground (0 V) No Connection 2/15 ¡ Semiconductor MSM511000C/CL BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 10 Column Address Buffers 10 Column Decoders Write Clock Generator WE A0 - A9 Internal Address Counter Refresh Control Clock Sense Amplifiers I/O Selector Output Buffer DOUT 10 Row Address Buffers 10 Row Decoders Word Drivers Memory Cells Input Buffer DIN VCC On Chip VBB Generator VSS 3/15 ¡ Semiconductor MSM511000C/CL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating –1.0 to 7.0 50 1 0 to 70 –55 to 150 Unit V mA W °C °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 –1.0 Typ. 5.0 0 — — Max. 5.5 0 6.5 0.8 (Ta = 0°C to 70°C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A9, DIN) Input Capacitance (RAS, CAS, WE) Output Capacitance (DOUT) Symbol CIN1 CIN2 COUT Typ. — — — (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Max. 5 5 6 Unit pF pF pF 4/15 ¡ Semiconductor DC Characteristics MSM511000C/CL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Parameter Output High Voltage Output Low Voltage Input Leakage Current Condition IOH = –5.0 mA IOL = 4.2 mA 0 V £ VI £ 6.5 V; All other pins not under test = 0 V DOUT disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH MSM511000 MSM511000 MSM511000 MSM511000 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. VOH VOL ILI 2.4 0 –10 VCC 0.4 10 2.4 0 –10 VCC 0.4 10 2.4 0 –10 VCC 0.4 10 2.4 0 –10 VCC 0.4 10 V V mA Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) ILO –10 10 –10 10 –10 10 –10 10 mA ICC1 — — — — — 85 2 1 200 85 — — — — — 80 2 1 200 80 — — — — — 70 2 1 200 70 — — — — — 60 2 1 200 60 mA 1, 2 ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, mA mA mA 1 1, 5 1, 2 ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DOUT = enable — 5 — 5 — 5 — 5 mA 1 ICC6 RAS cycling, CAS before RAS RAS = VIL, — 85 — 80 — 70 — 60 mA 1, 2 ICC7 CAS cycling, tPC = Min. tRC = 125 ms, — 80 — 75 — 65 — 55 mA 1, 3 ICC10 CAS before RAS, tRAS £ 1 ms — 300 — 300 — 300 — 300 mA 1, 4, 5 Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version. 5/15 ¡ Semiconductor AC Characteristics (1/2) MSM511000C/CL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Output Low Impedance Time from CAS Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Symbol MSM511000 MSM511000 MSM511000 MSM511000 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tCLZ tT tREF tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL 90 110 34 54 — — — — 0 0 3 — — 35 — — — — 45 14 24 28 — 14 50 8 64 — 100 120 36 56 — — — — 0 0 3 — — 40 — — — — 50 14 26 30 — 14 50 8 64 — 120 140 40 60 — — — — 0 0 3 — — 50 — — — — 60 15 30 35 — 15 50 8 64 — 130 155 45 70 — — — — 0 0 3 — — 50 — — — — 70 20 35 40 — 20 50 8 64 — ns ns ns ns ns ns ns ns ns ns ns ms ms ns 4, 5, 6 4, 5 4, 6 4 4 7 3 CAS to Data Output Buffer Turn-off Delay Time tOFF 45 10,000 50 10,000 60 10,000 70 10,000 ns 45 100,000 50 100,000 60 100,000 70 100,000 ns 14 10 45 5 28 17 12 0 7 0 12 35 24 — — — — — 31 21 — — — — — — 14 10 50 5 30 18 13 0 8 0 13 40 26 — — — — — 36 24 — — — — — — 15 10 60 5 35 20 15 0 10 0 15 50 30 — — — — — 45 30 — — — — — — 20 10 70 5 40 20 15 0 10 0 15 55 35 — — — — — 50 35 — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 14 10,000 14 10,000 15 10,000 20 10,000 ns 6/15 ¡ Semiconductor AC Characteristics (2/2) MSM511000C/CL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Read Command Set-up Time Read Command Hold Time Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time Symbol MSM511000 MSM511000 MSM511000 MSM511000 C/CL-45 C/CL-50 C/CL-60 C/CL-70 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. tRCS tRCH tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tCWD tAWD tRWD tCPWD 0 0 0 0 10 35 10 14 14 0 12 35 14 24 45 33 0 10 25 — — — — — — — — — — — — — — — — — — — 0 0 0 0 10 40 10 14 14 0 13 40 14 26 50 35 0 10 25 — — — — — — — — — — — — — — — — — — — 0 0 0 0 10 50 10 15 15 0 15 50 15 30 60 40 0 10 30 — — — — — — — — — — — — — — — — — — — 0 0 0 0 15 55 15 20 20 0 15 55 20 35 70 45 0 10 30 — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9 Read Command Hold Time referenced to RAS tRRH CAS Active Delay Time from RAS Precharge tRPC RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) tCHR 7/15 ¡ Semiconductor Notes: MSM511000C/CL 1. A start-up delay of 100 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in a read modify write cycle. 8/15 E2G0088-17-41A ¡ Semiconductor MSM511000C/CL TIMING WAVEFORM Read Cycle tRC VIH – RAS V IL – tCRP CAS VIH – VIL – tRCD tRAS tCSH tRSH tCAS tRP tCRP Address Address VIH – VIL –   ,,   

 ,  ,,  ,

  tRAD tASR tRAH tASC tRAL tCAH VIH – VIL – Row Column tAR tRCS tRRH tRCH WE VIH – VIL – tCAC tAA tRAC tCLZ tOFF DOUT VOH – VOL – Open Valid Data "H" or "L" Write Cycle (Early Write) tRC VIH – RAS V – IL tRAS tRP tCRP tRCD tRSH tCSH tCRP CAS VIH – VIL – tCAS tAR tRAD tASR tRAH tASC tRAL tCAH Row Column tWCR tCWL tWCS tWCH VIH – WE VIL – tWP tDHR tRWL tDS tDH DIN VIH – VIL – Valid Data DOUT VOH – VOL – Open "H" or "L" 9/15 ¡ Semiconductor Read Modify Write Cycle tRWC VIH – RAS VIL – tCRP CAS VIH – VIL – tRCD tCAS tAR tCSH tRAS tRSH MSM511000C/CL tRP tRWL tCRP Fast Page Mode Read Cycle Address  ,  

,  
 ,,     ,         tASR tRAD tRAH tASC tRAL tCAH tCWL Address VIH – VIL – Row Column tAWD tRWD tCWD tWP VIH – WE VIL – tRCS tDS tDH DIN VIH – VIL – Valid Data tCAC tAA tRAC tOFF DOUT VOH – VOL – Open Valid Data tCLZ "H" or "L" tRASP tRP VIH – RAS VIL – VIH – VIL – tRHCP tCRP tCSH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tCRP CAS tASR tRAH tAR tASC tCAH tASC tCAH tASC tRAL tCAH VIH – VIL – Row Column Column Column tRAD tRCH tRCS tRCS tRCH tRRH tRCS tRCH WE VIH – VIL – tCAC tCAC tCAC tAA tAA tAA tRAC tCPA tCPA DOUT VOH – VOL – Valid Data tCLZ tOFF tCLZ Valid Data tOFF tCLZ Valid Data tOFF "H" or "L" 10/15 ¡ Semiconductor Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH – VIL – tCRP CAS VIH – VIL – tASR tRAH tRCD tCAS tCP MSM511000C/CL tRP tRHCP tPC tCAS tCP tRSH tCAS tCRP Fast Page Mode Read Modify Write Cycle Address VIH – VIL –      , 
,,, 


 tCAH tASC tCAH tASC Address VIH – VIL – Row Column Column Column tRAD tWCR tRWL VIH – WE VIL – tWCS tCWL tWP tWCH tWCS tCWL tWCH tWP tDH tWCS tCWL tWCH tWP tDH tDS tDH tDS tDS DIN VIH – VIL – Valid Data Valid Data Valid Data tDHR DOUT VOH – VOL – Open "H" or "L" tRASP RAS VIH – VIL – tRHCP tRCD tCSH V CAS IH – VIL – tCAS tCP tPRWC tCAS tRSH tRP tCP tCRP tCAS tASR tAR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL Row Column Column Column tAR tASC tRAL tCAH tRCS tRWD tCWD tAWD tAA tCAC tCWL tRCS tCPWD tCWD tCWL tRCS tCPWD tCWD tAWD tCPA tAA tCAC tCWL WE VIH – VIL – tWP tRAD tOFF tAWD tCPA tAA tCAC tWP tWP tOFF tOFF DOUT VOH – VOL – VIH – VIL – tRAC tCLZ Valid Data Valid Data tDS Valid Data tDH tCLZ tDS Valid Data tDH tCLZ Valid Data tRWL tDH tDS Valid Data DIN "H" or "L" 11/15 ¡ Semiconductor RAS-Only Refresh Cycle Address CAS before RAS Refresh Cycle ,    MSM511000C/CL tRC tRP VIH – RAS VIL – tRAS tCRP tRPC CAS VIH – VIL – tASR tRAH VIH – VIL – Row tOFF DOUT VOH – VOL – Open Note: WE = "H" or "L" "H" or "L" tRC tRAS tRP RAS VIH – VIL – tRPC tCP tCSR tCHR V CAS IH – VIL – tOFF DOUT VOH – VOL – Open Note: WE, Address = "H" or "L" 12/15 ¡ Semiconductor Hidden Refresh Read Cycle tRC tRAS VIH – RAS VIL – tCRP CAS VIH – VIL – tRCD tRSH tCHR tRP tRAS MSM511000C/CL Address Hidden Refresh Write Cycle Address     ,    
,,,    

tRAD tRAL tASR tRAH tASC tCAH VIH – VIL – Row Column tAR tRCS tRRH WE VIH – VIL – tCAC tAA tRAC tOFF DOUT VOH – VOL – Valid Data tCLZ "H" or "L" tRC tRAS tRP tRAS VIH – RAS VIL – tCRP tRCD tRSH tCHR CAS VIH – VIL – tAR tRAD tASR tRAH tASC tRAL tCAH VIH – VIL – Row Column tRAD tWCR tWCS tRWL tWCH WE VIH – VIL – tWP tDS tDH DIN VIH – VIL – VOH – VOL – Valid Data tDHR DOUT Open "H" or "L" 13/15 ¡ Semiconductor MSM511000C/CL PACKAGE DIMENSIONS (Unit : mm) SOJ26/20-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/15 ¡ Semiconductor MSM511000C/CL (Unit : mm) ZIP20-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP. 15/15