MSM514100DL

E2G0022-17-41 ¡ Semiconductor MSM514100D/DL ¡ Semiconductor This version: Jan. 1998 MSM514100D/DL Previous version: May 1997 4,194,304-Word ¥ 1-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM514100D/DL is a 4,194,304-word ¥ 1-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514100D/DL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514100D/DL is available in a 26/20-pin plastic SOJ, 20pin plastic ZIP, or 26/20-pin plastic TSOP. The MSM514100DL (the low-power version) is specially designed for lower-power applications. FEATURES • 4,194,304-word ¥ 1-bit configuration • Single 5 V power supply, ± 10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Package options: 26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM514100D/DL-xxSJ) 20-pin 400 mil plastic ZIP (ZIP20-P-400-1.27) (Product : MSM514100D/DL-xxZS) 26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM514100D/DL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM514100D/DL-50 MSM514100D/DL-60 MSM514100D/DL-70 Access Time (Max.) tRAC 50 ns 60 ns 70 ns tAA 25 ns 30 ns 35 ns tCAC 13 ns 15 ns 20 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 110 ns 130 ns 550 mW 495 mW 440 mW 5.5 mW/ 1.1 mW (L-version) 1/17 ¡ Semiconductor MSM514100D/DL  DIN 1 WE 2 RAS 3 NC 4 A10 5 A0 9 A1 10 A2 11 A3 12 VCC 13 PIN CONFIGURATION (TOP VIEW) 26 VSS 25 DOUT 24 CAS 23 NC 22 A9 18 A8 17 A7 16 A6 15 A5 14 A4 A9 1 DOUT 3 DIN 5 RAS 7 NC 9 A0 11 A2 13 VCC 15 A5 17 A7 19 2 CAS 4 VSS 6 WE 8 A10 10 NC 12 A1 14 A3 16 A4 18 A6 20 A8 DIN 1 WE 2 RAS 3 NC 4 A10 5 A0 9 A1 10 A2 11 A3 12 VCC 13 26/20-Pin Plastic SOJ 20-Pin Plastic ZIP  26/20-Pin Plastic TSOP (K Type) 26 VSS 25 DOUT 24 CAS 23 NC 22 A9 18 A8 17 A7 16 A6 15 A5 14 A4 Pin Name A0 - A10 RAS CAS DIN DOUT WE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input Data Output Write Enable Power Supply (5 V) Ground (0 V) No Connection 2/17 ¡ Semiconductor MSM514100D/DL BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 11 Column Address Buffers 11 Column Decoders Write Clock Generator WE A0 - A10 Internal Address Counter Refresh Control Clock Sense Amplifiers I/O Selector Output Buffer DOUT 11 Row Address Buffers 11 Row Decoders Word Drivers Memory Cells Input Buffer DIN VCC On Chip VBB Generator VSS 3/17 ¡ Semiconductor MSM514100D/DL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating –1.0 to 7.0 50 1 0 to 70 –55 to 150 Unit V mA W °C °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 –1.0 Typ. 5.0 0 — — Max. 5.5 0 6.5 0.8 (Ta = 0°C to 70°C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A10, DIN) Input Capacitance (RAS, CAS, WE) Output Capacitance (DOUT) Symbol CIN1 CIN2 COUT Typ. — — — (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Max. 6 7 7 Unit pF pF pF 4/17 ¡ Semiconductor DC Characteristics MSM514100D/DL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Condition MSM514100 MSM514100 MSM514100 D/DL-50 D/DL-60 D/DL-70 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 –10 Max. VCC 0.4 10 Min. 2.4 0 –10 Max. VCC 0.4 10 V V mA 2.4 0 –10 Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol VOH IOH = –5.0 mA VOL IOL = 4.2 mA 0 V £ VI £ 6.5 V; ILI All other pins not under test = 0 V DOUT disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DOUT = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS £ 1 ms Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) ILO –10 10 –10 10 –10 10 mA ICC1 — — — — — 100 2 1 200 100 — — — — — 90 2 1 200 90 — — — — — 80 2 1 200 80 mA 1, 2 mA mA 1 1, 5 mA 1, 2 — 5 — 5 — 5 mA 1 — 100 — 90 — 80 mA 1, 2 — 80 — 70 — 60 mA 1, 3 — 300 — 300 — 300 mA 1, 4, 5 Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version. 5/17 ¡ Semiconductor AC Characteristics (1/2) MSM514100D/DL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time MSM514100 MSM514100 MSM514100 D/DL-50 D/DL-70 D/DL-60 Unit Note Symbol Min. tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tCLZ tOFF tT tREF tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL 90 108 35 53 — — — — 0 0 3 — — 30 50 50 13 10 13 50 5 30 20 15 0 10 0 10 45 25 Max. — — — — 50 13 25 30 — 13 50 16 128 — 10,000 100,000 Min. 110 130 40 60 — — — — 0 0 3 — — 40 60 60 15 10 15 60 5 35 20 15 0 10 0 15 50 30 Max. — — — — 60 15 30 35 — 15 50 16 128 — 10,000 100,000 Min. 130 155 45 70 — — — — 0 0 3 — — 50 70 70 20 10 20 70 5 40 20 15 0 10 0 15 55 35 Max. — — — — 70 20 35 40 — 20 50 16 128 — 10,000 100,000 ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4, 5, 6 4, 5 4, 6 4 4 7 3 — — 10,000 — — — 37 25 — — — — — — — — 10,000 — — — 45 30 — — — — — — — — 10,000 — — — 50 35 — — — — — — 6/17 ¡ Semiconductor AC Characteristics (2/2) MSM514100D/DL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) Symbol MSM514100 MSM514100 MSM514100 D/DL-50 D/DL-70 D/DL-60 Unit Note Min. Max. — — — — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 10 45 10 15 15 0 15 50 15 30 60 35 10 5 10 10 10 10 10 Max. — — — — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 10 50 10 20 20 0 15 55 20 35 70 40 10 5 10 10 10 10 10 Max. — — — — — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9 0 0 0 0 10 40 10 13 13 0 10 45 13 25 50 30 10 5 10 10 10 10 10 tRCS tRCH tRRH tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tCWD tAWD tRWD tCPWD tRPC tCSR tCHR WE to RAS Precharge Time (CAS before RAS) tWRP WE Hold Time from RAS (CAS before RAS) tWRH RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tWTS tWTH 7/17 ¡ Semiconductor Notes: MSM514100D/DL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. RA10, CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data output pin will indicate a high level. If any internal bits are not equal, the data output pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/17 E2G0090-17-41C ¡ Semiconductor MSM514100D/DL TIMING WAVEFORM Read Cycle tRC VIH – RAS V IL – tCRP CAS VIH – VIL – tRCD tRAS tCSH tRSH tCAS tRP tCRP Address Write Cycle (Early Write) Address   ,,     ,,

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  tRAD tASR tRAH tASC tRAL tCAH VIH – VIL – Row Column tAR tRCS tRRH tRCH WE VIH – VIL – tCAC tAA tRAC tCLZ tOFF DOUT VOH – VOL – Open Valid Data "H" or "L" tRC VIH – RAS VIL – tRAS tRP tCRP tRCD tRSH tCSH tCRP CAS VIH – VIL – tCAS tAR tRAD tASR tRAH tASC tRAL tCAH VIH – VIL – Row Column tWCR tCWL tWCS tWCH VIH – WE VIL – tWP tDHR tRWL tDS tDH DIN VIH – VIL – Valid Data DOUT VOH – VOL – Open "H" or "L" 9/17 ¡ Semiconductor Read Modify Write Cycle tRWC VIH – RAS VIL – tCRP CAS VIH – VIL – tRCD tCAS tAR tCSH tRAS tRSH MSM514100D/DL tRP tRWL tCRP V Address IH – VIL – Fast Page Mode Read Cycle VIH – VIL – Address  ,  

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 ,,     ,         tASR tRAD tRAH tASC tRAL tCAH tCWL Row Column tAWD tRWD tCWD tWP VIH – WE VIL – tRCS tDS tDH DIN VIH – VIL – Valid Data tCAC tAA tRAC tOFF DOUT VOH – VOL – Open Valid Data tCLZ "H" or "L" tRASP tRP RAS tRHCP tCRP tCSH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tCRP V CAS IH – VIL – tASR tRAH tAR tASC tCAH tASC tCAH tASC tRAL tCAH VIH – VIL – Row Column Column Column tRAD tRCH tRCS tRCS tRCH tRRH tRCS tRCH VIH – WE VIL – tCAC tCAC tCAC tAA tRAC tAA tCPA tAA tCPA DOUT VOH – VOL – Valid Data tCLZ tOFF tCLZ Valid Data tOFF tCLZ Valid Data tOFF "H" or "L" 10/17 ¡ Semiconductor Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH – VIL – tCRP CAS VIH – VIL – tASR tRAH tRCD tCAS tCP MSM514100D/DL tRP tRHCP tPC tCAS tCP tRSH tCAS tCRP Address VIH – VIL – Fast Page Mode Read Modify Write Cycle VIH – VIL – Address VIH – VIL –  ,      , ,

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tCAH tASC tCAH tASC Row Column Column Column tRAD tWCR tRWL VIH – WE VIL – tWCS tCWL tWP tWCH tWCS tCWL tWCH tWP tDH tWCS tCWL tWCH tWP tDH tDS tDH tDS tDS DIN VIH – VIL – VOH – VOL – Valid Data Valid Data Valid Data tDHR DOUT Open "H" or "L" tRASP RAS tRHCP tRCD tCSH CAS VIH – VIL – tCAS tCP tPRWC tCAS tRSH tRP tCP tCRP tCAS tASR tAR tRAH tASC tCAH tASC tCAH tASC tCAH tRAL Row Column Column Column tAR tASC tRAL tCAH tRCS tRWD tCWD tAWD tAA tCAC tCWL tRCS tCPWD tCWD tCWL tRCS tCPWD tCWD tAWD tCPA tAA tCAC tCWL WE VIH – VIL – tWP tRAD tOFF tAWD tCPA tAA tCAC tWP tWP tOFF tOFF DOUT VOH – VOL – VIH – VIL – tRAC tCLZ Valid Data Valid Data tDS Valid Data tDH tCLZ tDS Valid Data tDH tCLZ Valid Data tRWL tDH tDS Valid Data DIN "H" or "L" 11/17 ,     

,,     ¡ Semiconductor MSM514100D/DL RAS-Only Refresh Cycle tRC tRAS tRP RAS VIH – VIL – tRPC tCRP CAS VIH – VIL – tASR tRAH Address VIH – VIL – Row tOFF DOUT VOH – VOL – Open Note: WE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRAS tRP RAS VIH – VIL – tRPC tRPC tCP tCSR tCHR CAS VIH – VIL – tWRP tWRH tWRP WE VIH – VIL – tOFF DOUT VOH – VOL – Open Note: Address = "H" or "L" "H" or "L" 12/17 ¡ Semiconductor Hidden Refresh Read Cycle RAS CAS Address WE DOUT Hidden Refresh Write Cycle RAS CAS Address WE DIN DOUT 
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,, MSM514100D/DL tRC tRAS tRP tRAS VIH – VIL – VIH – VIL – tCRP tRCD tRSH tCHR tRAD tASR tRAH tASC tRAL tCAH VIH – VIL – Row Column tRCS tAR tRRH tWRP tWRH VIH – VIL – VOH – VOL – tCAC tRAC tAA tOFF Valid Data tCLZ "H" or "L" tRC tRAS tRP tRAS VIH – VIL – tCRP tRCD tRSH tCHR VIH – VIL – tRAD tAR tASR tRAH tASC tRAL tCAH VIH – VIL – Row Column tWCR tWCS VIH – VIL – VIH – VIL – VOH – VOL – tRWL tWCH tWP tWRP tWRH tDS tDH Valid Data tDHR Open "H" or "L" 13/17 ¡ Semiconductor Test Mode Initiate Cycle RAS CAS WE DOUT ,

   MSM514100D/DL tRC tRP tRAS VIH – VIL – tRPC tCP tCSR tCHR VIH – VIL – tWTS tWTH VIH – VIL – tOFF VOH – VOL – Open Note: Address, DIN = "H" or "L" "H" or "L" 14/17 ¡ Semiconductor MSM514100D/DL PACKAGE DIMENSIONS (Unit : mm) SOJ26/20-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/17 ¡ Semiconductor MSM514100D/DL (Unit : mm) ZIP20-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.50 TYP. 16/17 ¡ Semiconductor MSM514100D/DL (Unit : mm) TSOPII26/20-P-300-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.38 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17