0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
MSM514265CSL

MSM514265CSL

  • 厂商:

    OKI

  • 封装:

  • 描述:

    MSM514265CSL - 262,144-Word x 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO - OKI electronic com...

  • 数据手册
  • 价格&库存
MSM514265CSL 数据手册
E2G0027-17-41 ¡ Semiconductor ¡ Semiconductor MSM514265C/CSL DESCRIPTION This MSM514265C/CSL version: Jan. 1998 Previous version: May 1997 262,144-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO The MSM514265C/CSL is a 262,144-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514265C/CSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514265C/CSL is available in a 40-pin plastic SOJ or 44/ 40-pin plastic TSOP. The MSM514265CSL (the self-refresh version) is specially designed for lowerpower applications. FEATURES • 262,144-word ¥ 16-bit configuration • Single 5 V power supply, ± 10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 512 cycles/8 ms, 512 cycles/128 ms (SL version) • Fast page mode with EDO, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM514265C/CSL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM514265C/CSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM514265C/CSL-50 MSM514265C/CSL-60 MSM514265C/CSL-70 Access Time (Max.) tRAC tAA tCAC tOEA 50 ns 25 ns 15 ns 15 ns 60 ns 30 ns 15 ns 15 ns 70 ns 35 ns 20 ns 20 ns Power Dissipation Cycle Time (Min.) Operating (Max.) Standby (Max.) 90 ns 110 ns 130 ns 935 mW 825 mW 770 mW 5.5 mW/ 1.1 mW (SL version) 1/17   ¡ Semiconductor MSM514265C/CSL PIN CONFIGURATION (TOP VIEW) VCC 1 40 VSS DQ1 2 DQ2 3 DQ3 4 DQ4 5 VCC 6 DQ5 7 DQ6 8 DQ7 9 39 DQ16 38 DQ15 37 DQ14 36 DQ13 35 VSS 34 DQ12 33 DQ11 32 DQ10 31 DQ9 VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS DQ8 10 NC 11 NC 12 WE 13 NC 15 A0 16 A1 17 A2 18 A3 19 RAS 14 NC NC 30 NC WE 29 LCAS RAS 28 UCAS NC 27 OE A0 26 A8 A1 A2 25 A7 A3 24 A6 VCC 23 A5 22 A4 21 VSS 13 14 15 16 17 18 19 20 21 22 VCC 20 44/40-Pin Plastic TSOP (K Type) 40-Pin Plastic SOJ Pin Name A0 - A8 RAS LCAS UCAS DQ1 - DQ16 OE WE VCC VSS NC Function Address Input Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data Input / Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17 ¡ Semiconductor MSM514265C/CSL BLOCK DIAGRAM RAS LCAS UCAS Column Address Buffers Internal Address Counter Row Address 9 Buffers Timing Generator WE I/O Controller I/O Controller OE 8 Output Buffers 8 DQ1 - DQ8 8 9 9 Column Decoders Input Buffers 8 A0 - A8 Refresh Control Clock Sense Amplifiers 16 I/O Selector 16 8 9 Input Buffers 8 Row Decoders Word Drivers Memory Cells 8 DQ9 - DQ16 Output Buffers 8 VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin RAS H L L L L L L L L LCAS UCAS WE OE DQ Pin DQ1 - DQ8 High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ9 - DQ16 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write — * H L H L L H L L * H H L L H L L L * * H H H L L L H * * L L L H H H H *: "H" or "L" 3/17 ¡ Semiconductor MSM514265C/CSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating –1.0 to 7.0 50 1 0 to 70 –55 to 150 Unit V mA W °C °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 –1.0 Typ. 5.0 0 — — Max. 5.5 0 6.5 0.8 (Ta = 0°C to 70°C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A8) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ1 - DQ16) Symbol CIN1 CIN2 CI/O Typ. — — — (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Max. 7 7 10 Unit pF pF pF 4/17 ¡ Semiconductor DC Characteristics MSM514265C/CSL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol Condition MSM514265 MSM514265 MSM514265 C/CSL-50 C/CSL-60 C/CSL-70 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 –10 Max. VCC 0.4 10 Min. 2.4 0 –10 Max. VCC 0.4 10 V V mA 2.4 0 –10 VOH IOH = –2.0 mA VOL IOL = 2.0 mA 0 V £ VI £ 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS £ 1 ms RAS £ 0.2 V, CAS £ 0.2 V Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh) ILO –10 10 –10 10 –10 10 mA ICC1 — — — — — 170 2 1 200 170 — — — — — 150 2 1 200 150 — — — — — 140 2 1 200 140 mA 1, 2 mA mA 1 1, 5 mA 1, 2 — 5 — 5 — 5 mA 1 — 170 — 150 — 140 mA 1, 2 — 170 — 150 — 140 mA 1, 3 — 300 — 300 — 300 mA 1, 4, 5 ICCS — 200 — 200 — 200 mA 1, 5 Notes: 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. SL version. 5/17 ¡ Semiconductor AC Characteristics (1/2) MSM514265C/CSL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low Symbol MSM514265 MSM514265 MSM514265 C/CSL-60 C/CSL-70 Unit Note C/CSL-50 Min. Max. — — — — 50 15 25 30 15 — — 15 15 15 15 50 8 128 — 10,000 100,000 — — — 10,000 — — — — 35 25 — — — — — — — Min. 110 150 25 80 — — — — — 0 5 0 0 0 0 1 — — 40 60 60 15 15 10 10 60 10 35 5 20 15 60 0 10 0 10 50 30 Max. — — — — 60 15 30 35 15 — — 15 15 15 15 50 8 128 — 10,000 100,000 — — — 10,000 — — — — 45 30 — — — — — — — Min. 130 180 30 95 — — — — — 0 5 0 0 0 0 1 — — 50 70 70 20 20 10 10 70 10 40 10 20 15 70 0 10 0 15 55 35 Max. — — — — 70 20 35 40 20 — — 20 20 20 20 50 8 128 — 10,000 — — — 10,000 — — — — 50 35 — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 12 5 6 13 13 15 7, 8 7, 8 7 7 3 16 4, 5, 6 4, 5 4, 6 4, 13 4 4 90 130 20 75 — — — — — 0 5 0 0 0 0 1 — — 30 50 50 15 10 7 7 50 10 30 5 18 13 50 0 8 0 10 40 25 tRC tRWC tHPC tHPRWC tRAC tCAC tAA tCPA tOEA tCLZ tDOH CAS to Data Output Buffer Turn-off Delay Time tCEZ RAS to Data Output Buffer Turn-off Delay Time tREZ OE to Data Output Buffer Turn-off Delay Time tOEZ WE to Data Output Buffer Turn-off Delay Time tWEZ Transition Time Refresh Period Refresh Period (SL version) RAS Precharge Time RAS Pulse Width RAS Hold Time RAS Hold Time referenced to OE CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time RAS to Second CAS Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time tT tREF tREF tRP tRAS tRSH tROH tCAS tCSH tCRP tRHCP tCHO tRCD tRAD tRSCD tASR tRAH tASC tCAH tAR tRAL RAS Pulse Width (Fast Page Mode with EDO) tRASP 100,000 ns CAS Precharge Time (Fast Page Mode with EDO) tCP 6/17 ¡ Semiconductor AC Characteristics (2/2) MSM514265C/CSL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge Symbol MSM514265 MSM514265 MSM514265 C/CSL-60 C/CSL-70 Unit Note C/CSL-50 Min. Max. — — — — — — — — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 15 45 15 7 15 10 10 15 15 0 10 50 15 35 50 80 55 10 10 15 100 110 –40 Max. — — — — — — — — — — — — — — — — — — — — — — — — — — — Min. 0 0 0 0 15 50 15 7 20 10 10 20 20 0 15 55 20 45 60 95 65 10 10 15 100 130 –50 Max. — — — — — — — — — — — — — — — — — — — — — — — — — — — ns ns ns 12 9, 12 9 0 0 0 0 10 40 10 5 15 7 7 15 15 0 10 40 15 35 45 70 50 10 10 15 100 90 –30 tRCS tRCH tRRH tWCS tWCH tWCR tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC ns 10, 12 12 ns ns ns ns ns ns ns ns ns 14 ns 11, 12 ns 11, 12 ns ns ns 10 ns 10 ns 10 ns ns ns ns ms ns ns 10 12 12 13 16 16 16 RAS to CAS Set-up Time (CAS before RAS) tCSR RAS to CAS Hold Time (CAS before RAS) tCHR RAS Pulse Width tRASS (CAS before RAS Self-Refresh) RAS Precharge Time tRPS (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) tCHS 7/17 ¡ Semiconductor Notes: MSM514265C/CSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. The output timing reference levels are VOH = 2.0 V (IOH = –2 mA) and VOL = 0.8 V (IOL = 2 mA). 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the UCAS and LCAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. These parameters are determined by the falling edge of either UCAS or LCAS, whichever is earlier. 13. These parameters are determined by the rising edge of either UCAS or LCAS, whichever is later. 14. tCWL should be satisfied by both UCAS and LCAS. 15. tCP is determined by the time both UCAS and LCAS are high. 16. Only SL version. 8/17 E2G0097-17-41J ¡ Semiconductor MSM514265C/CSL  ,,,      ,     ,,   ,    ,,,, TIMING WAVEFORM Read Cycle tRC tRAS tRP VIH – RAS VIL – tAR tCRP tCSH tCRP tRCD VIH – CAS VIL – VIH – VIL – VIH – VIL – VIH – VIL – VOH – tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address Row Column tRCS tRRH tRCH WE tAA tROH tOEA tREZ OE tRAC tCAC tOEZ tCEZ DQ VOL – Open Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRAS tRP RAS VIH – VIL – tAR tCRP tCRP tCSH tRCD tRSH VIH – CAS VIL – VIH – VIL – tRAD tRAH tCAS tASR tASC tCAH tRAL Address Row Column tWCS VIH – WE VIL – tWCH tWP tCWL tWCR tRWL VIH – OE VIL – VIH – tDS tDHR tDH DQ VIL – Valid Data-in Open "H" or "L" 9/17  ,,,       ¡ Semiconductor MSM514265C/CSL Read Modify Write Cycle tRWC tRAS tRP RAS VIH – VIL – tAR tCSH tCRP tCRP tRCD tRSH VIH – CAS VIL – tCAS tASR tRAH tASC tCAH VIH – Address VIL – WE OE VIH – VIL – VIH – VIL – VI/OH– Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL– tCLZ Valid Data-out Valid Data-in "H" or "L" 10/17 ¡ Semiconductor Fast Page Mode Read Cycle (Part-1) Address Fast Page Mode Read Cycle (Part-2) Address  , ,,,          ,   ,    MSM514265C/CSL tRASP tRP RAS VIH – VIL – tRSCD tAR tRHCP tCRP tRCD tHPC tCP tCP CAS VIH – VIL – tCAS tCAS tCAS tRAD tASR tRAH tASC tCSH tCAH tASC tCAH tASC tCAH VIH – VIL – VIH – VIL – VIH – VIL – Row Column Column Column tRCS tRRH WE tCHO tOCH tRAC tAA tOEP OE tAA tAA tOEP tOEA tCAC tCPA tDOH tCAC tOEA tOEA tOEZ tCAC tOEZ tREZ DQ VOH – VOL – tCLZ Valid Data-out Valid Data-out Valid* Data-out Valid* Data-out * : Same Data, "H" or "L" tRASP tRP RAS VIH – VIL – tRSCD tAR tRHCP tCRP tCRP tHPC tRCD tCP tCP CAS VIH – VIL – tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tCAH VIH – VIL – VIH – VIL – VIH – VIL – Row Column Column tRCS tRCS WE tRAC tAA tRCH tWPE tAA tAA OE tCPA tOEA tCAC tWEZ tCAC tCAC tDOH tCEZ DQ VOH – VOL – tCLZ Valid Data-out Valid Data-out Valid Data-out "H" or "L" 11/17 ,,  ,       ,          ,  ¡ Semiconductor MSM514265C/CSL Fast Page Mode Write Cycle (Early Write) tRSCD tRASP tRP RAS VIH – VIL – tAR tCRP tRCD tHPC tHPC tCP tCP CAS VIH – VIL – tCAS tCAS tCAS tRAD tASR tRAH tCSH tASC tCAH Column tASC tCAH tASC tRSH tCAH Address VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – Row Column Column tWCS tWCH tWCS tWCH tWCS tWCH WE OE tDHR tDS tDH tDS tDH tDS tDH DQ Valid Data-in Valid Data-in Valid Data-in "H" or "L" Fast Page Mode Read Modify Write Cycle tRSCD tRASP RAS VIH – VIL – tRWD tAR tCRP tRCD tCP CAS VIH – VIL – tRAD tCWD tASR tRAH tASC tHPRWC tCPWD tASC tCAH tCWL tCPA tCAH tRWL Address VIH – VIL – Row Column Column tRCS tAWD tRCS tCWD WE VIH – VIL – tRAC tAWD tAA tDS tWP tAA tDS tWP OE VIH – VIL – tOEA tOED tOEH tDH tOEA tOED tOEH tDH tCAC tOEZ tCAC tOEZ DQ VI/OH – VI/OL – Valid Data-out Valid Data-in Valid Data-out Valid Data-in tCLZ tCLZ "H" or "L" 12/17 ,    ¡ Semiconductor MSM514265C/CSL RAS-Only Refresh Cycle tRC RAS VIH – VIL – tRAS tRP tCRP tRPC CAS VIH – VIL – tASR tRAH Address VIH – VIL – Row tCEZ DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" CAS before RAS Refresh Cycle tRC tRP tRAS tRP RAS VIH – VIL – tRPC tRPC tCP tCSR tCHR CAS VIH – VIL – VOH – VOL – tCEZ DQ Open Note: WE, OE, Address = "H" or "L" 13/17 ¡ Semiconductor Hidden Refresh Read Cycle Hidden Refresh Write Cycle Address   ,,,   ,,      ,,       , MSM514265C/CSL tRC tRAS tRP tRC tRAS tRP RAS VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – tAR tCRP tRCD tRSH tCHR CAS tASR tRAH tRAD tASC tCAH Address Row Column tRCS tRAL tRRH WE tAA tROH OE VIH – VIL – tOEA tRAC tCAC tCLZ tOEZ DQ VOH – VOL – Open Valid Data-out "H" or "L" tRC tRAS tRP tRC tRAS tRP RAS VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – VIH – VIL – tAR tCRP tRCD tRSH tCHR CAS tASR tRAH tRAD tASC tCAH tRAL Row Column tWCS tRWL tWCH WE tWP tWCR OE tDS tDH DQ Valid Data-in tDHR "H" or "L" 14/17 ¡ Semiconductor CAS before RAS Self-Refresh Cycle tRP RAS VIH – VIL – tRPC tCP CAS VIH – VIL – tCEZ DQ VOH – VOL – Open tCSR tRASS Note: WE, OE, Address = "H" or "L" Only SL version ,   MSM514265C/CSL tRPS tRPC tCHS "H" or "L" 15/17 ¡ Semiconductor MSM514265C/CSL PACKAGE DIMENSIONS (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/17 ¡ Semiconductor MSM514265C/CSL (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/17
MSM514265CSL 价格&库存

很抱歉,暂时无法提供与“MSM514265CSL”相匹配的价格&库存,您可以联系我们找货

免费人工找货