MSM514800CSL-70

E2G0024-17-42 ¡ Semiconductor ¡ Semiconductor MSM514800C/CSL DESCRIPTION This MSM514800C/CSL version: Jan. 1998 Previous version: May 1997 524,288-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE The MSM514800C/CSL is a 524,288-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514800C/CSL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/ single-layer metal CMOS process. The MSM514800C/CSL is available in a 28-pin plastic SOJ or 28pin plastic TSOP. The MSM514800CSL (the self-refresh version) is specially designed for lowerpower applications. FEATURES • 524,288-word ¥ 8-bit configuration • Single 5 V power supply, ± 10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (SL version) • Fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • CAS before RAS self-refresh capability (SL version) • Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1.27) (Product : MSM514800C/CSL-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1.27-K) (Product : MSM514800C/CSL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM514800C/CSL-60 MSM514800C/CSL-70 MSM514800C/CSL-80 Access Time (Max.) tRAC tAA tCAC tOEA 60 ns 30 ns 20 ns 20 ns 70 ns 35 ns 20 ns 20 ns 80 ns 40 ns 20 ns 20 ns Power Dissipation Cycle Time (Min.) Operating (Max.) Standby (Max.) 110 ns 130 ns 150 ns 660 mW 605 mW 550 mW 5.5 mW/ 1.1 mW (SL version) 1/16   ¡ Semiconductor MSM514800C/CSL PIN CONFIGURATION (TOP VIEW) VCC 1 28 VSS VCC 1 28 VSS 27 DQ8 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 NC 20 A8 19 A7 18 A6 17 A5 16 A4 15 VSS DQ1 2 27 DQ8 DQ1 2 DQ2 3 DQ3 4 DQ4 5 DQ2 3 DQ3 4 DQ4 5 NC 6 WE 7 26 DQ7 25 DQ6 24 DQ5 23 CAS 22 OE 21 NC NC 6 WE 7 RAS 8 A9R 9 RAS 8 A9R 9 20 A8 19 A7 18 A6 17 A5 16 A4 A0 10 A1 11 A2 12 A3 13 A0 10 A1 11 A2 12 A3 13 VCC 14 28-Pin Plastic SOJ 15 VSS VCC 14 28-Pin Plastic TSOP (K Type) Pin Name A0 - A8, A9R RAS CAS DQ1 - DQ8 OE WE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input / Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) No Connection Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM514800C/CSL BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 9 Column Address Buffers Internal Address Counter 9 Column Decoders Write Clock Generator WE OE 8 Output Buffers 8 8 A0 - A8 Refresh Control Clock Sense Amplifiers 8 I/O Selector 8 8 DQ1 - DQ8 Input Buffers 8 9 A9R VCC 1 Row Address Buffers 10 Row Decoders Word Drivers Memory Cells On Chip VBB Generator VSS 3/16 ¡ Semiconductor MSM514800C/CSL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating –1.0 to 7.0 50 1 0 to 70 –55 to 150 Unit V mA W °C °C *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 –1.0 Typ. 5.0 0 — — Max. 5.5 0 6.5 0.8 (Ta = 0°C to 70°C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A8, A9R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ8) Symbol CIN1 CIN2 CI/O Typ. — — — (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Max. 7 7 8 Unit pF pF pF 4/16 ¡ Semiconductor DC Characteristics MSM514800C/CSL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol Condition MSM514800 MSM514800 MSM514800 C/CSL-70 C/CSL-60 C/CSL-80 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 –10 Max. VCC 0.4 10 Min. 2.4 0 –10 Max. VCC 0.4 10 V V mA 2.4 0 –10 VOH IOH = –5.0 mA VOL IOL = 4.2 mA 0 V £ VI £ 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC –0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS £ 1 ms RAS £ 0.2 V, CAS £ 0.2 V Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) Average Power Supply Current (CAS before RAS Self-Refresh) ILO –10 10 –10 10 –10 10 mA ICC1 — — — — — 120 2 1 200 120 — — — — — 110 2 1 200 110 — — — — — 100 2 1 200 100 mA 1, 2 mA mA 1 1, 5 mA 1, 2 — 5 — 5 — 5 mA 1 — 120 — 110 — 100 mA 1, 2 — 110 — 100 — 90 mA 1, 3 — 300 — 300 — 300 mA 1, 4, 5 ICCS — 300 — 300 — 300 mA 1, 5 Notes: 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. SL version. 5/16 ¡ Semiconductor AC Characteristics (1/2) MSM514800C/CSL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (SL version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Symbol MSM514800 MSM514800 MSM514800 C/CSL-70 C/CSL-60 C/CSL-80 Unit Note Min. Max. — — — — 60 20 30 35 20 — 15 15 50 16 128 — 10,000 100,000 Min. 130 185 45 100 — — — — — 0 0 0 3 — — 50 70 70 20 20 10 20 70 10 40 20 15 0 10 0 15 55 35 0 0 0 Max. — — — — 70 20 35 40 20 — 20 20 50 16 128 — 10,000 100,000 Min. 150 205 50 105 — — — — — 0 0 0 3 — — 60 80 80 20 20 10 20 80 10 45 20 15 0 10 0 15 60 40 0 0 0 Max. — — — — 80 20 40 45 20 — 20 20 50 16 128 — 10,000 100,000 tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH 110 155 40 85 — — — — — 0 0 0 3 — — 40 60 60 15 15 10 20 60 10 35 20 15 0 10 0 10 50 30 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 11 — — — 10,000 — — — 40 30 — — — — — — — — — — — — 10,000 — — — 50 35 — — — — — — — — — — — — 10,000 — — — 60 40 — — — — — — — — — 6/16 ¡ Semiconductor AC Characteristics (2/2) MSM514800C/CSL (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) RAS Pulse Width (CAS before RAS Self-Refresh) RAS Precharge Time (CAS before RAS Self-Refresh) CAS Hold Time (CAS before RAS Self-Refresh) Symbol MSM514800 MSM514800 MSM514800 C/CSL-60 C/CSL-70 C/CSL-80 Unit Note Min. Max. — — — — — — — — — — — — — — — — — — — — — Min. 0 15 55 15 20 20 20 0 15 55 20 50 65 100 70 10 10 15 100 130 –50 Max. — — — — — — — — — — — — — — — — — — — — — Min. 0 15 60 15 20 20 20 0 15 60 20 50 70 110 75 10 10 15 100 150 –60 Max. — — — — — — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 11 11 11 9 9 9 9 10 10 9 0 15 50 15 15 15 15 0 15 50 15 40 60 90 65 10 10 15 100 110 –40 tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tRASS tRPS tCHS 7/16 ¡ Semiconductor Notes: MSM514800C/CSL 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. Only SL version. 8/16 E2G0096-17-41I ¡ Semiconductor MSM514800C/CSL 



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,,,,  TIMING WAVEFORM Read Cycle tRC tRAS tRP RAS VIH – VIL – tAR tCRP tCRP tCSH tRCD CAS VIH – VIL – tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address VIH – VIL – VIH – VIL – Row Column tRCS tRRH tRCH WE tAA tROH VIH – OE VIL – VOH – tOEA tRAC tCAC tOEZ tOFF DQ VOL – Open Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRAS tRP RAS VIH – VIL – tAR tCRP tCRP tCSH tRCD tRSH VIH – CAS VIL – VIH – VIL – VIH – VIL – tRAD tRAH tCAS tASR tASC tCAH tRAL Address Row Column tWCS tWCH tWP tCWL WE tWCR tRWL OE VIH – VIL – tDS tDHR tDH DQ VIH – VIL – Valid Data-in Open "H" or "L" 9/16 
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     ¡ Semiconductor MSM514800C/CSL Read Modify Write Cycle tRWC tRAS tRP RAS VIH – VIL – tAR tCSH tCRP tCRP tRCD tRSH VIH – CAS VIL – tCAS tASR tRAH tASC tCAH VIH – Address VIL – WE OE VIH – VIL – VIH – VIL – VI/OH– Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL– tCLZ Valid Data-out Valid Data-in "H" or "L" 10/16 
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¡ Semiconductor MSM514800C/CSL Fast Page Mode Read Cycle tRASP tRP VIH – RAS V – IL VIH – CAS VIL – VIH – VIL – VIH – VIL – tAR tRHCP tCRP tRCD tPC tRSH tCRP tCP tCP tRAD tCAS tCAS tCAS tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Address Row Column Column Column tRCS tRCH tRCS tAA tRCH tRCS tAA tRCH WE tAA tRRH VIH – OE VIL – tOEA tCPA tCPA tOEA tOEA tCAC tRAC tOFF tOEZ tCAC tOFF tCAC tOFF tCLZ tOEZ tCLZ tOEZ VOH – DQ VOL – tCLZ Valid Data-out Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tPC tRP VIH – RAS V – IL VIH – CAS VIL – VIH – VIL – tAR tRHCP tCRP tRCD tRSH tCRP tCAS tCP tCP tCAS tCAS tASR tRAH tASC tRAD tCSH tCAH tASC tCAH tASC tCAH tRAL Address Row tWCS VIH – WE VIL – Column tCWL tWCH tWP tWCR tDH Column tCWL tWCS tWCH tWP Column tRWL tCWL tWCS tWCH tWP tDS tDH tDS tDS tDH DQ VIH – VIL – Valid Data-in Valid Data-in Valid Data-in tDHR Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor Fast Page Mode Read Modify Write Cycle VIH – RAS VIL – tAR VIH – CAS VIL – Address VIH – VIL – V WE IH – VIL – VIH – OE V – IL VI/OH– VI/OL – DQ RAS-Only Refresh Cycle RAS VIH – VIL – CAS VIH – VIL – Address VIH – VIL – DQ VOH – VOL – 
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, tRASP tRP tCSH tPRWC tRCD tCAS tCP tCAS tCP tRSH tCAS tCRP tRAD tRAH tCAH tASC tASC tASR tASC tCAH tCAH tRAL Row Column tRWD Column Column tRCS tCWD tCWL tRCS tCPWD tCWD tAWD tCWL tRCS tCPWD tCWD tAWD tRWL tCWL tAWD tRAC tDS tWP tDH tDS tWP tDH tROH tDS tWP tDH tAA tCPA tAA tCPA tAA tOEA tOEA tOEA tOED tOED tOED tCAC tOEZ tCAC tOEZ In MSM514800C/CSL tCAC tOEZ Out In Out Out In tCLZ tCLZ tCLZ "H" or "L" tRC tRAS tRP tCRP tRPC tASR tRAH Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 ¡ Semiconductor 
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,,,  MSM514800C/CSL CAS before RAS Refresh Cycle tRC tRP tRAS tRP RAS VIH – VIL – tRPC tRPC tCP tCSR tCHR CAS VIH – VIL – VOH – VOL – tOFF DQ Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRC tRAS tRP tRAS tRP RAS VIH – VIL – VIH – VIL – tAR tCRP tRCD tRSH tCHR CAS tASR tRAD tASC tRAH tCAH Address VIH – VIL – Row Column tRCS tRAL tRRH VIH – WE V IL – VIH – OE V IL – tAA tROH tOEA tRAC DQ VOH – VOL – tCAC tCLZ Valid Data-out tOFF tOEZ "H" or "L" 13/16 


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Hidden Refresh Write Cycle tRC tRAS tRP tRC tRAS tRP VIH – RAS VIL – CAS VIH – VIL – tAR tCRP tRCD tRSH tCHR tASR tRAH tRAD tASC tCAH tRAL Address VIH – VIL – V WE IH – VIL – VIH – OE VIL – Row tWCS Column tRWL tWCH tWP tWCR tDS tDH DQ VIH – VIL – Valid Data-in tDHR "H" or "L" ¡ Semiconductor MSM514800C/CSL CAS before RAS Self-Refresh Cycle tRP tRASS tRPS RAS VIH – VIL – tRPC tCP tCSR tRPC tCHS CAS VIH – VIL – tOFF DQ VOH – VOL – Open Note: WE, OE, Address = "H" or "L" Only SL version "H" or "L" 14/16 ¡ Semiconductor MSM514800C/CSL PACKAGE DIMENSIONS (Unit : mm) SOJ28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM514800C/CSL (Unit : mm) TSOPII28-P-400-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.51 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16