MSM51V17405F

FEDD51V17405F-01 1 Semiconductor MSM51V17405F DESCRIPTION This version: June. 2000 Previous version :  4,194,304-Word × 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO The MSM51V17405F is a 4,194,304-word × 4-bit dynamic RAM fabricated in Oki’s silicon-gate CMOS technology. The MSM51V17405F achieves high integration, high-speed operation, and lowpower consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V17405F is available in a 26/24-pin plastic SOJ or 26/24-pin plastic TSOP. FEATURES ∙ 4,194,304-word × 4-bit configuration ∙ Single 3.3V power supply, ±0.3V tolerance ∙ Input : LVTTL compatible, low input capacitance ∙ Output : LVTTL compatible, 3-state ∙ Refresh : 2048 cycles/32ms ∙ Fast page mode with EDO, read modify write capability ∙ CAS before RAS refresh, hidden refresh, RAS-only refresh capability ∙ Packages 26/24-pin 300mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM51V17405F-xxSJ) 26/24-pin 300mil plastic TSOP (TSOPII26/24-P-300-0.80-K) (Product : MSM51V17405F-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Family tRAC 50ns 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 84ns 104ns 124ns Power Dissipation Operating (Max.) 360mW 324mW 288mW Standby (Max.) 1.8mW MSM51V17405F 1/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F PIN CONFIGURATION (TOP VIEW) VCC DQ1 DQ2 WE RAS NC A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13 26/24-Pin Plastic SOJ 26/24-Pin Plastic TSOP (K Type) Pin Name A0–A10 RAS CAS DQ1–DQ4 OE WE VCC VSS NC Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 11 Column Address Buffers Internal Address Counter Row Address Buffers 11 Column Decoders Write Clock Generator WE OE 4 Output Buffers 4 4 4 Input Buffers 4 A0 − A10 Refresh Control Clock Sense Amplifiers 4 I/O Selector 4 DQ1 − DQ4 11 11 Row Decoders Word Drivers Memory Cells VCC On Chip VBB Generator VSS 3/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIUM RATINGS Parameter Voltage VCC Supply relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Value –0.5 to 4.6 50 1 0 to 70 –55 to 150 Unit V mA W °C °C *: Ta = 25°C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 − 0.3 Typ. 3.3 0   Max. 3.6 0 VCC + 0.3 0.8 Unit V V V V Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS − 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). PIN CAPACITANCE (Vcc = 3.3V ± 0.3V, Ta = 25°C, f = 1 MHz) Parameter Input Capacitance (A0 – A10) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 – DQ4) Symbol CIN1 CIN2 CI/O Min. — — — Typ. — — — Min. 5 7 7 Unit pF pF pF 4/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) MSM51V17405 MSM51V17405 MSM51V17405 F-50 F-60 F-70 Unit Note Min. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) VOH VOL IOH = −2.0mA IOL = 2.0mA 0V ≤ VI ≤ VCC+0.3V; ILI All other pins not under test = 0V DQ disable 0V ≤ VO ≤ VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS ≥ VCC − 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tHPC = Min.  100  90  80 mA 1,3  5  5  5 mA 1  100  90  80 mA 1,2 − 10 10 − 10 10 − 10 10 µA 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 Min. 2.4 0 Max. VCC 0.4 V V Parameter Symbol Condition ILO − 10 10 − 10 10 − 10 10 µA ICC1  100  90  80 mA 1,2   2 0.5   2 0.5   2 mA 0.5 1 ICC6  100  90  80 mA 1,2 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F AC CHARACTERISTICS (1/3) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13 Parameter MSM51V17405 F-50 Symbol Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time tRC tRWC tHPC 84 110 20 58      0 5 0 0 0 0 1  30 50 50 7 7 7 7 35 Max.     50 13 25 30 13   13 13 13 13 50 32  10,000 100,000    10,000  MSM51V17405 F-60 Min. 104 135 25 68      0 5 0 0 0 0 1  40 60 60 10 10 10 10 40 Max.     60 15 30 35 15   15 15 15 15 50 32  10,000 100,000    10,000  MSM51V17405 F-70 Unit Min. 124 160 30 78      0 5 0 0 0 0 1  50 70 70 13 13 10 13 45 Max.     70 20 35 40 20   20 20 20 20 50 32  10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 7,8 7,8 7 7 3 4, 5, 6 4,5 4,6 4 4 4 Note Fast Page Mode Read Modify Write tHPRWC Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turnoff Delay Time RAS to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turnoff Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode with EDO) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode with EDO) CAS Pulse Width CAS Hold Time tRAC tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH 100,000 ns    10,000  ns ns ns ns ns 6/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F AC CHARACTERISTICS (2/3) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13 Parameter CAS to RAS Precharge Time MSM51V17405 F-50 Symbol Min. tCRP 5 30 5 11 9 0 7 0 7 25 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 Max.    37 25                         MSM51V17405 F-60 Min. 5 35 5 14 12 0 10 0 10 30 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 Max.    45 30                         MSM51V17405 F-70 Unit Min. 5 40 5 14 12 0 10 0 13 35 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 Max.    50 35                         ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 11 11 9 9 10 5 6 Note RAS Hold Time from CAS Precharge tRHCP OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time tCHO tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD 7/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F AC CHARACTERISTICS (3/3) (VCC = 3.3V ± 0.3V, Ta = 0 to 70°C) Note1,2,3,12,13 Parameter CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to CAS Hold Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) MSM51V17405 F-50 Symbol Min. tRPC tCSR tCHR tWRP tWRH tWTS tWTH 5 5 10 10 10 10 10 Max.        MSM51V17405 F-60 Min. 5 5 10 10 10 10 10 Max.        MSM51V17405 F-70 Unit Min. 5 5 10 10 10 10 10 Max.        ns ns ns ns ns ns ns Note 8/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 2ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. -50 is measured with a load circuit equivalent to 1 TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 1 TTL load and 100pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.), and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. tCEZ, and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test CA9 and CA10 are not used and each DQ pin now access 4-bit locations. Since all 4 DQ pins are used, a total 16 data bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 9/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F TIMING CHART Read Cycle RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC DQ VOH VOL tCLZ Open Valid Data-out “H” or “L” tAA tROH tOEA tCAC tOEZ tRCH tREZ tRAD tRAL tRAH tASC Column tRCS tCAH tRCD tCSH tRSH tCAS tCRP tRC tRAS tRP Row tRRH WE OE tCEZ Write Cycle (Early Write) VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAL tRAH tASC tCAH tRCD tRC tRAS tRP tCSH tRSH tCAS tCRP RAS Row tWCS Column tCWL tWCH tWP tRWL WE VIH VIL VIH VIL tDS VIH VIL OE tDH Valid Data-in Open “H” or “L” DQ 10/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F Read Modify Write Cycle tRWC RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC tCAH tCWL tRWL tRCD tRAS tRP tCSH tRSH tCAS tCRP Row Column tRCS tRWD tCWD tWP tAWD tAA tOEA tOED tCAC tRAC tOEZ tCLZ Valid Data-out WE VIH VIL VIH VIL tOEH OE tDH tDS Valid Data-in DQ VI/OH VI/OL “H” or “L” 11/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F Fast Page Mode Read Cycle (Part-1) tRASP RAS VIH VIL tCRP CAS VIH VIL VIH VIL VIH VIL VIH VIL tOEA tCAC DQ VOH VOL tCLZ * : Same Data, “H” or “L” tAA tRAC tAA tCPA tDOH Valid Data-out tOEZ Valid Data-out tRP tHPC tRHCP tCP tCAS tCAS tASC tCAH tRCD tCSH tCAS tRAD tASR Row tRCS tRAH tASC tCAH tASC tCP tCAH Address Column Column Column tOCH tCHO tOEP tCAC tAA tRRH WE tCAC tOEP tOEA OE tOEA tOEZ Valid * Data-out tREZ Valid * Data-out Fast Page Mode Read Cycle (Part-2) tRASP RAS VIH VIL tCRP tRCD CAS VIH VIL VIH VIL VIH VIL VIH VIL tCAC tCAC DQ VOH VOL tCLZ “H” or “L” tWEZ Valid Data-out tRP tHPC tRHCP tHPC tCRP tCP tCAS tCAH Column tASC Column tCAS tCSH tCP tCAS tASR Row tRAD tRAH tASC tCAH tASC tCAH Address Column tRCS tRCS tAA tRAC tRCH tWPE tOEA WE tAA tCPA tAA OE tCAC tDOH Valid Data-out tCEZ Valid Data-out 12/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tDS DQ VIH VIL Valid Data-in tRP tHPC tHPC tCP tCAS tRSH tCAS tCAH tCSH tCRP tRCD tCAS tRAD tASR Row tWCS tRAH tASC tCAH tASC tCP CAS tCAH tASC Address Column tWCH Column tWCS tWCH Column tWCS tWCH WE OE tDH tDS Valid Data-in tDH tDS Valid Data-in tDH “H” or “L” Fast Page Mode Read Modify Write Cycle tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAC OE VIH VIL tCAC DQ VI/OH VI/OL tCLZ tOEZ Valid Data-out tRWD tCRP tRCD tCWD tASC tRAD tRAH Column tRCS tRCS tAWD tAA tOEA tOED tDH Valid Data-in tCPWD tCP tASC tHPRWC tCAH tCWL Column tCWD tAWD tDS tWP tAA tOEA tOEH tCAC tOEZ Valid Data-out Valid Data-in tRWL CAS tCAH tCPA Row WE tDS tWP tOED tOEH tDH tCLZ “H” or “L” 13/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F RAS-only Refresh Cycle tRC RAS VIH VIL VIH VIL VIH VIL VOH VOL tASR tRAH tCRP tRAS tRP tRPC CAS Address Row tCEZ DQ Open Note: WE, OE = “H” or “L” “H” or “L” CAS before RAS Refresh Cycle tRP RAS VIH VIL VIH VIL VIH VIL tCEZ DQ VOH VOL Open Note: OE, Address = “H” or “L” “H” or “L” tWRP tRPC tCP tCSR tCHR tWRH tWRP tRAS tRP tRPC tRC CAS WE 14/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F Hidden Refresh Read Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAD tRAH Row tRCS WE tASC Column tCAC tRAL tAA tROH OE VIH VIL VOH VOL tRAC tCLZ Open Valid Data-out “H” or “L” tOEA tOEZ tCEZ tREZ tRRH tCAH tCRP tRCD tRAS tRSH tRP tCHR tRAS tRP tRC CAS DQ Hidden Refresh Write Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL tRAD tRAH Row tASC tCAH Column tRAL tRWL tWP tWCH tCRP tRCD tRAS tRSH tRP tCHR tRAS tRP tRC CAS WE VIH VIL tWCS VIH VIL VIH VIL tDS OE tDH Valid Data-in DQ “H” or “L” 15/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F Test Mode-in Cycle tRC tRP RAS VIH VIL VIH VIL tWTS WE VIH VIL VIH VIL tOFF Open Note: OE, Address = “H” or “L” “H” or “L” tWTH tRPC tCP tCSR tCHR tRAS CAS DQ 16/17 FEDD51V17405F-01 1 Semiconductor MSM51V17405F NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 17/17