MSM5260

E2B0016-27-Y2 ¡ Semiconductor ¡ Semiconductor MSM5260 80-DOT COMMON/SEGMENT DRIVER This version: Nov. 1997 MSM5260 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM5260 is a dot matrix common/segment LCD driver LSI which is fabricated using low power CMOS metal gate technology. This LSI consists of 80-bit shift register, 80-bit latch, 80-bit level shifter and 80-bit 4-level driver. It converts display data, which is serially received from an LCD controller LSI, to parallel data, and outputs LCD driving waveform to LCD. This LSI can drive a variety of LCD panels since the bias voltage can be optionally supplied from an external source. FEATURES • • • • • • • Supply voltage : 4.5 to 5.5V LCD driving voltage : 8 to 18V Applicable LCD duty : static and 1/32 to 1/64 Bias voltage can be supplied externally Can be used either as common or segment driver Interface with MSM6255 LCD controller LSI Package options : 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5260GS-K) 100-pin plastic QFP (QFP100-P-1420-0.65-L) (Product name : MSM5260GS-L) 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5260GS-BK) 1/12 ¡ Semiconductor MSM5260 BLOCK DIAGRAM O1 O2 O79 O80 VDD V2 V3 V5 VDD 80-Bit 4-Level Driver V5 80-Bit Level Shifter DF COM/SEG LOAD VDD VSS 80-Bit Latch VSS DO80 DI1 CP 80-Bit Shift Register 2/12 ¡ Semiconductor MSM5260 PIN CONFIGURATION (TOP VIEW) NC DI1 NC VSS DF NC COM/SEG NC LOAD DO80 VDD* NC NC NC NC CP O1 V3 V5 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 O31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 V2 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 O52 O51 O32 O33 O34 O35 O36 O37 O38 O39 O40 VDD* O41 O42 O43 O44 O45 O46 O47 O48 O49 NC : No connection 100-Pin Plastic QFP (Type K) *VDD must be supplied to both pin 40 and pin 97. O50 3/12 ¡ Semiconductor MSM5260 PIN CONFIGURATION O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26 O27 O28 O29 O30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 O1 NC V3 VDD* CP NC DI1 NC NC NC NC DO80 NC LOAD VSS DF NC COM/SEG V5 V2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 9 O31 O2 O3 O4 O5 O6 O7 O8 O9 O32 O33 O34 O35 O36 O37 O38 O39 O40 VDD* O41 O42 O43 O44 O45 O46 O47 O48 O49 O50 O80 O79 O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53 NC : No connection 100-Pin Plastic QFP (Type L) *VDD must be supplied to both pin 40 and pin 97. Note: This figure shows the configuration viewed from the reverse side of the package. Pay attention to the difference in pin arrangement. O52 O51 4/12 ¡ Semiconductor MSM5260 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage (1) Supply Voltage (2) Input Voltage Storage Temperature Symbol VDD VLCD VI TSTG Condition Ta = 25°C Ta = 25°C, VDD – V5 *1 Ta = 25°C, VDD – V5 *1*2 Ta = 25°C — Rating –0.3 to +6.0 0 to 18 0 to 20 –0.3 to VDD +0.3 –55 to +150 Unit V V V V °C *1 VDD > V2 > V3 > V5 *2 When a series resistance of more than 47W is connected as shown below: VDD V2 MSM5260 V3 V5 VSS RS≥47W –V VDD–V5 +V 5/12 ¡ Semiconductor MSM5260 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (1) Supply Voltage (2) Operating Temperature Symbol VDD VLCD Top Condition — VDD – V5 *1 VDD – V5 *1*2 — Range 4.5 to 5.5 8 to 16 8 to 18 –20 to +85 Unit V V V °C *1 VDD > V2 > V3 > V5 *2 When a series resistance of more than 47W is connected as shown below: VDD V2 MSM5260 V3 V5 VSS RS≥47W VDD–V5 +V –V ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 5V ± 10%, Ta = –20 to +85°C) Parameter "H" Input Voltage "L" Input Voltage "H" Input Current "L" Input Current "H" Output Voltage "L" Output Voltage ON Resistance Supply Current Symbol VIH *1 VIL *1 IIH *1 VIH = VDD IIL *1 VIL = 0V VOH *2 IO = –0.4mA VOL *2 IO = 0.4mA RON *4 IDD VDD–V5 = 10V VN–VO = 0.25V CP = DC VDD–V5 = 18V, no load *3 Condition Min. 0.8VDD VSS — — VDD – 0.4 — — — Typ. — — — — — — 1 — Max. VDD 0.2VDD 1 –1 — 0.4 2 100 Unit V V mA mA V V kW mA *1 *2 *3 *4 Applied to LOAD, CP, DI1, DF and COM/SEG Applied to DO80 VN = VDD to V5, V2 = 8/9 (VDD – V5), V3 = 1/9 (VDD – V5) Applied to O1 to O80 6/12 ¡ Semiconductor Switching Characteristics MSM5260 (VDD = 5V ± 10%, Ta = –20 to +85°C, CL = 15pF) Parameter "H","L" Propagation Delay Time Clock Frequency Clock Pulse Width LOAD Pulse Width Data Setup Time DIÆCP CPÆLOAD Time LOADÆCP Time Data Hold Time DIÆCP CP Rise/Fall Time LOAD Rise/Fall Time Symbol tpLH tpHL fCP tW(CP) tW(L) tSETUP tCL tLC tHOLD tr(CP) tf(CP) tr(L) tf(L) Condition — Duty = 50% — — — — — — — — Min. — — 125 125 50 250 0 50 — — Typ. — — — — — — — — — — Max. 250 3.3 — — — — — — 50 1 Unit ns MHZ ns ns ns ns ns ns ns ms tf(CP) tw(CP) 0.8VDD CP 0.8VDD tSETUP 0.2VDD tHOLD DI1 0.8VDD 0.8VDD 0.2VDD 0.2VDD tr(CP) tw(CP) 0.8VDD 0.2VDD tSETUP 0.8 VDD 0.2 VDD 0.8VDD 0.2VDD tHOLD 0.8 VDD 0.2 VDD tPLH tPHL DO80 0.8VDD 0.2VDD tCL LOAD 0.2VDD tr(L) 0.8VDD tw(L) 0.8VDD tf(L) tLC 0.2VDD 7/12 ¡ Semiconductor MSM5260 FUNCTIONAL DESCRIPTION Pin Functional Description • DI1 The data input pin for the 80-bit shift register (between 1st to 80th bit). The display data is clocked in to this pin. (Positive logic) • CP Clock pulse input pin for 80-bit shift register. The data is shifted to the 80-bit shift register at the falling edge of the clock pulse. A data setup time (tSETUP) and a data hold time (tHOLD) are required between a DI1 signal and a clock pulse. Clock pulse rise time (tr) and clock pulse fall time (tf) should be a maximum of 50ns respectively. • DO80 The 80th bit output from the 80-bit shift register. The data which is input from DI1 is clocked out with the delay in the number of the bits of the shift register. When extending the number of characters, this pin is used to connect to the next MSM5260 in cascade. • LOAD The signal for latching the shift register contents is input from this pin. When LOAD pin is set at "H" level, the shift register contents are transferred to the 80-bit 4level driver through the 80-bit level shifter. When LOAD pin is set at "L" level, the last display output data (O1 to O80), which was transferred when LOAD pin was at "H" level, is held. • DF Synchronous signal input pin for alternate signal for LCD driving. 8/12 ¡ Semiconductor MSM5260 • COM/SEG Selection signal input pin. MSM5260 is used either as common driver or segment driver according to input signal level at COM/SEG pin. When this pin is set when at "H" level, MSM5260 is used as a common driver, while it is used as a segment driver when at "L" level. The display driving data O1 to O80 are determined according to the combination of latched data and DF signal, as shown in Table 1 below. Table 1 Latched data level High H (Select) Low (Non-select) High L (Select) Low (Non-select) Driver data output level (O1 - O80) VDD V5 V3 V2 V5 VDD V3 V2 Segment driver Common driver COM/SEG DF H L H L H L H L Remarks When MSM5260 is used as a common driver, both LOAD pin and COM/SEG pin are to be connected to VDD. In this case, a bias voltage of common side’s non-select level is to be supplied to V2 and V3 pins. • VDD, VSS Supply voltage pins. VDD should be 4.5 to 5.5V. VSS is a ground pin (VSS = 0V) • V2, V3, V5 Bias supply voltage pins to drive the LCD. Use an external bias voltage supply for driving the LCD. • O1 to O80 Display data output pins which correspond to each bit of the 80-bit latch. One of VDD, V2, V3 and V5 is selected as a display driving voltage source according to the combination of latched data level and DF signal. NOTES ON USE Note the following when turning power on and off : The LCD drivers of this IC requiers a high voltage. For this reason, if a high voltage is applied to the LCD drivers with the logic power supply floating, excess current flows. This may damage the IC. Be sure to carry out the following power-on and power-off sequences : When turning power on : First VDD ON, next V5, V3, V2 ON. Or both ON at the same time. When turning power off : First V5, V3, V2 OFF, next VDD OFF. Or both OFF at the same time. 9/12 ¡ Semiconductor MSM5260 PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 10/12 ¡ Semiconductor MSM5260 (Unit : mm) QFP100-P-1420-0.65-L Spherical surface Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 11/12 ¡ Semiconductor MSM5260 (Unit : mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 12/12