MSM5265

E2B0008-27-Y2 ¡ Semiconductor ¡ Semiconductor MSM5265 80-DOT LCD DRIVER This version: Nov. 1997 MSM5265 Previous version: Mar. 1996 GENERAL DESCRIPTION The MSM5265 is an LCD driver which can directly drive up to 80 segments in the static display mode and up to 160 segments in the 1/2 duty dynamic display mode. The MSM5265 is fabricated with low power CMOS metal gate technology. The MSM5265 consists of a 160-stage shift register, 160-bit data latch, 80 pairs of LCD drivers and a common signal generator. The display data is serially input from the DATA-IN pin to the 160-stage shift register synchronized with the CLOCK pulse. The data is shifted into the 160-bit data latch by the LOAD signal. Then the latched data is directly output to the LCD from the 80 pairs of LCD drivers as a serial output. The common signal can be generated by the built-in generator, or externally input. The common synchronization circuit which is used in the dynamic display mode is integrated on the chip. FEATURES • • • • • • • • • • • • Supply voltage : 3.0 to 6.0 V Drives LCD of up to 80 segments (in the static display mode) Drives LCD of up to 160 segments (in the 1/2 duty dynamic display mode) Simple interface with microcomputer Bit-to-bit correspondence between input data and output data H: Display ON L: Display OFF Can be cascade-connected Built-in common signal generator Can be synchronized with the external common signal Testing pins for all-on (SEG-TEST) and all-off (BLANK) Applicable as an output expander LCD driving voltage can be adjusted by the combination of VLC1 and VLC2 Package options: 100-pin plastic QFP (QFP100-P-1420-0.65-K) (Product name : MSM5265GS-K) 100-pin plastic QFP (QFP100-P-1420-0.65-BK) (Product name : MSM5265GS-BK) 1/18 ¡ Semiconductor MSM5265 BLOCK DIAGRAM To LCD panel SEG 1 SEG 80 SEG-TEST 80-Dot Segment Driver BLANK 80 80-Ch Data Selector VDD GND LOAD DATA-IN CLOCK D/S OSC-OUT OSC-OUT OSC-IN EXT/INT SYNC SYNC Circuit OSC 1/4 or 1/8 1/2 Common Driver VLC1 VLC2 COM-A COM-B COM-OUT (A) 80-Stage Shift Register (B) 80-Stage Shift Register DATA-OUT 2 80 (A) 80-Bit Data Latch 80 (B) 80-Bit Data Latch DATA-OUT 1 2/18 ¡ Semiconductor MSM5265 PIN CONFIGURATION (TOP VIEW) 100 SEG50 99 SEG49 98 SEG48 97 SEG47 96 SEG46 95 SEG45 94 SEG44 93 SEG43 92 SEG42 91 SEG41 90 SEG40 89 SEG39 88 SEG38 87 SEG37 86 SEG36 85 SEG35 84 SEG34 83 SEG33 82 SEG32 81 SEG31 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 LOAD CLOCK DATA-IN DATA-OUT1 DATA-OUT2 OSC-OUT OSC-OUT OSC-IN EXT/INT VDD D/S GND SEG-TEST BLANK SYNC COM-OUT VLC1 COM-A COM-B VLC2 100-Pin Plastic QFP 3/18 ¡ Semiconductor MSM5265 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Storage Temperature Symbol VDD VI TSTG Condition Ta = 25°C Ta = 25°C — Rating –0.3 to +6.5 GND–0.3 to VDD +0.3 –55 to +150 Unit V V °C RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Operating Temperature LCD Driving Voltage Symbol VDD Top VLCD Condition — — VDD–VLC2 Range 3 to 6 –40 to +85 3 to VDD Unit V °C V • Oscillation circuit Parameter Oscillator Resistance Oscillator Capacitance Current Limiting Resistance Common Signal Frequency Symbol Corresponding pin R0 C0 R1 fCOM OSC-OUT OSC-OUT OSC-IN COM-A COM-B Condition — Min. 56 Typ. 100 — 1 — Max. 220 0.047 2.2 150 Unit kW mF MW Hz Film capacitor 0.001 R1≥10 R0 — 0.56 25 (MSM5265) R0 OSC-OUT C0 OSC-OUT R1 OSC-IN 4/18 ¡ Semiconductor MSM5265 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter "H" Input Voltage "L" Input Voltage Input Leakage Current "H" Output Voltage Symbol VIH VIL Condition — — (VDD = 5.0 V Ta =–40 to +85°C) Min. Typ. Max. Unit Applicable pin 36 GND — — VDD 1.0 V V SEG-TEST, BLANK, LOAD, DATA-IN, CLOCK, D/S, EXT/INT, OSC-IN IIL VI = 5.0 V/0 V — — ±1 mA VOH IO = –100 mA 4.5 — — V DATA-OUT1 DATA-OUT2 COM-OUT OSC-OUT OSC-OUT SEG1-SEG80 COM-A COM-B COM-A COM-B DATA-OUT1 DATA-OUT2 COM-OUT OSC-OUT OSC-OUT SEG1 - SEG80 COM-A COM-B SYNC SYNC IO = –200 mA VLC1 = 2.5 V, VLC2 = 0 V IO = –30 mA VLC1 = 2.5 V, VLC2 = 0 V IO = –150 mA "M" Output Voltage "L" Output Voltage VOM VLC1 = 2.5 V, VLC2 = 0 V IO = ±150 mA IO = 100 mA 4.5 4.8 4.8 2.3 — — — — — — — 2.7 V V V V VOL — — 0.5 V IO = 200 mA VLC1 = 2.5 V, VLC2 = 0 V IO = 30 mA VLC1 = 2.5 V, VLC2 = 0 V IO = 150 mA IO = 250 mA Output Leakage Current Segment Output Impedance VO = 5 V when internal Tr is off — — — — — — — — — — 0.5 0.2 0.2 0.8 5 V V V V mA ILO RSEG VLC1 = (5+VLC2)/2 VLC2 = 0 to 2 V — — 10 kW SEG1 - SEG80 5/18 ¡ Semiconductor MSM5265 Parameter Common Output Impedance Static Supply Current Dynamic Supply Current Symbol RCOM IDD1 Condition VLC1 = (5+VLC2)/2 VLC2 = 0 to 2 V Fix all input levels at either VDD or GND No load. R0 = 100 kW, C0 = 0.01 mF, R1 = 1 MW Min. — — Typ. — — Max. 1.5 100 Unit kW mA Applicable Pin COM-A COM-B VDD — 0.12 0.5 mA IDD2 Switching Characteristics Parameter Clock Frequency Clock Pulse "H" Time Clock Pulse "L" Time Data Setup Time Data Hold Time "H"‚ "L" Propagation Delay Time LOAD Pulse "H" Time Clock Æ LOAD Time OSC-IN Input Frequency SYNC Pulse "L" Time Symbol ff ffH ffL fD–f ff–D tPHL tPLH tL tf–L fOSC ts Condition — — — — — Load capacitance of DATA-OUT1, DATA-OUT2: 15 pF — — — — (VDD = 3.0 to 6.0 V Ta = –40 to +85°C) Min. Max. — 0.3 0.5 0.1 0.1 — 0.2 0.1 — 0.2 1 — — — — 0.8 — — 5 — Unit Applicable Pin MHz ms ms ms ms ms ms ms kHz ms DATA-IN CLOCK DATA-OUT1 DATA-OUT2 CLOCK LOAD CLOCK LOAD OSC-IN SYNC CLOCK VH DATA-IN VL tD-f CLOCK VL tfL VL VH VL tf-D tfH VH VH VL tL VH VL tPHL tPLH VH VL ts VL VL (VH = 0.8 VDD, VL = 0.2 VDD) VH tf-L LOAD DATA-OUT1 DATA-OUT 2 SYNC 6/18 ¡ Semiconductor MSM5265 FUNCTIONAL DESCRIPTION Operational Description The MSM5265 consists of a 160-stage shift register, 160-bit data latch, and 80 pairs of LCD drivers. The display data is input from the DATA-IN pin to the 160-stage shift register at the rising edge of the CLOCK pulse and it is shifted to the 160-bit data latch when the LOAD signal is set at "H" level, then it is directly output from the 80 pairs of LCD drivers to the LCD panel. Input the display data in the order of SEG80, SEG79, SEG78, ..., SEG2, SEG1. DATA-IN 1 CLOCK 2 3 4 5 6 159 160 LOAD DATA LATCH Output (inside the IC) Pin Functional Description • OSC-IN, OSC-OUT, OSC-OUT As shown in the figure below, by connecting the external resistors R0, R1 and external capacitor C0 with OSC-IN, OSC-OUT and OSC-OUT respectively, an oscillating circuit to generate the common signal is formed. This frequency is divided into either 1/8 or 1/4 by the internal dividing circuit. The 1/8 divided frequency is used in the static display mode, while the 1/4 divided frequency is used as the common signal in the 1/2 duty dynamic display mode which is output from the COMOUT pin. (EXT/INT should be set at low level.) The resistor R1 is used to limit the current on the OSC-IN pin's protecting diodes. The value of the R1 should be more than 10 times that of R0. When the external common signal is used, the EXT/INT pin should be set at high level and the external common signal should be input from the OSC-IN pin. Keep the wiring between the OSC-IN pin and R1 as short as possible, because the OSC-IN pin becomes susceptible to external noise if the value of R1 is large. (MSM5265) R0 OSC-OUT fOSC = 1/2.2 C0R0 R1≥10 R0 C0 OSC-OUT VDD R1 OSC-IN fOSC 7/18 ¡ Semiconductor MSM5265 • D/S When this pin is set at high level, the MSM5265 operates in the 1/2 duty dynamic display mode, the MSM5265 operates in the static display mode when this pin is set at low level. • EXT/INT When the external common signal is used, fix this pin at high level and input the external common signal from the OSC-IN pin. The input common signal is used as the internal common signal and is output from the COM-OUT pin through the buffer. When the built-in common signal generator is used, fix this pin at low level. When the MSM5265 is used as an output expander, fix this pin at high level and the OSC-IN pin at low level. The output logic can be reveresed in respect to the input data by setting OSC-IN to "H" level. • COM-OUT When two or more MSM5265s are connected in series (cascade connection), this pin should be connected with all of the slave MSM5265's OSC-IN pins. • SYNC This pin is an input/output pin which is used when two or more MSM5265s are connected in series (cascade connection) in the 1/2 duty dynamic display mode. All of the involved MSM5265's SYNC pins should be connected by the same line and they should be pulled up with a common resistor, which makes a phase level of all involved MSM5265's COM-A and COM-B pins equal. When a single MSM5265 is used in the dynamic display mode, SYNC should be pulled up with a resistor. Connect this pin to GND if any of the following conditions is true: – the MSM5265 is operated in the static display mode – two or more MSM5265 devices are cascade connected – a single MSM5265 device is used – the MSM5265 is used as an output expander • DATA-IN, CLOCK The display data is serially input from the DATA-IN pin to the 160-stage shift register at the rising edge of the CLOCK pulse. The high level of the display data is used to turn the display on, while low level of the display data is used to turn off the display. • DATA-OUT1 The 80th stage of the shift register contents is output from this pin. When two or more MSM5265s are connected in series (cascade connection) in the static display mode, this pin should be connected to the next MSM5265's DATA-IN pin. • DATA-OUT2 The 160th stage of the shift register contents is output from this pin. When two or more MSM5265s are connected in series (cascade connection) in the 1/2 duty dynamic display mode, this pin should be connected to the next MSM5265's DATA-IN pin. • LOAD The signal for latching the shift register contents is input from this pin. When LOAD pin is set at high level, the shift register contents are shifted to the 80 sets of LCD drivers. When this pin is set at low level, the last display data is held which was transfered to the 80 sets of LCD drivers when LOAD pin was set at high level. 8/18 ¡ Semiconductor MSM5265 • VLC2 Supply voltage pin for the 80 sets of LCD drivers. The input level to this pin should be the low level output voltage of segment outputs (SEG1 to SEG80) and common outputs (COM-A, COM-B). In this case, the high level of segment outputs and common outputs is the VDD level, while low level of segment outputs and common outputs is VLC2 level. VLC2 should be set at higher level than ground level. • VLC1 Supply voltage pin for the middle level voltage of the common outputs. The input level of this pin is the middle level output voltage of the common outputs (COM-A, COM-B) in the 1/2 duty dynamic display mode. The value of VLC1 is calculated by the following formula: VLC1 = (VDD + VLC2)/2 In the static display mode, this pin should be open. • COM-A, COM-B LCD driving common signals are output from these pins. These pins should be connected to the common side of the LCD panel. – In the static display mode A pulse in phase with the COM-OUT output is output from both COM-A and COM-B. In this case, the high level is VDD, and the low level is VLC2. – In the 1/2 duty dynamic display mode The COM-A and COM-B output signals are alternately changed within each COM-OUT output cycle, resulting in alternate repetition of select and non-select modes. In the select mode, a signal in phase with the COM-OUT signal is output at "H" (VDD) and "L" (VLC2). In the non-select mode, a voltage is output at "M" (VLC1). In the select mode of COM-A (non-select mode of COM-B), signals that correspond to the 1st- to 80th-bit data of the data latch are output to the segment outputs. In the select mode of COM-B (non-select mode of COM-A), signals that correspond to the 81st- to 160th-bit data of the data latch are output to the segment outputs. Dynamic display mode (D/S : "H") Static display mode (D/S : "L") COM-OUT VDD COM-A VLC1 VLC2 VDD COM-B VLC1 VLC2 9/18 ¡ Semiconductor MSM5265 • SEG1 to SEG80 LCD segment driving signals are output from these pins and they should be connected to the segment side of the LCD panel. "H" level : VDD, "L" level : VLC2 – In the static display mode The nth-bit data of the data latch (A) corresponds to the SEG n. The data of the data latch (B) is invalid . A signal out of phase with the COM-OUT signal is output to the segment outputs when the display is turned on, while a signal in phase with it is output when the display is turned off. – In the 1/2 duty dynamic display mode Output of the SEG n corresponds to as follows. When COM-A is in select mode: nth-bit data of the data latch (A) When COM-B is in select mode: nth-bit data of the data latch (B) When the display is turned on, a signal out of phase with the common signal corresponding to the data is output, while a signal in phase with the common signal is output when the display is turned off. Dynamic display mode (D/S : "H") Static display mode (D/S : "L") COM-A COM-A COM-B COM-B Off Off Off Off Off SEG n Off On Off On SEG n On Off On Off On On 80+n On On On n n 80+n 10/18 ¡ Semiconductor MSM5265 • SEG-TEST This pin is used to test the segment outputs (SEG1 to SEG80). All displays are turned on when this pin is set to high level. The display returns to the condition before the pin was set to high level. When this pin is at high level, the input on the BLANK pin is disabled. • BLANK This pin is also used to test the segment outputs (SEG1 to SEG80). All displays are turned off when this pin is set to high level. The display returns to the condition before the pin was set to high level. When SEG-TEST pin is at high level, the input on this pin is disabled. 11/18 ¡ Semiconductor MSM5265 APPLICATION CIRCUITS 1) Single MSM5265 operation in the static display mode LCD panel 80 segments (static) COM RCOM SEG 1 SEG-TEST From controller BLANK LOAD DATA-IN CLOCK D/S EXT/INT R1 RCOM ≥ 1.5 kW C0 R0 MSM5265 VLC2 SYNC OSC-IN OSC-OUT OSC-OUT SEG 80 COM-A VDD 1 MW 0.01 mF 100 kW 2) Single MSM5265 operation in the 1/2 duty dynamic display mode LCD panel 80 x 2 segments (1/2 duty dynamic) COM-A COM-B VDD RCOM x2 RLC SEG 1 SEG-TEST From controller BLANK LOAD DATA-IN CLOCK D/S MSM5265 SEG 80 VLC1 COM-A COM-B VLC2 RLC SYNC EXT/INT OSC-IN OSC-OUT OSC-OUT R1 C0 R0 VLC2 22 kW VDD RCOM ≥ 1.5 kW, RCOM ≥ RLC 1 MW 0.01 mF 100 kW 12/18 LCD panel COM ¡ Semiconductor (80 x n segments) static 80 RCOM RCOM 80 80 RCOM SEG-TEST COM-A MSM5265 VLC2 MSM5265 VLC2 COM-A COM-A VLC2 BLANK MSM5265 LOAD DATA-IN SYNC D/S DATA-OUT 1 COM-OUT DATA-IN DATA-OUT 1 SYNC D/S EXT/INT OSC-IN VDD VLC2 DATA-IN DATA-OUT 1 CLOCK EXT/INT OSC-IN VDD 3) Cascade connections for MSM5265s in the static display mode D/S EXT/INT SYNC OSC RCOM ≥ 1.5 kW MSM5265 13/18 LCD panel COM-A COM-B ¡ Semiconductor (80 x n segments) 1/2 duty dynamic VDD RLC RLC RCOM VLCI COM-A MSM5265 VLC2 DATA-IN SYNC D/S VDD VDD EXT/INT OSC-IN VDD D/S DATA-OUT 2 DATA-IN COM-B MSM5265 RCOM 80 RCOM RCOM 80 80 RCOM RCOM VLC2 VLCI SEG-TEST COM-A VLCI COM-A COM-B VLC2 DATA-OUT 2 SYNC EXT/INT OSC-IN BLANK MSM5265 LOAD COM-B VLC2 DATA-IN COM-OUT DATA-OUT 2 CLOCK D/S EXT/INT SYNC OSC VDD 4) Cascade connections for MSM5265s in the 1/2 duty dynamic display mode 22kW RCOM≥1.5 kW, RCOM≥RLC MSM5265 14/18 ¡ Semiconductor 5) Output-expander MSM5265 80 outputs (same logic as input data) SEG 1 SEG-TEST From controller BLANK LOAD DATA-IN CLOCK D/S EXT/INT VDD OSC-IN * MSM5265 SEG 80 VLC2 SYNC * The output logic can be reversed with respect to the input data by setting OSC-IN to "H" level. 15/18 ¡ Semiconductor MSM5265 REFERENCE DATA IDD2 vs. VDD mA 300 Condition Oscillating, no load Room temperature I DD2 200 R0=100kW C0=0.01mF R1=1MW 100 0 0 1 2 3 4 5 6 7 V VDD fCOM vs. R0, C0 Hz 320 280 240 200 fCOM 160 140 120 100 80 70 60 50 40 35 30 25 20 175 15 125 10 8.75 7.5 6.25 5 C0=0.001mF C0=0.0022mF C0=0.0047mF C0=0.01mF Condition D/S="L" EXT/INT="L" VDD=5.0V Room temperature R1=10R0 fCOM=1/8fOSC.=1/ (17.6C0R0) . C0=0.022mF C0=0.047mF 120 R0 150 180 220 kW 56 68 82 100 fOSC vs. VDD Hz 460 450 +2% 0% –2% 430 420 410 Condition Room temperature fOSC 440 R0=100kW C0=0.01mF R1=1MW 1 2 3 4 5 6 7 V VDD 16/18 ¡ Semiconductor MSM5265 PACKAGE DIMENSIONS (Unit : mm) QFP100-P-1420-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 17/18 ¡ Semiconductor MSM5265 (Unit : mm) QFP100-P-1420-0.65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.29 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/18