MSM5432128

E2L0045-17-Y1 ¡ Semiconductor ¡ Semiconductor MSM5432126/8 DESCRIPTION This version: Jan. 1998 MSM5432126/8 Previous version: Dec. 1996 Pr el im in ar y 131,072-Word ¥ 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO The MSM5432126/8 is a new generation Graphics DRAM organized in a 131,072-word ¥ 32-bit configuration. The technology used to fabricate the MSM5432126/8 is OKI's CMOS silicon gate process technology. The device operates with a single 5 V power supply. FEATURES • 131,072-word ¥ 32-bit organization • Single 5 V power supply, ± 10% tolerance • Refresh: 512 cycles/8 ms • Fast Page Mode with Extended Data Out (EDO) • Write per bit (MSM5432128 only) • Byte write, Byte read • RAS only refresh • CAS before RAS refresh • Hidden refresh • Package: 64-pin 525 mil plastic SSOP (SSOP64-P-525-0.80-K) (Product : MSM5432126-xxGS-K) (Product : MSM5432128-xxGS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM5432126/8-45 MSM5432126/8-50 MSM5432126/8-60 Access Time (Max.) tRAC tAA tCAC tOEA 45 ns 23 ns 13 ns 13 ns 50 ns 25 ns 15 ns 15 ns 60 ns 30 ns 18 ns 18 ns Cycle Time (Min.) 100 ns 110 ns 130 ns Power Dissipation Operating (Max.) Standby (Max.) 935 mW 907 mW 880 mW 11 mW 1/24 ¡ Semiconductor MSM5432126/8 PIN CONFIGURATION (TOP VIEW) VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 VSS NC NC NC WB* / WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33  10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS DQ31 DQ30 DQ29 DQ28 VCC DQ27 DQ26 DQ25 DQ24 VSS DQ23 DQ22 DQ21 DQ20 VCC DQ19 DQ18 DQ17 DQ16 VSS CAS1 CAS2 CAS3 CAS4 OE A8 A7 A6 A5 A4 VSS 64-Pin Plastic SSOP Pin Name A0 - A8 DQ0 - DQ31 RAS CAS1 - CAS4 WB* / WE OE VCC VSS NC Function Address Input Data Input / Data Output Row Address Strobe Column Address Strobe Write Per Bit* / Write Enable Output Enable Power Supply (5 V) Ground (0 V) No Connection Note: *: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. MSM5432128 only 2/24 ¡ Semiconductor BLOCK DIAGRAM RAS CAS1 CAS2 CAS3 CAS4 Timing Generator WB / WE I/O Controller I/O Controller I/O Controller I/O Controller OE 8 Output Buffers 8 DQ0 - DQ7 8 Input Buffers 8 8 Output Buffers 8 DQ8 - DQ15 Column 8 Address Buffers Internal Address Counter Row 9 Address Buffers 8 Column Decoders 8 I/O Selector 32 Input Buffers 8 A0 - A8 Refresh Control Clock Sense Amps 32 8 9 Row Decoders Word Drivers Memory Cells 8 Input Buffers 8 DQ16 - DQ23 Output Buffers 8 VCC On-chip VBB Generator VSS 8 Input Buffers MSM5432126/8 8 DQ24 - DQ31 8 Output Buffers 8 3/24 ¡ Semiconductor MSM5432126/8 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Rating –0.5 to 7.0 50 1 0 to 70 –55 to 150 Unit V mA W °C °C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 3.0 –0.3 Typ. 5.0 0 — — Max. 5.5 0 (Ta = 0°C to 70°C) Unit V V V V VCC + 1.0 0.3 Capacitance Parameter Input Capacitance Input / Output Capacitance Symbol CIN CIO Typ. — — (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Max. 8 9 Unit pF pF 4/24 ¡ Semiconductor DC Characteristics MSM5432126/8 (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol Condition IOH = –0.1 mA IOL = 0.1 mA 0 V < VIN < VCC; All other pins not under test = 0 V 0 V < VOUT < 5.5 V Output Disable RAS, CAS cycling, tRC = Min. RAS ≥ VCC – 0.2 V, CAS ≥ VCC – 0.2 V RAS = cycling, CAS = VIH, tRC = Min. RAS = VIL, CAS cycling, tHPC = Min. RAS = cycling, CAS before RAS MSM5432126/8 MSM5432126/8 MSM5432126/8 Unit Note -45 -50 -60 VOH VOL ILI Min. Max. Min. Max. Min. Max. VCC VCC 2.0 2.0 2.0 VCC 0 –10 0.8 10 0 –10 0.8 10 0 –10 0.8 10 V V mA Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS Only Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (CAS before RAS Refresh) ILO –10 10 –10 10 –10 10 mA ICC1 — 150 — 140 — 130 mA 1, 2, 3 ICC2 — 2 — 2 — 2 mA ICC3 — 150 — 140 — 130 mA 1, 2, 3 ICC4 — 170 — 165 — 160 mA 1, 2, 4 ICC5 — 150 — 140 — 130 mA 1, 2, 4 Notes: 1. Specified values are obtained with minimum cycle time. 2. ICC is dependent on output loading. Specified values are obtained with the output open. 3. Address can be changed once or less while RAS = VIL. 4. Address can be changed once or less while CAS = VIH. 5/24 ¡ Semiconductor AC Characteristics (1/2) MSM5432126/8 (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Fast Page Mode Cycle Time Fast Page Mode Read-Modify-Write Cycle Time Access Time from RAS Access Time from Column Address Access Time from CAS Access Time from CAS Precharge Output Buffer Turn-off Delay Time from RAS Output Buffer Turn-off Delay Time from CAS Transition Time (Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Hyper Page Mode Only) RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time Column Address to RAS Lead Time CAS to RAS Precharge Time CAS Precharge Time (Hyper Page Mode) Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time referenced to RAS Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS CAS "H" to RAS "H" Lead Time RAS "H" to CAS "H" Lead Time Data Output Hold after CAS Low Write Command Set-up Time Write Command Hold Time Symbol MSM5432126/8 MSM5432126/8 MSM5432126/8 -45 -50 -60 Unit Note Min. tRC tRWC tHPC tPRWC tRAC tAA tCAC tCPA tREZ tCEZ tT tRP tRAS tRASP tRSH tCSH tCAS tRCD tRAD tRAL tCRP tCP tASR tRAH tASC tCAH tAR tRCS tRCH tRRH tCRL tRCL tDOH tWCS tWCH 100 135 20 65 — — — — 3 3 3 49 45 45 12 45 7 20 15 22 6 7 0 6 0 7 30 0 0 0 0 0 3 0 7 Max. — — — — 45 23 13 28 20 20 35 — 10k 100k — — 10k 32 22 — — — — — — — — — — — — — — — — Min. 110 145 22 70 — — — — 3 3 3 54 50 50 14 50 8 20 15 24 6 8 0 7 0 8 35 0 0 0 0 0 3 0 8 Max. — — — — 50 25 15 30 20 20 35 — 10k 100k — — 10k 35 25 — — — — — — — — — — — — — — — — Min. 130 170 24 80 — — — — 3 3 3 64 60 60 14 60 9 20 15 28 8 9 0 9 0 10 40 0 0 0 0 0 3 0 10 Max. — — — — 60 30 18 35 20 20 35 — 10k 100k — — 10k 42 30 — — — — — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 8, 12 12 12 6, 12 6 12 12 13 15 9 10 4, 9,10 4, 10 4, 9 4, 13 5 5 3 6/24 ¡ Semiconductor AC Characteristics (2/2) MSM5432126/8 (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM5432126/8 MSM5432126/8 MSM5432126/8 -45 -50 -60 Unit Note Min. Write Command Hold Time referenced to RAS tWCR Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Output Buffer Turn-off Delay Time from WE Data Set-up Time Data Hold Time Data Hold Time referenced to RAS OE to Data-in Delay Time RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Data to CAS Delay Time Data to OE Delay Time Access Time from OE Output Buffer Turn-off Delay Time from OE OE Command Hold Time RAS Hold Time referenced to OE OE "L" to CAS "H" Lead Time CAS "H" to OE "L" Lead Time High-Z Command Pulse Width WB/WE Pulse Width (Output Disable) CAS Set-up Time for CAS before RAS Cycle CAS Hold Time for CAS before RAS Cycle RAS Precharge to CAS Active Time CAS Precharge Time (Refresh Counter Test) Refresh Period WB Set-up Time WB Hold Time Write-Per-Bit Mask Data Set-up Time Write-Per-Bit Mask Data Hold Time tWP tRWL tCWL tWEZ tDS tDH tDHR tOED tRWD tAWD tCWD tDZC tDZO tOEA tOEZ tOEH tROH tOCH tCHO tOEP tWPE tCSR tCHR tRPC tCPT tREF tWSR tRWH tMS tMH 30 8 8 8 3 0 7 30 12 65 42 32 0 0 — 3 8 10 10 10 10 10 6 6 10 20 — 0 6 0 7 Max. — — — — 20 — — — — — — — — — 13 20 — — — — — — — — — — 8 — — — — Min. 35 9 9 9 3 0 8 35 12 70 45 35 0 0 — 3 9 10 10 10 10 10 8 8 10 25 — 0 7 0 8 Max. — — — — 20 — — — — — — — — — 15 20 — — — — — — — — — — 8 — — — — Min. 40 10 10 10 3 0 10 40 12 80 50 40 0 0 — 3 10 12 10 10 12 12 10 10 10 30 — 0 8 0 10 Max. — — — — 20 — — — — — — — — — 18 20 — — — — — — — — — — 8 — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 16 16 16 16 12 13 12 15 5 8 8 8 14 5 7, 12 7, 12 7/24 ¡ Semiconductor Notes: MSM5432126/8 1. An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles (Example : RAS only refresh) before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS before RAS cycles instead of 8 RAS cycles are required. 2. The AC characteristics assume at tT = 3 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. Input levels at the AC testing are 3.0 V/0 V. 4. Data outputs are measured with a load of 30 pF. DOUT reference levels : VOH/VOL = 2.0 V/0.8 V. 5. tREZ (Max.), tCEZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. This parameter is sampled and not 100% tested. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to CAS leading edge of early write cycles and to WE leading edge in OE controlled write cycles and read modify write cycles. 8. tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), the cycle is an early write cycle and the data out pin will remain open circuit throughout the entire cycle; If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.), the cycle is a read modify write cycle and the data out will contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out is indeterminate. 9. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 11. This is guaranteed by design. (tDOH = tCAC - output transition time) This parameter is not 100% tested. 12. These parameters are determined by the earliest falling edge of CAS1, CAS2, CAS3, or CAS4. 13. These parameters are determined by the latest rising edge of CAS1, CAS2, CAS3, or CAS4. 14. tCWL should be satisfied by all CASes. 15. tCP and tCPT are determined by the time that all CASes are high. 16. Only MSM5432128. 8/24 ¡ Semiconductor CASn-DQ FUNCTION TABLE CAS1 H H H H H H H H L L L L L L L L CAS2 H H H H L L L L H H H H L L L L CAS3 H H L L H H L L H H L L H H L L CAS4 H L H L H L H L H L H L H L H L DQ0-7 * * * * * * * * Enable Enable Enable Enable Enable Enable Enable Enable Enable Read cycle Write cycle Valid Data-out Write Data MSM5432126/8 DQ8-15 * * * * Enable Enable Enable Enable * * * * Enable Enable Enable Enable * High-Z Don't Care DQ16-23 * * Enable Enable * * Enable Enable * * Enable Enable * * Enable Enable DQ24-31 * Enable * Enable * Enable * Enable * Enable * Enable * Enable * Enable WRITE CYCLE FUNCTION TABLE RAS falling edge CODE RWM (*1) RW A WB / WE L H (*2) B DQ Write mask Don't care CAS or WB / WE falling edge C DQ Write data Write data Write per bit Normal write Function Write mask : 'L' = Mask, 'H' = No mask (*1): MSM5432128 only. (*2): In case of MSM5432126, don't care. 9/24 ¡ Semiconductor TIMING WAVEFORM Read Cycle (Outputs Controlled by RAS) RAS CAS1 | CAS4 Address WB / WE OE DQ0 - DQ31  ,,
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,        MSM5432126/8 tRC tRAS tRP tCRP tCSH tCRP tRCD tRSH tCAS tASR tRAD tRAH tASC tCRL tCAH tRAL Row Column tAR tRRH tRCS tRCH tROH tOEA tCAC tAA tOEZ tREZ Open tRAC Valid Data-out "H" or "L" 10/24 ¡ Semiconductor Read Cycle (Outputs Controlled by CAS) RAS CAS1 | CAS4 Address WB / WE OE DQ0 - DQ31  ,,
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,        MSM5432126/8 tRC tRAS tRP tCRP tCSH tCRP tRCD tRSH tCAS tASR tRAD tRAH tASC tCAH tRAL tRCL Row Column tAR tRCH tRCS tRRH tROH tOEA tCAC tAA tOEZ tCEZ Open Valid Data-out tRAC "H" or "L" 11/24 ¡ Semiconductor Write Cycle (Early Write) tRC tRAS RAS tCRP tAR tCSH CAS1 | CAS4 tRCD tRSH tCAS tRP MSM5432126/8 Address WB / WE OE DQ0 - DQ31    


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    tRAD tRAL tASR tRAH tASC tCAH Row Column tWSR tRWH tCWL tRWL A tWP tWCS tWCH tWCR tMS tMH tDS tDH B C tDHR "H" or "L" 12/24 ¡ Semiconductor Write Cycle (OE Control Write) tRC tRAS RAS tAR tCSH tRP MSM5432126/8 CAS1 | CAS4 Address WB / WE OE DQ0 - DQ31   


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,,      tCRP tRCD tRSH tCAS tRAL tASR tRAD tRAH tASC tCAH Row Column tWSR tRWH tRCS tCWL tRWL A tWP tWCR tOEH tOED tDHR tMS tMH tDS tDH B C "H" or "L" 13/24 ¡ Semiconductor Read Modify Write Cycle tRWC tRAS RAS tAR tRP MSM5432126/8 CAS1 | CAS4 Address WB / WE OE DQ0 - DQ31   ,  
,,        tCSH tCRP tRCD tRSH tCAS tRAD tRAL tASR tRAH tASC tCAH Row Column tCWL tWSR tRWH tRCS tCWD tRWL A tWP tAWD tRWD tOEA tOEH tDZO tMS tMH tAA tOEZ tOED tDS tDH B tRAC tDZC tCAC OUT C "H" or "L" 14/24 ¡ Semiconductor Fast Page Mode Read Cycle with EDO RAS CAS1 | CAS4 Address WB / WE OE DQ0 - DQ31 

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 MSM5432126/8 tRC tRASP tRP tAR tCSH tHPC tRSH tCRP tRCD tCP tCP tCRP tCAS tCAS tCAS tRAD tRAL tASR tRAH tASC tCAH Column tASC tCAH tASC tCAH Row Column Column tRCS tRCH tRCS tRCH tRCS tRCH tRRH tOEA tCAC tCAC tCAC tREZ tAA tDOH tDOH tOEZ Open Valid Data-out Valid Data-out Valid Data-out tRAC tAA tCPA tAA tCPA "H" or "L" 15/24 ¡ Semiconductor Fast Page Mode Write Cycle (Early Write) tRC tRASP RAS tCRP CAS1 | CAS4 tRCD tCAS tRAD tAR tCSH tCP tHPC tCAS tCP tRSH MSM5432126/8 tRP tCRP tCAS tRAL tCAH Address WB / WE OE DQ0 - DQ31  
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   tASR tRAH Row tASC tCAH tASC tCAH tASC Column Column Column tCWL tCWL tCWL tWSR tRWH tWCS A tWCH tWP tWCS tWCH tWP tWCS tWCH tWP tWCR tRWL tDHR tMS tMH B tDS tDH tDS tDH C tDS tDH C C "H" or "L" 16/24 ¡ Semiconductor Fast Page Mode Read Modify Write Cycle tRC tRASP RAS tCRP CAS1 | CAS4 tRCD tCAS tAR tCSH tCP tPRWC tCAS tCP tRSH MSM5432126/8 tRP tCRP tCAS Address WB / WE DQ0 - DQ31   ,,
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  ,,   tRAD tASR tRAH Row tASC tCAH tASC tCAH tASC tRAL tCAH Column Column Column tWSR tRWH tRCS A tCWD tCWL tCWD tCWL tCWD tRWL tCWL tRWD tAWD tOEA tWP tAWD tOEA tWP tAWD tOEA tWP tROH tOEH OE tOED tAA tOEZ tAA tMS tMH B tDS tDH tDS tOED tAA tOEZ tDH C tOED tOEZ tDS tDH OUT C OUT OUT C tCAC tCAC tCAC tRAC "H" or "L" 17/24 ¡ Semiconductor RAS Only Refresh Cycle RAS CAS1 | CAS4 Address 


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    MSM5432126/8 tRC tRAS tRP tRPC tCRP tASR tRAH Row Note: DQs are open, WB / WE, OE = "H" or "L" "H" or "L" 18/24 ¡ Semiconductor CAS before RAS Refresh Cycle tRC tRP RAS tRPC tCP CASn tCSR tCHR tRAS MSM5432126/8 tRP tCEZ DQ0 - DQ31 Open Note: WB / WE, OE, A0 - A8 = "H" or "L" 19/24 ,,,


    ,    ¡ Semiconductor MSM5432126/8 Hidden Refresh Read Cycle tRC tRAS tRP tRC tRAS tRP RAS tCRP tRCD tRSH tCHR CAS1 | CAS4 tASR tRAD tRAH tASC tRAL tCAH Address Row Column tAR tRCS tRRH WB / WE tROH OE tOEA tCAC tOEZ tREZ DQ0 - DQ31 Valid Data-out tAA tRAC "H" or "L" 20/24 ¡ Semiconductor Hidden Refresh Write Cycle tRC tRAS tRP tRC tRAS MSM5432126/8 tRP 
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,,         RAS tCRP tRCD tRSH tCHR CAS1 | CAS4 tASR tRAH tRAD tASC tRAL tCAH Address Row Column tAR tWSR tRWH tWCS tWCH WB / WE A tWP tRWL tWCR OE tMS tMH tDS tDH DQ0 - DQ31 B C tDHR "H" or "L" 21/24 ¡ Semiconductor CAS before RAS Refresh Counter Test Cycle MSM5432126/8  




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    ,   tRAS tRP RAS CAS1 | CAS4 tCSR tCHR tCPT tRSH tCAS tASC tCAH Address Column tRAL Read Cycle WB / WE OE tRCS tCAC tRRH tRCH tAA tROH tOEA tAA tOEZ tCEZ DQ0 - DQ31 Open Valid Data-out Write Cycle WB / WE tRWL tCWL tWCS tWCH tWP OE tDS tDH DQ0 - DQ31 Open Valid Data-in Read Modify Write Cycle WB / WE tRCS tAWD tCWD tRWL tCWL tWP tOEA OE tAA tCAC tOEZ tOED tDS tDH DQ0 - DQ31 Open Valid Data-out Valid Data-in "H" or "L" 22/24 ¡ Semiconductor Fast Page Mode Read with EDO High-Z Operation tRC tRASP RAS tCRP CAS1 | CAS4 tAR tCSH tRCD tCAS tCP tCAS tHPC tCP tCAS tCP tCAS tRSH tCRP tRP  
,     tRAD tRAL tASR tRAH Row tASC tCAH tASC tCAH Column tASC tCAH Column tASC tCAH Column Address Column tRRH tRCS tRCH tRCS tRCH WB / WE tRAC tCHO tOCH tWPE tOEA tCAC tOEP tOEP OE tAA tCAC tCAC tCPA tAA tCAC tAA tDOH tOEZ tOEA tOEZ tOEA tWEZ tAA tREZ DQ0 - DQ31 Open Valid Data-out Valid Data-out Valid* Data-out Valid* Data-out Valid Data-out MSM5432126/8 * : Same Data "H" or "L" 23/24 ¡ Semiconductor MSM5432126/8 PACKAGE DIMENSIONS (Unit : mm) SSOP64-P-525-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.34 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/24