MSM56V16800F

Semiconductor MSM56V16800F 2-Bank ´ 1,048,576 Word ´ 8 Bit SYNCHRONOUS DYNAMIC RAM This version : Dec.1999 DESCRIPTION The MSM56V16800F is a 2-Bank ´ 1,048,576-word ´ 8 bit Synchronous dynamic RAM, fabricated in OKI’s CMOS silicon-gate process technology. The device operates at 3.3V. The inputs and outputs are LVTTL compatible. FEATURES · · · · · · · Silicon gate , quadruple polysilicon CMOS , 1-transistor memory cell 2-bank ´ 1,048,576-word ´ 8bit configuration 3.3V power supply ± 0.3V tolerance Input Output Refresh : LVTTL compatible : LVTTL compatible : 4096 cycles/64 ms Programmable data transfer mode - CAS Latency (1,2,3) - Burst Length (1,2,4,8,Full page) - Data scramble (sequential , interleave) · · CBR auto-refresh, Self-refresh capability Package: 44-pin 400mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM56V16800F-xxTS-K) xx : indicates speed rank. PRODUCT FAMILY Family MSM56V16800F-8A MSM56V16800F-8 MSM56V16800F-10 Max. Frequency 125MHz 125MHz 100MHz Access Time (Max.) tAC2 6ns 9ns 9ns tAC3 6ns 6ns 9ns 1/30 MSM56V16800F PIN CONFIGRATION (TOP VIEW) VCC 1 DQ1 2 VSS(Q) 3 DQ2 4 VCC(Q) 5 DQ3 6 VSS(Q) 7 DQ4 8 VCC(Q) 9 NC 10 NC 11 WE 12 CAS 13 RAS 14 CS 15 A11 16 A10 17 A0 18 A1 19 A2 20 A3 21 VCC 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DQ8 VSS(Q) DQ7 VCC(Q) DQ6 VSS(Q) DQ5 VCC(Q) NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS 44-Pin Plastic TSOP (II) (K Type) Pin Name CLK CS CKE A0–A10 A11 RAS CAS WE Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Pin Name DQM DQi VCC VSS VCCQ VSSQ NC Function Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground (0V) Data Output Power Supply (3.3V) Data Output Ground (0V) No Connection Note: The same power supply voltage must be provided to every VCC pin and VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 2/30 MSM56V16800F PIN DESCRIPTION CLK CS Fetches all inputs at the “H” edge. Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE, UDQM and LDQM. Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. Row & column multiplexed. Row address : RA0 – RA10 Column Address : CA0 – CA8 Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. A11=”L” : Bank A, A11=”H” : Bank B Functionality depends on the combination. For details, see the function truth table. Masks the read data of two clocks later when DQM is set “H” at the “H” edge of the clock signal. Masks the write data of the same clock when DQM is set “H” at the “H” edge of the clock signal. Data inputs/outputs are multiplexed on the same pin. CKE Address A11 RAS CAS WE DQM DQi 3/30 MSM56V16800F BLOCK DIAGRAM CKE CLK CS RAS CAS WE DQM Programing Register Latency & Burst Controller I/O Controller Timing Register Bank Controller A11 Internal Col. Address Counter A0 - A11 Input Data Register 8 98 Column Address Buffers 9 Column Decoders Input Buffers 8 Sense Amplifiers Internal Row Address Counter 8 Read Data Register 8 Output Buffers 8 DQ1 - DQ8 Row Decoders Word Drivers 8Mb Memory Cells 12 Row Address Buffers 12 Row Decoders Word Drivers 8Mb Memory Cells Sense Amplifiers Column Decoders 4/30 MSM56V16800F ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (Voltages referenced to VSS) Parameter Voltage on Any Pin Relative to VSS VCC Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Operating Temperature Symbol VIN, VOUT VCC, VCCQ Tstg PD* IOS Topr *: Ta = 25°C Rating -0.5 to VCC + 0.5 -0.5 to 4.6 -55 to 150 600 50 0 to 70 Unit V V °C mW mA °C Recommended Operating Conditions (Voltages referenced to VSS = 0V) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC, VCCQ VIH VIL Min. 3.0 2.0 -0.3 Typ. 3.3 ¾ ¾ Max. 3.6 VCC + 0.2 0.8 Unit V V V Capacitance (VCC = 1.4V, Ta = 25°C, f=1MHz) Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, WE, CS, CKE, DQM, A0-A11) Input/Output Capacitance (DQ1-DQ8) Symbol CCLK CIN COUT Min. 2.5 2.5 4 Max. 4 5 6.5 Unit pF pF pF 5/30 MSM56V16800F DC Characteristics Condition Parameter Output High Voltage Output Low Voltage Input Leakage Current Input Leakage Current Symbol Bank VOH VOL ILI ILO ¾ ¾ ¾ ¾ One Bank Active CKE ¾ ¾ ¾ ¾ Others MSM56V16800F 8A 8 10 Unit Note Min Max Min Max Min Max ¾ 0.4 10 10 2.4 ¾ -10 -10 ¾ 0.4 10 10 2.4 ¾ -10 -10 ¾ 0.4 10 10 V V µA µA IOH = -2.0mA 2.4 IOL = 2.0mA ¾ ¾ ¾ -10 -10 ICC1 Average power supply current (Operating) tCC=min. CKE³VIH tRC=min. No Burst ¾ 70 ¾ 70 ¾ 60 mA 1,2 tCC=min. t =min. Both Banks ICC1D CKE³VIH RC Active tRRD=min. No Burst ICC2 Both Banks CKE³VIH tCC=min. Precharge ¾ 105 ¾ 105 ¾ 85 mA 1,2 Power supply current (Standby) ¾ 35 ¾ 35 ¾ 30 mA 3 Average power supply current ICC3S Both Banks CKE£VIL tCC=min. Active (Clock Suspension) Average power supply current (Active Standby ) Power supply current (Burst) Power supply current (Auto-Refresh) Average power supply current (Self-Refresh) Average power supply current (Power Down) ICC3 One Bank Active CKE³VIH tCC=min. ¾ 3 ¾ 3 ¾ 3 mA 2 ¾ 40 ¾ 40 ¾ 35 mA 3 ICC4 Both Banks CKE³VIH tCC=min. Active One Bank Active t =min. CKE³VIH CC tRC=min. ¾ 95 ¾ 90 ¾ 80 mA 1,2 ICC5 ¾ 70 ¾ 70 ¾ 60 mA 2 ICC6 Both Banks CKE£VIL tCC=min. Precharge Both Banks CKE£VIL tCC=min. Precharge ¾ 2 ¾ 2 ¾ 2 mA ICC7 ¾ 2 ¾ 2 ¾ 2 mA Notes: 1. 2. 3. Measured with outputs open. The address and data can be changed once or left unchanged during one cycle. The address and data can be changed once or left unchanged during two cycles. 6/30 MSM56V16800F Mode Set Address Keys CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CL Reserved 1 2 3 Reserved Reserved Reserved Reserved Burst Type A3 0 1 BT Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Burst Length A0 0 1 0 1 0 1 0 1 BT = 0 1 2 4 8 Reserved Reserved Reserved Full Page BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Notes: A7, A8, A9, A10 and A11 should stay “L” during mode set cycle. POWER ON SEQUENCE 1. 2. 3. 4. 5. With inputs in NOP state, turn on the power supply and start the system clock. After the VCC voltage has reached the specified level, pause for 200ms or more with the input kept in NOP state. Issue the precharge all bank command. Apply a CBR auto-refresh eight or more times. Enter the mode register setting command. 7/30 MSM56V16800F AC Characteristic (1/2) Note 1,2 MSM56V16800F Parameter Symbol Min. CL = 3 Clock Cycles Time CL = 2 CL = 1 CL = 3 Access Time from Clock CL = 2 CL = 1 Clock High Pulse Time Clock Low Pulse Time Input Setup Time Input Hold Time Output Low Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock RAS Cycle Time RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Refresh Time Power-down Exit setup Time Input Level Transition Time CAS to CAS Delay Time(Min.) Clock Disable Time from CKE Data Output High Impedance Time from UDQM, LDQM Data Input Mask Time from UDQM, LDQM Data Input Mask Time from Write Command tCH tCL tSI tHI tOLZ tOHZ tOH tRC tRP tRAS tRCD tWR tRRD tREF tPDE tT lCCD lCKE lDOZ lDOD lDWD tAC tCC 8 10 20 ¾ ¾ ¾ 3 3 2 1 3 ¾ 3 70 20 48 20 8 20 ¾ tSI +1CLK ¾ 1 1 2 0 0 8A Max. ¾ ¾ ¾ 6 6 16 ¾ ¾ ¾ ¾ ¾ 9 ¾ ¾ ¾ 10 5 8 Min. 8 12 24 ¾ ¾ ¾ 3 3 2 1 3 ¾ 3 70 20 48 20 8 20 ¾ tSI +1CLK ¾ 1 1 2 0 0 Max. ¾ ¾ ¾ 6 9 22 ¾ ¾ ¾ ¾ ¾ 9 ¾ ¾ ¾ 10 5 10 Min. 10 15 30 ¾ ¾ ¾ 3 3 3 1 3 ¾ 3 90 30 60 30 15 20 ¾ tSI +1CLK ¾ 1 1 2 0 0 8 ¾ ¾ ¾ 10 5 Unit Max. ¾ ¾ ¾ 9 9 27 ¾ ¾ ¾ ¾ ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Cycle Cycle Cycle Cycle Cycle Note 3,4 3,4 3,4 4 4 3 ¾ ¾ ¾ 64 ¾ 3 ¾ ¾ ¾ 64 ¾ 3 ¾ ¾ ¾ 64 ¾ 3 8/30 MSM56V16800F AC Characteristic (2/2) Note 1,2 MSM56V16800F Parameter Symbol Min. Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Set Command Input (Min.) Write Command Input Time from Output lROH lMRD lOWD CL 3 8A Max Min. CL 3 8 Max. Min. CL 3 10 Max. Cycle Cycle Unit Note 2 2 2 Cycle Notes: 1) 2) 3) AC measurements assume that tT = 1ns. The reference level for timing of input signals is 1.4V. Output load. Z=50W Output 50pF (External Load) 4) 5) The access time is defined at 1.5V. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL. 9/30 MSM56V16800F TIMING WAVEFORM · Read & Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tRC CKE CS tRP RAS tRCD CAS ADDR Ra C a0 Rb C b0 A11 A10 Ra Rb tOH DQ Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 tAC WE tOHZ tWR DQM Row Active Read Command Precharge Command Row Active Write Command Precharge Command 10/30 MSM56V16800F · Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=2, Burst Length=4 tCH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tCC CKE tCL High CS tHI RAS tSI tSI CAS tHI ICCD tSI ADDR Ra tSI Ca tSI Cb Cc tHI A11 BS BS tHI BS BS BS A10 Ra tAC DQ Qa tOHZ Db tHI Qc tOLZ tOH lOWD WE tSI tHI tSI DQM Row Active Read Command Write Command Precharge Command Read Command 11/30 MSM56V16800F *Notes : 1. When CS is set ”High” at a clock transition from “Low” to ”High”, all inputs except CKE, UDQM and LDQM are invalid. 2. When issuing an active, read or write command, the bank is selected by A11. A11 0 1 Active, read or write Bank A Bank B 3. The auto precharge function is enabled or disabled by the A10 input when the read or write command is issued. A10 0 1 0 1 A11 0 0 1 1 Operation After the end of burst, bank A holds the idle status. After the end of burst, bank A is precharged automatically. After the end of burst, bank B holds the idle status. After the end of burst, bank B is precharged automatically. 4. When issuing a precharge command, the bank to be precharged is selected by the A10 and A11 inputs. A10 0 0 1 A11 0 1 X Operation Bank A is precharged. Bank B is precharged. Both banks A and B are precharged. 5. The input data and the write command are latched by the same clock (Write latency = 0). 6. The output is forced to high impedance by (1CLK+tOHZ) after UDQM, LDQM entry. 12/30 MSM56V16800F · Page Read & Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS Bank A Active RAS CAS ICCD ADDR C a0 C b0 C c0 C d0 A11 A10 DQ Q a0 Q a1 Q b0 Q b1 D c0 D c1 D d0 lOWD WE *Note 1 tWR *Note 2 DQM Read Command Read Command Write Command Precharge Command Write Command *Notes: 1. To write data before a burst read ends, DQM should be asserted three cycles prior to the write command to avoid bus contention. 2. To assert row precharge before a burst write ends, wait tWR after the last write data input. Input data during the precharge input cycle will be masked internally. 13/30 MSM56V16800F · Read & Write Cycle with Auto Precharge @ Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS tRRD CAS ADDR Ra Rb Ca Cb A11 A10 Ra Rb WE CAS Latency=1 DQ Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 A-Bank Precharge Start DQM CAS Latency=2 DQ Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 A-Bank Precharge Start DQM CAS Latency=3 DQ Q a0 Q a1 Q a2 Q a3 D b0 D b1 D b2 D b3 A-Bank Precharge Start tWR DQM Row Active (A-Bank) Row Active (B-Bank) A Bank Read with Auto Precharge B Bank Write with Auto Precharge B Bank Precharge Start Point 14/30 MSM56V16800F x Bank Interleave Random Row Read Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS tRC RAS tRRD CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb1 Q Bb2 Q Bb3 Q Bb4 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE DQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Row Active (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 15/30 MSM56V16800F x Bank Interleave Random Row Write Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac DQ D Aa0 D Aa1 D Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 D Ac0 D Ac1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write Command (A-Bank) Precharge Command Write Command (A-Bank) (B-Bank) Row Active (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank) Precharge Command (B-Bank) 16/30 MSM56V16800F x Bank Interleave Page Read Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE *Note 1 High CS RAS CAS ADDR R Aa C Aa R Bb C Bb C Ac C Bd C Ae A11 A10 R Aa R Bb DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Bd0 Q Bd1 Q Ae0 Q Ae1 IROH WE DQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Read Command (A-Bank) Precharge Command (A-Bank) Note: 1. CS is ignored when RAS, CAS and WE are high at the same cycle. 17/30 MSM56V16800F · Bank Interleave Page Write Cycle @CAS Latency = 2, Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR R Aa C Aa R Bb C Bb C Ac C Bd A11 A10 R Aa R Ab DQ D Aa0 D Aa1 D Aa2 D Aa3 D Bb0 D Bb1 D Bb2 D Bb3 D Ac0 D Ac1 D Bd0 WE DQM Row Active Row Active (A-Bank) Write Command (B-Bank) Write Command (B-Bank) (A-Bank) Write Command Write Command (B-Bank) Precharge Command (A-Bank) (Both Bank) 18/30 MSM56V16800F · Bank Interleave Random Row Read/Write Cycle @CAS Latency = 2, Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR R Aa C Aa R Bb C Bb R Ac C Ac A11 A10 R Aa R Bb R Ac DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 Q Bb0 Q Bb1 Q Bb2 Q Bb3 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE DQM Row Active (A-Bank) Read Command (A-Bank) Row Active (B-Bank) Precharge Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) Row Active (A-Bank) 19/30 MSM56V16800F · Bank Interleave Page Read/Write Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR C Aa0 C Bb0 C Ac0 A11 A10 DQ Q Aa0 Q Aa1 Q Aa2 Q Aa3 D Bb0 D Bb1 D Bb2 D Bb3 Q Ac0 Q Ac1 Q Ac2 Q Ac3 WE DQM Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank) 20/30 MSM56V16800F · Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK *Note 1 *Note 1 CKE CS RAS CAS ADDR Ra Ca Cb Cc A11 A10 Ra DQ1-8 Q a0 Q a1 *Note 2 Q a2 Q b0 Q b1 D c0 *Note 3 D c2 tOHZ tOHZ WE DQM Row Active Read Command Read DQM CLOCK Suspension Read Command Read DQM Write DQM Write Command CLOCK Suspension Write DQM *Notes: 1. When Clock Suspension is asserted, the next clock cycle is ignored. 2. When DQM are asserted, the read data after two clock cycles is masked. 3. When DQM are asserted, the write data in the same clock cycle is masked. 21/30 MSM56V16800F · Read to Write Cycle (Same Bank) @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE CS *Note 1 RAS tRCD CAS ADDR Ra C a0 C b0 A11 A10 Ra DQ D a0 D b0 D b1 D b2 D b3 tWR WE DQM Row Active Read Command Write Command Precharge Command *Note: 1. In Case CAS latency is 3, READ can be interrupted by WRITE. The minimum command interval is [burst length + 1] cycles. DQM must be high at least 3 clocks prior to the write command. 22/30 MSM56V16800F x Read Interruption by Precharge Command @Burst Length =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK High CKE CS RAS CAS ADDR Ra Ca A11 A10 Ra WE CAS Latency=1 DQ Q a0 Q a1 Q a2 Q a3 Q a4 óNote 1 Q a5 lROH DQM CAS Latency=2 DQ Q a0 Q a1 Q a2 Q a3 Q a4 óNote 2 Q a5 lROH DQM CAS Latency=3 DQ Q a0 Q a1 Q a2 Q a3 óNote 3 Q a4 Q a5 lROH DQM Row Active Read Command Precharge Command óNotes: 1. 2. 3. When the CAS latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. When the CAS latency = 2, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. When the CAS latency = 3, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 56263 MSM56V16800F x Burst Stop Command @Burst Length =8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK CKE High CS RAS CAS ADDR Ca Cb A11 A10 WE CAS Latency=1 DQ Q a0 Q a1 Q a2 Q a3 Q a4 Q b0 Q b1 Q b2 Q b3 Q b4 DQM CAS Latency=2 DQ Q a0 Q a1 Q a2 Q a3 Q a4 Q b0 Q b1 Q b2 Q b3 Q b4 DQM CAS Latency=3 DQ Q a0 Q a1 Q a2 Q a3 Q a4 Q b0 Q b1 Q b2 Q b3 Q b4 DQM Read Command Burst Stop Command Write Command Burst Stop Command 57263 MSM56V16800F x Power Down Mode @CAS Latency = 2, Burst Length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLK tSI CKE tPDE óNote 2 óNote 1 tSI tSI tREF (min.) CS RAS CAS ADDR Ra Ca A11 A10 Ra DQ WE Q a0 Q a1 Q a2 DQM Power-down Entry Power-down Exit Row Active Clock Suspension Entry Read Command Clock Suspension Exit Precharge Command óNotes: 1. When both banks are in precharge state, and if CKE is set low, then the MSM56V16800F enters power-down mode and maintains the mode while CKE is low. 2. To release the circuit from power-down mode, CKE has to be set high for longer than t PDE (tSI + 1CLK). 58263 MSM56V16800F x Self Refresh Cycle 0 1 2 CLK tRC CKE tSI CS RAS CAS ADDR Ra A11 BS A10 Ra DQ WE Hi - Z DQM Self Refresh Entry Self Refresh Exit Row Active 59263 MSM56V16800F x Mode Register Set Cycle 0 1 2 3 4 5 6 x 0 Auto Refresh Cycle 1 2 3 4 5 6 7 8 9 10 11 CLK CKE High High CS lMRD RAS tRC CAS ADDR DQ Key Ra Hi - Z Hi - Z WE DQM MRS New Command Auto Refresh Auto Refresh 5:263 MSM56V16800F FUNCTION TRUTH TABLE (Table 1) (1/2) Current State Idle 1 CS H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L H L L L L L L RAS X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L X H H H H L L CAS X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H L X H H L L H L WE X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L X X X H L H L X X BA X X BA BA BA BA X L X X BA BA BA BA X X X X BA BA BA BA X X X X BA BA BA BA X X X BA BA X BA X X X BA BA X BA X ADDR X X X CA RA A10 X OP Code X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 CA, A10 RA A10 X X X X CA, A10 X RA, A10 X X X X CA, A10 X RA, A10 X NOP NOP ILLEGAL 2 ILLEGAL 2 Row Active NOP 4 Action Auto-Refresh or Self-Refresh 5 Mode Register Write NOP NOP Read Write ILLEGAL 2 Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst --> Row Active Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge ILLEGAL NOP (Continue Row Active after Burst ends) NOP (Continue Row Active after Burst ends) Term Burst --> Row Active Term Burst, start new Burst Read 3 Term Burst, start new Burst Write 3 ILLEGAL 2 Term Burst, execute Row Precharge 3 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL NOP (Continue Burst to End and enter Row Precharge) NOP (Continue Burst to End and enter Row Precharge) ILLEGAL 2 ILLEGAL 2 ILLEGAL ILLEGAL 2 ILLEGAL Row Active Read Write Read with Auto Precharge Write with Auto Precharge 28/30 MSM56V16800F FUNCTION TRUTH TABLE (Table 1) (2/2) Current State Precharge 1 CS H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L RAS X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L CAS X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X WE X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X BA X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X X X X X X X X X X ADDR X X X CA RA A10 X X X X CA RA A10 X X X X CA RA A10 X X X X X X X X X X X NOP --> Idle after tRP NOP --> Idle after tRP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 NOP 4 ILLEGAL NOP NOP ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL Action Write Recovery Row Active NOP --> Row Active after tRCD NOP --> Row Active after tRCD ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL 2 ILLEGAL NOP --> Idle after tRC NOP --> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL Refresh Mode Register Access ABBREVIATIONS RA = Row Address CA = Column Address BA = Bank Address AP = Auto Precharge NOP = No OPeration command *Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of lCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle. 29/30 MSM56V16800F FUNCTION TRUTH TABLE for CKE (Table 2) Current State (n) Self Refresh CKEn-1 H L L L L L L Power Down H L L L L L L All Banks Idle 6 (ABI) H H H H H H H H L Any State Other than Listed Above H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L CS X H L L L L X X H L L L L X X H L L L L L L X X X X X RAS X X H H H L X X X H H H L X X X H H H L L L X X X X X CAS X X H H L X X X X H H L X X X X H H L H L L X X X X X WE X X H L X X X X X H L X X X X X H L X L H L X X X X X ADDR X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self Refresh --> ABI Exit Self Refresh --> ABI ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self Refresh) INVALID Exit Power Down --> ABI Exit Power Down --> ABI ILLEGAL ILLEGAL ILLEGAL 6 NOP (Continue power down mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend Next Cycle Enable Clock of Next Cycle Continue Clock Suspension Action *Notes : 6. Power-down and self-refresh can be entered only when all the banks are in an idle state. 30/30