MSM63P238

E2E0041-18-95 ¡ Semiconductor MSM63P238 ¡ Semiconductor This version: Sep. 1998 MSM63P238 4-Bit Microcontroller with Built-in 16K Word PROM, POCSAG Decoder, and Melody Circuit GENERAL DESCRIPTION The MSM63P238 is a CMOS 4-bit microcontroller with a built-in POCSAG (Post Office Code Standardization Advisory Group) decoder, which employs Oki's original nX-4/250 CPU core. The MSM63P238 is a one-time-programmable ROM-version product having one-time PROM (OTP) as internal program memory. The specifications of the MSM63P238 are equal to those of the MSM63238 except for electrical characteristics, packaging (only 80-pin flat package is available for the MSM63P238), and some functions. FEATURES The features of the MSM63P238 with an asterisk (*) differ from those of the mask ROM-version MSM63238. • Rich instruction set 439 instructions Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, external memory transfer, stack operations, flag operations, branch, conditional branch, call/return, control. • Rich selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register. Data memory bank internal direct addressing mode. • Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle. Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock) 1 ms (@ 2 MHz system clock) • Clock generation circuit Low-speed clock High-speed clock : 32.768 kHz/38.4 kHz/76.8 kHz crystal oscillator : 2 MHz (Max.) RC or ceramic oscillator select • Program memory (PROM) space* 16K words Basic instruction length is 16 bits/1 word • Data memory space 1K nibbles • External data memory space 64 Kbytes (expandable by using an I/O port) 1/28 ¡ Semiconductor • Stack level Call stack level Register stack level MSM63P238 : 16 levels : 16 levels • POCSAG decoder Data rate : 512 bps/1200 bps/2400 bps User frame : 3 types User address : 6 types Battery saving mode (for controlling intermittent operations of RF receiver) • I/O ports Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/ high-impedance input Output ports: Selectable as P-channel open drain output/N-channel open drain output/ CMOS output/high-impedance output Input-output ports: Selectable as input with pull-up resistance/input with pull-down resistance/high-impedance input Selectable as P-channel open drain output/N-channel open drain output/CMOS output/high-impedance output Can be interfaced with external peripherals that use a different power supply than this device uses. Number of ports: Input port : 1 port ¥ 4 bits Output port : 6 ports ¥ 4 bits Input-output port : 5 ports ¥ 4 bits 1 port ¥ 2 bits • Melody output function Melody sound frequency Tone length Tempo Note data Buzzer drive signal output • Reset function Reset through RESET pin Power-on reset Reset by low-speed oscillation halt • Battery check* Low-voltage supply check Criterion voltage : : : : : 529 to 2979 Hz 63 types 15 types Resides in the program memory 4 kHz : Can be selected as 2.20 ± 0.20 V or 2.80 ± 0.30 V • Power supply backup* Backup circuit (voltage multiplier) enables operation at 1.45 V minimum 2/28 ¡ Semiconductor MSM63P238 • Timers and counter 8-bit timer ¥ 4 Selectable as auto-reload mode/capture mode/clock frequency measurement mode Watchdog timer ¥ 1 15-bit time base counter ¥ 1 1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read • Serial port Mode UART communication speed Clock frequency in synchronous mode Data length • Interrupt sources External interrupt Internal interrupt : UART mode, synchronous mode : 1200 bps, 2400 bps, 4800 bps, 9600 bps : 32.768 kHz (internal clock mode), external clock frequency : 5 to 8 bits :3 : 15 (watchdog timer interrupt is a nonmaskable interrupt) • Operating voltage* When backup used When backup not used • Package*: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) : VDD = 1.45 to 2.7 V : VDD = 2.7 to 5.5 V : (Product name: MSM63P238-xxxGS-BK) xxx indicates a code number. 3/28 ¡ Semiconductor MSM63P238 BLOCK DIAGRAM An asterisk (*) indicates the port secondary function. and indicate that the power is supplied from VDDI to the circuits corresponding to the signal names inside , and from VDDR to the circuits corresponding to signal names inside . (VDDI and VDDR: power supply for interface) nX-4/250 H L TIMING CONTROL CBR RA PC PROM 16KW VPP EBR X Y C A G MIE Z BUS CONTROL EXTMEM A0-15* RD* WR* IR D0-7* SP RSP ALU STACK CAL.S: 16-level REG.S: 16-level INSTRUCTION DECODER INT 4 RESET RST RAM 1024N INT TST1 TST2 TST3 2 TST INT INT INT XTM0 XTM1 XT0 XT1 OSC0 OSC1 TBCCLK* HSCLK* XTSEL0 XTSEL1 VDDH VDD VDDL VDD2 CB1 CB2 4 TBC 1 MELODY MD SIO TIMER 8bit ¥ 4 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* RXC* TXC* RXD* TXD* BLD INT 1 WDT DATA BUS OSC P8.0, P8.1 P9.0-P9.3 I/O PORT INT 3 INT 1 INPUT PORT PC.0-PC.3 PD.0-PD.3 PA.0-PA.3 PB.0-PB.3 P1.0-P1.3 BACKUP INT 3 Internal PORT P0.0-P0.3 P8.2, P8.3 PE.0-PE.3 PF.0-PF.3 P7.0-P7.3 P6.0-P6.3 OUTPUT PORT P5.0-P5.3 P4.0-P4.3 P3.0-P3.3 P2.0-P2.3 VDDI VDDR SIGIN BS1 BS2 POCSAG Dec 4/28 ¡ Semiconductor MSM63P238 PIN CONFIGURATION (TOP VIEW) 72 PA.3 71 PA.2 70 PA.1 69 PA.0 80 P5.3 78 P5.1 77 P5.0 76 P4.3 75 P4.2 74 P4.1 73 P4.0 68 P9.3 67 P9.2 66 P9.1 65 P9.0 79 P5.2 (NC) P6.0 P6.1 P6.2 P6.3 P7.0 P7.1 P7.2 P7.3 BS1 BS2 SIGIN VDDR XT0 XT1 TST1 TST2 TST3 OSC0 OSC1 XTSEL0 XTSEL1 XTM0 XTM1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 P8.1 63 (NC) 62 P8.0 61 P3.3 60 P3.2 59 P3.1 58 P3.0 57 P2.3 56 P2.2 55 P2.1 54 P2.0 53 P1.3 52 P1.2 51 P1.1 50 P1.0 49 PB.3 48 PB.2 47 PB.1 46 PB.0 45 PC.3 44 PC.2 43 PC.1 42 PC.0 41 (NC) Note: Pins marked as (NC) are no-connection pins which are left open. (NC) 25 VDD2 26 VDDL 27 VDDH 28 CB1 29 CB2 30 VDD 31 VSS 32 MD 33 RESET 34 VPP 35 VDDI 36 PD.0 37 PD.1 38 PD.2 39 PD.3 40 80-Pin Plastic QFP 5/28 ¡ Semiconductor MSM63P238 PIN DESCRIPTIONS The basic functions of each pin of the MSM63P238 are described in Table 1. A symbol with a slash (/) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin. Table 1 Pin Descriptions (Basic Functions) Function Symbol VPP VDD VSS VDDR VDDI Power Supply VDDL VDD2 VDDH CB1 CB2 XT0 XT1 XTM0 Oscillation XTM1 OSC0 OSC1 XTSEL0 XTSEL1 TST1 Test TST2 TST3 Pin 35 31 32 13 36 27 26 28 29 30 14 15 23 24 19 20 21 I 22 16 17 18 I Type — — — — — — — — — — I O I O I O Positive power supply Negative power supply Interface power supply for SIGIN, BS1, BS2 Positive power supply pin for external interface (power supply for input, output, and I/O ports) Positive power supply pin for internal logic (internally generated). A capacitor (0.1 mF) should be connected between this pin and VSS. Positive power supply pin for low-speed clock (internally generated) Voltage multiplier pin for power supply backup (internally generated). A capacitor (1.0 mF) should be connected between this pin and VSS. Pins to connect a capacitor for voltage multiplier. A capacitor (1.0 mF) should be connected between CB1 and CB2. Clock oscillation pins for POCSAG decoder. A 32.768 kHz, 38.4 kHz, or 76.8 kHz crystal and capacitor (CG) should be connected to these pins. Low-speed clock oscillation pins for CPU. A 32.768 kHz crystal and capacitor (CGM) should be connected to these pins. High-speed clock oscillation pins. A ceramic resonator and capacitors (CL0, CL1) or external oscillation resistor (ROS) should be connected to these pins. Low-speed CPU clock select pins. These pins are used to select a low-speed CPU clock. Because these are high impedance inputs, be sure to tie these pins to VDD or VSS. Input pins for testing. Pull-down resistors are internally connected to these pins. The user cannot use these pins. Reset input pin. Setting this pin to "H" level puts this device into a reset state. Reset RESET 34 I Then, setting this pin to "L" level starts executing an instruction from address 0000H. A pull-down resistor is internally connected to this pin. Description Power supply (+12.5 V) for PROM writing 6/28 ¡ Semiconductor Table 1 Pin Descriptions (Basic Functions) (continued) Function Melody POCSAG Decoder Symbol MD BS1 BS2 SIGIN P1.0/INT5 P1.1/INT5 P1.2/INT5 P1.3/INT5 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 Port P4.0/A0 P4.1/A1 P4.2/A2 P4.3/A3 P5.0/A4 P5.1/A5 P5.2/A6 P5.3/A7 P6.0/A8 P6.1/A9 P6.2/A10 P6.3/A11 P7.0/A12 P7.1/A13 P7.2/A14 P7.3/A15 Pin 33 10 11 12 50 51 I 52 53 54 55 56 57 58 59 60 61 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 O O O O O O 4-bit output ports. Type O O I Description Melody output pin (normal phase) Battery saving outputs. MSM63P238 Signals to control intermittent operations of RF receiver. Receive data input pin. Input pin for receive data from RF receiver. 4-bit input port. Pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output is selectable for each bit. 7/28 ¡ Semiconductor Table 1 Pin Descriptions (Basic Functions) (continued) Function Symbol P8.0/RD P8.1/WR P9.0/D0 P9.1/D1 P9.2/D2 P9.3/D3 PA.0/D4 PA.1/D5 PA.2/D6 PA.3/D7 PB.0/INT0/ TM0CAP/ TM0OVF PB.1/INT0/ TM1CAP/ Port TM1OVF PB.2/INT0/ T02CK PB.3/INT0/ T13CK PC.0/INT1/ RXD PC.1/INT1/ TXC PC.2/INT1/ RXC PC.3/INT1/ TXD PD.0 PD.1 PD.2 PD.3 48 49 42 43 I/O 44 45 37 38 39 40 I/O 47 I/O 46 Pin 62 64 65 66 67 68 69 70 71 72 I/O I/O Type I/O Description MSM63P238 2-bit input-output port and 4-bit input-output ports. In input mode, pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. In output mode, P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output is selectable for each bit. 8/28 ¡ Semiconductor Table 2 shows the secondary functions of each pin of the MSM63P238. Table 2 Pin Descriptions (Secondary Functions) Function Symbol PB.0/INT0 PB.1/INT0 PB.2/INT0 PB.3/INT0 PC.0/INT1 External Interrupt PC.1/INT1 PC.2/INT1 PC.3/INT1 P1.0/INT5 P1.1/INT5 P1.2/INT5 P1.3/INT5 Capture PB.0/TM0CAP PB.1/TM1CAP Pin 46 47 48 49 42 43 44 45 50 51 52 53 46 47 I I I I I Type Description External 0 interrupt input pins. MSM63P238 The change of input signal level causes an interrupt to occur. The Port B Interrupt Enable register (PBIE) enables or disables an interrupt for each bit. External 1 interrupt input pins. The change of input signal level causes an interrupt to occur. The Port C Interrupt Enable register (PCIE) enables or disables an interrupt for each bit. External 5 interrupt input pins. The change of input signal level causes an interrupt to occur. The Port 1 Interrupt Enable register (P1IE) enables or disables an interrupt for each bit. Timer 0 capture trigger input pin. Timer 1 capture trigger input pin. 9/28 ¡ Semiconductor Table 2 Pin Descriptions (Secondary Functions) (continued) Function Symbol PB.0/TM0OVF Timer PB.1/TM1OVF PB.2/T02CK PB.3/T13CK Oscillation PD.2/TBCCLK Output PD.3/HSCLK PC.0/RXD Pin 46 47 48 49 39 40 42 Type O O I I O O I Description Timer 0 overflow flag output pin. Timer 1 overflow flag output pin. MSM63P238 External clock input pin for timer 0 and timer 2. External clock input pin for timer 1 and timer 3. Low-speed oscillation clock output pin High-speed oscillation clock output pin Serial port receive data input pin Sync serial port clock input-output pin. Transmit clock output when this device is used as a master PC.1/TXC Serial Port PC.2/RXC 43 I/O processor. Transmit clock input when this device is used as a slave processor. Sync serial port clock input-output pin. Receive clock output when this device is used as a master 44 I/O processor. Receive clock input when this device is used as a slave processor. PC.3/TXD 45 O Serial port transmit data output pin. 10/28 ¡ Semiconductor MSM63P238 Table 2 Pin Descriptions (Secondary Functions) (continued) Function Symbol P4.0/A0 P4.1/A1 P4.2/A2 P4.3/A3 P5.0/A4 P5.1/A5 P5.2/A6 P5.3/A7 P6.0/A8 P6.1/A9 P6.2/A10 P6.3/A11 External Memory P7.0/A12 P7.1/A13 P7.2/A14 P7.3/A15 P9.0/D0 P9.1/D1 P9.2/D2 P9.3/D3 PA.0/D4 PA.1/D5 PA.2/D6 PA.3/D7 P8.0/RD P8.1/WR Pin 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 65 66 67 68 69 70 71 72 62 64 O O Read signal output pin for external memory (negative logic) Write signal output pin for external memory (negative logic) I/O Data bus for external memory O Type Description Address output bus for external memory 11/28 ¡ Semiconductor MSM63P238 ABSOLUTE MAXIMUM RATINGS (VSS = 0 V) Parameter Power Supply Voltage 1 Power Supply Voltage 2 Power Supply Voltage 3 Power Supply Voltage 4 Power Supply Voltage 5 Input Voltage 1 Input Voltage 2 Input Voltage 3 Output Voltage 1 Output Voltage 2 Output Voltage 3 Output Voltage 4 Storage Temperature Symbol VDD VDDI VDDR VDDH VDDL VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 VOUT4 TSTG Condition Backup used, Ta = 25°C Backup not used, Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C Ta = 25°C VDD Input, Ta = 25°C VDDI Input, Ta = 25°C VDDR Input, Ta = 25°C VDD output, Ta = 25°C VDDI output, Ta = 25°C VDDR output, Ta = 25°C VDDH output, Ta = 25°C — Rating –0.3 to +3.0 –0.3 to +6.0 –0.3 to +6.0 –0.3 to +6.0 –0.3 to +6.0 –0.3 to +6.0 –0.3 to VDD + 0.3 –0.3 to VDDI + 0.3 –0.3 to VDDR + 0.3 –0.3 to VDD + 0.3 –0.3 to VDDI + 0.3 –0.3 to VDDR + 0.3 –0.3 to VDDH + 0.3 –55 to +150 Unit V V V V V V V V V V V V °C 12/28 ¡ Semiconductor MSM63P238 RECOMMENDED OPERATING CONDITIONS • When backup is used (VSS = 0 V) Parameter Operating Temperature Operating Voltage Symbol Top VDD VDDI VDDR Crystal Oscillation Frequency Ceramic Oscillation Frequency External RC Oscillator Resistance fXT fXTM fCM ROS Condition — — — — — — VDD = 1.45 to 2.7 V VDD = 1.45 to 2.7 V Range 0 to +65 1.45 to 2.7 1.45 to 5.5 1.45 to 5.5 30 to 80 30 to 35 200k to 1M 50 to 300 Unit °C V V V kHz kHz Hz kW • When backup is not used (VSS = 0 V) Parameter Operating Temperature Operating Voltage Symbol Top VDD VDDI VDDR Crystal Oscillation Frequency Ceramic Oscillation Frequency External RC Oscillator Resistance fXT fXTM fCM ROS Condition — — — — — — VDD = 2.7 to 5.5 V VDD = 2.9 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.9 to 5.5 V Range 0 to +65 2.7 to 5.5 1.8 to 5.5 1.8 to 5.5 30 to 80 30 to 35 300k to 1M 200k to 2M 50 to 300 30 to 300 Unit °C V V V kHz kHz Hz kW 13/28 ¡ Semiconductor MSM63P238 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = VDDI = VDDR = 1.45 to 5.5 V, VDDH = 2.7 to 5.5 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified) MeaParameter Symbol Condition Min. Typ. Max. Unit suring Circuit VDDL Voltage VDD2 Voltage Crystal Oscillation Start Voltage Crystal Oscillation Stop Detect Time External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance Internal RC Oscillator Capacitance POR Voltage Non-POR Voltage VDDL VDD2 VSTA 5 seconds — — — — — VDD = 1.5 V VDD = 3.0 V VDD = 1.5 V VDD = 3.0 V High speed clock stop High speed clock oscillation — Oscillation start time: within 1.2 1.45 1.2 1.45 1.45 0.1 12 12 8 0.0 0.0 1.45 2.7 1.6 — 1.6 — — — — 15 12 — — — — 2.0 5.5 2.0 — — 5.0 30 20 16 0.4 0.7 1.5 3.0 V V V V V ms pF pF pF V V V V 1 Crystal Oscillation Hold Voltage VHOLD TSTOP CG, CGM CD, CDM COS VPOR1 VPOR2 Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. 2. "POR" denotes Power On Reset. 3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises up to VDD. 4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and again rises up to VDD. 14/28 ¡ Semiconductor DC Characteristics (continued) • When backup is used MSM63P238 Parameter (VDD = VDDI = 1.5 V, VDDH = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit CPU in HALT mode. (High-speed clock oscillation stop) Decoder in HALT mode. (Decoder oscillation stop) CPU in HALT mode. (High-speed clock oscillation stop) Decoder in carrier on state. (76.8 kHz operation) CPU in HALT mode. (High-speed clock oscillation stop) Decoder in data receiving state. (76.8 kHz operation) CPU in operation at 32 kHz. (High-speed clock oscillation stop) Decoder in HALT mode. (Decoder oscillation stop) CPU in operation at high speed. (RC oscillation, ROS = 51 kW) Decoder in HALT mode. (Decoder oscillation stop) CPU in operation at high speed. (Ceramic oscillation, 1 MHz) Decoder in HALT mode. (Decoder oscillaiton stop) Supply Current 1 IDD1 — 7.0 35 mA Supply Current 2 IDD2 — 17 40 mA Supply Current 3 IDD3 — 85 200 mA 1 Supply Current 4 IDD4 — 230 400 mA Supply Current 5 IDD5 — 1.5 2.0 mA Supply Current 6 IDD6 — 2.0 3.0 mA 15/28 ¡ Semiconductor DC Characteristics (continued) • When backup is not used MSM63P238 Parameter (VDD = VDDI = VDDH = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit CPU in HALT mode. (High-speed clock oscillation stop) Decoder in HALT mode. (Decoder oscillation stop) CPU in HALT mode. (High-speed clock oscillation stop) Decoder in carrier on state. (76.8 kHz operation) CPU in HALT mode. (High-speed clock oscillation stop) Decoder in data receiving state. (76.8 kHz operation) CPU in operation at 32 kHz. (High-speed clock oscillation stop) Decoder in HALT mode. (Decoder oscillation stop) CPU in operation at high speed. (RC oscillation, ROS = 51 kW) Decoder in HALT mode. (Decoder oscillation stop) CPU in operation at high speed. (Ceramic oscillation, 2 MHz) Decoder in HALT mode. (Decoder oscillation stop) Supply Current 1 IDD1 — 3.0 20 mA Supply Current 2 IDD2 — 8.0 20 mA Supply Current 3 IDD3 — 42 100 mA 1 Supply Current 4 IDD4 — 120 200 mA Supply Current 5 IDD5 — 1.5 2.0 mA Supply Current 6 IDD6 — 3.5 5.0 mA 16/28 ¡ Semiconductor DC Characteristics (continued) MSM63P238 Parameter Output Current 1 (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) . . . (PC.0 to PC.3) (PD.0 to PD.3) Output Current 2 (MD) (VDD = VDDI = VDDH = VDDR = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit VDDI = 1.5 V IOH1 VOH1 = VDDI – 0.5 V VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V IOL1 VOL1 = 0.5 V VDDI = 3.0 V VDDI = 5.0 V VDD = 1.5 V IOH2 VOH2 = VDD – 0.7 V VDD = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V IOL2 VOL2 = 0.7 V VDD = 3.0 V VDD = VDDH = 5.0 V VDDR = 1.5 V IOH3 VOH3 = VDDR – 0.5 V VDDR = 3.0 V VDDR = 5.0 V VDDR = 1.5 V IOL3 VOL3 = 0.5 V VDDR = 3.0 V VDDR = 5.0 V –2.0 –5.0 –8.0 0.4 1.0 2.0 –2.5 –6.0 –9.0 0.5 2.0 4.0 –6.0 –15.0 1.2 3.0 6.0 –2.5 –3.0 0.75 1.0 –240 –400 60 100 — –1.2 –3.0 –4.0 1.4 3.0 4.0 –1.3 –4.0 –5.5 1.3 4.0 5.5 –3.6 –9.0 3.6 9.0 12.0 –1.5 –2.0 1.5 2.0 –120 –200 120 200 — –0.4 –1.0 –2.0 2.0 5.0 8.0 –0.5 –2.0 –4.0 2.5 6.0 9.0 –1.2 –3.0 –6.0 6.0 15.0 24.0 –0.75 –1.0 2.5 3.5 –60 –100 250 400 1.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 2 Output Current 3 (BS1, BS2) –24.0 –12.0 Output Current 4 (OSC1) IOH4R IOL4R IOH4C IOL4C VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V (RC oscillation) VOL4R = 0.5 V (RC oscillation) (ceramic oscillation) VOL4C = 0.5 V (ceramic oscillation) VOH = VDDI VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V Output Leakage (P2.0 to P2.3) (P3.0 to P3.3) (P4.0 to P4.3) . . . (PD.0 to PD.3) IOOH IOOL VOL = VSS –1.0 — — mA 17/28 ¡ Semiconductor DC Characteristics (continued) MSM63P238 Parameter Input Current 1 (P1.0 to P1.3) (P8.0, P8.1) (P9.0 to P9.3) . . . (PD.0 to PD.3) (VDD = VDDI = VDDH = VDDR = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit IIH1 VIH1 = VDDI (when pulled down) VIL1 = VSS (when pulled up) VDDI = 1.5 V VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V VDDI = 3.0 V VDDI = 5.0 V 2 30 70 –30 –180 –600 0.0 –1.0 0.0 –1.0 VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V –200 –600 0.0 –1.0 0.1 0.75 –1.0 –3.0 10 150 0.5 –1.0 VDD = 1.5 V IIH5 IIL5 VIH5 = VDD VIL5 = VSS VIH6 = VDD VIL6 = VSS VDD = 3.0 V VDD = VDDH = 5.0 V 50 0.5 1.25 –1.0 0.0 –1.0 10 90 250 –10 –90 –250 — — — — –110 –350 — — 0.5 1.5 –0.5 –1.5 50 350 1.0 — 150 1.0 2.5 — — — 30 180 600 –2 –30 –70 1.0 0.0 1.0 0.0 –30 –150 1.0 0.0 1.0 3.0 –0.1 –0.75 80 600 2.0 0.0 300 1.5 4.0 0.0 1.0 0.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 3 IIL1 IIH1Z IIL1Z VIH1 = VDDI (in a high impedance state) VIL1 = VSS (in a high impedance state) VIH2 = VDDR VIL2 = VSS VIL3 = VSS (when pulled up) Input Current 2 (SIGIN) Input Current 3 (OSC0) IIH2Z IIL2Z IIL3 IIH3R IIL3R IIH3C IIL3C VIH3 = VDDH (RC oscillation) VIL3 = VSS (RC oscillation) VIH3 = VDDH VIL3 = VSS VDD = VDDH = 3.0 V VDD = VDDH = 3.0 V VDD = 1.5 V (ceramic oscillation) VDD = VDDH = 5.0 V (ceramic oscillation) VDD = VDDH = 5.0 V VIH4 = VDD VIL4 = VSS VDD = 3.0 V VDD = VDDH = 5.0 V Input Current 4 (RESET) IIH4 IIL4 Input Current 5 (TST1, TST2, TST3) Input Current 6 (XTSEL0, XTSEL1) IIH6Z IIL6Z 18/28 ¡ Semiconductor DC Characteristics (continued) MSM63P238 Parameter Input Voltage 1 (P1.0 to P1.3) (P8.0, P8.1) (P9.0 to P9.3) . . . (PD.0 to PD.3) Input Voltage 2 (SIGIN) (VDD = VDDI = VDDH = VDDR = 3.0 V, VSS = 0 V, Ta = 0 to +65°C unless otherwise specified) MeaSymbol Condition Min. Typ. Max. Unit suring Circuit VDDI = 1.5 V VIH1 VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V VIL1 VDDI = 3.0 V VDDI = 5.0 V VDDR = 1.5 V VIH2 VDDR = 3.0 V VDDR = 5.0 V VDDR = 1.5 V VIL2 VDDR = 3.0 V VDDR = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VIH4 VDD = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VIL4 VDD = 3.0 V VDD = VDDH = 5.0 V VDDI = 1.5 V DVT1 VDDI = 3.0 V VDDI = 5.0 V VDD = 1.5 V DVT2 VDD = 3.0 V VDD = VDDH = 5.0 V 1.2 2.4 4.0 0.0 0.0 0.0 1.2 2.4 4.0 0.0 0.0 0.0 2.4 4.0 0.0 0.0 1.35 2.4 4.0 0.0 0.0 0.0 0.05 0.2 0.25 0.05 0.2 0.25 — — — — — — — — — — — — — — — — — — — — — — 0.1 0.5 1.0 0.1 0.5 1.0 1.5 3.0 5.0 0.3 0.6 1.0 1.5 3.0 5.0 0.3 0.6 1.0 3.0 5.0 0.6 1.0 1.5 3.0 5.0 0.15 0.6 1.0 0.3 1.0 1.5 0.3 1.0 1.5 V V V V V V V V V V V V V V V V V V V V V V V V V V V V 4 Input Voltage 3 (OSC0) VIH3 VIL3 Input Voltage 4 (RESET, TST1, TST2, TST3, XTSEL0, XTSEL1) Hysteresis Width 1 (P1.0 to P1.3) (P8.0, P8.1) . . . (PD.0 to PD.3) Hysteresis Width 2 (RESET, TST1, TST2, TST3, XTSEL0, XTSEL1) Input Pin Capacitance (P1.0 to P1.3) (P8.0, P8.1) (P9.0 to P9.3) . . . (PD.0 to PD.3) CIN — — — 5 pF 1 19/28 ¡ Semiconductor Measuring circuit 1 MSM63P238 Cb12 CB1 CB2 XT0 XT1 XTM0 CG 76.8 kHz CGM Crystal 32.768 kHz Crystal q (*1) w OSC0 OSC1 VSS VDD A Ch V VDDI VDDR VDDH VDDL Cl V XTM1 VDD2 C2 V Cl, C2 Ch, Cb12 CG, CGM CL0 CL1 Ceramic Resonator : 0.1 mF : 1 mF : 15 pF : 30 pF : 30 pF : CSB1000J (1 MHz) CSA2.00MG (2 MHz) (Murata MFG.-make) *1 RC Oscillator q ROS w Ceramic Oscillator q CL0 CL1 Ceramic Resonator w Measuring circuit 2 (*3) VIH (*2) INPUT OUTPUT A VIL VSS VDD VDDI VDDR VDDH VDDL VDD2 *2 Input logic circuit to determine the specified measuring conditions. *3 Measured at the specified output pins. 20/28 ¡ Semiconductor Measuring circuit 3 MSM63P238 (*4) A INPUT OUTPUT VSS VDD VDDI VDDR VDDH VDDL VDD2 Measuring circuit 4 VIH Waveform Monitoring (*4) INPUT OUTPUT VIL VSS VDD VDDI VDDR VDDH VDDL VDD2 *4 Measured at the specified input pins. 21/28 ¡ Semiconductor AC Characteristics (Serial Interface, Serial Port) MSM63P238 (VDD = VDDR = 1.45 to 5.5 V, VDDH = 2.7 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = 0 to +65°C unless otherwise specified) (1) Synchronous Communication Parameter TXC/RXC Input Fall Time TXC/RXC Input Rise Time TXC/RXC Input "L" Level Pulse Width TXC/RXC Input "H" Level Pulse Width TXC/RXC Input Cycle Time TXC/RXC Output Cycle Time TXD Output Delay Time RXD Input Setup Time RXD Input Hold Time Symbol tf tr tCWL tCWH tCYC tCYC1(O) tCYC2(O) tDDR tDS tDH Condition — — — — — CPU in operation state at 32 kHz CPU in operation at 2 MHz VDD = VDDH = 2.9 V to 5.5 V Output load capacitance 10 pF — — Min. — — 0.8 0.8 2.0 — — — 0.5 0.8 Typ. — — — — — 30.5 0.5 — — — Max. 1.0 1.0 — — — — — 0.4 — — Unit ms ms ms ms ms ms ms ms ms ms Synchronous communication timing ("H" level = 4.0 V, "L" level = 1.0 V) tCYC TXC (PC.1)/ RXC (PC.2) tr tCWH tDDR TXD (PC.3) tDS RXD (PC.0) tDH tDS 5 V (VDDI) 0 V (VSS) tDDR 5 V (VDDI) 0 V (VSS) tf tCWL 5 V (VDDI) 0 V (VSS) 22/28 ¡ Semiconductor (2) UART Communication MSM63P238 Parameter Transmit Baud Rate Receive Baud Rate Symbol TBRT RBRT Condition TBRT = 1/fBRT TCR = 1/fOSC RBRT = 1/fBRT Min. TBRT–TCR RBRT¥0.97 Typ. TBRT RBRT Max. TBRT+TCR RBRT¥1.03 Unit s s fBRT: Baud rates (1200, 2400, 4800, 9600 bps) UART communication timing ("H" level = 4.0 V, "L" level = 1.0 V) TBRT TXD (PC.3) RBRT RXD (PC.0) 5 V (VDDI) 0 V (VSS) 5 V (VDDI) 0 V (VSS) 23/28 ¡ Semiconductor AC Characteristics (External Memory Interface) MSM63P238 (VDD = VDDR = 1.45 to 5.5 V, VDDH = 2.7 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = 0 to +65°C unless otherwise specified) (1) Reading from External Memory (a) When CPU operates at 32.768 kHz Parameter Read Cycle Time RD Output Delay Time Output Valid Time External Memory Output Delay Time Symbol tRC tOE tOHA tDO Condition — — — — Min. — — — — Typ. 61.0 — — — Max. — 5.0 5.0 5.0 Unit ms ms ms ms (b) When CPU operates at 2 MHz (VDDH = 2.9 to 5.5 V) Parameter Read Cycle Time RD Output Delay Time Output Valid Time External Memory Output Delay Time Symbol tRC tOE tOHA tDO Condition — — — — Min. 1.0 — — — Typ. — — — — Max. — 100 100 150 Unit ms ns ns ns AC characteristics timing ("H" level = 4.0 V, "L" level = 1.0 V) MOVXB obj, xadr16 MOVXB obj, [RA] S1 System clock tRC P7 - P4 (A15 - A0) P8.0 (RD) PA, P9 (D7 - D0) Port setup value Address output Port setup value 5 V (VDDI) 0 V (VSS) 5 V (VDDI) 0 V (VSS) 5 V (VDDI) 0 V (VSS) S2 S1 S2 S1 S2 tOE Port setup value Input data tDO tOHA Port setup value 24/28 ¡ Semiconductor (2) Writing to External Memory (a) When CPU operates at 32.768 kHz Parameter Write Cycle Time Address Setup Time Write Time Write Recovery Time Data Setup Time Data Hold Time Symbol tWC tAS tW tWR tDS tDH Condition — — — — — — Min. — — — — — — Typ. 61.0 30.5 15.3 15.3 45.8 15.3 MSM63P238 Max. — — — — — — Unit ms ms ms ms ms ms (b) When CPU operates at 2 MHz (VDDH = 2.9 to 5.5 V) Parameter Write Cycle Time Address Setup Time Write Time Write Recovery Time Data Setup Time Data Hold Time Symbol tWC tAS tW tWR tDS tDH Condition — — — — — — Min. 1.0 0.4 0.2 0.2 0.7 0.2 Typ. — — — — — — Max. — — — — — — Unit ms ms ms ms ms ms AC characteristics timing ("H" level = 4.0 V, "L" level = 1.0 V) MOVXB [RA], obj or MOVXB xadr16, obj S1 System clock tWC P7 - P4 (A15 - A0) PA, P9 (D7 - D0) P8.1 (WR) tAS tW tWR Port setup value Address output Port setup value 5 V (VDDI) 0 V (VSS) 5 V (VDDI) 0 V (VSS) 5 V (VDDI) 0 V (VSS) S2 S1 S2 S1 S2 Port setup value Output data tDS tDH Port setup value 25/28 ¡ Semiconductor MSM63P238 APPLICATION CIRCUITS • RC oscillation is selected as high-speed oscillation. • Ports and RF section are powered from external memory power source. • CV is an IC power supply bypass capacitor. • Values of Cl, C2, CG, CGM, Ch, Cb12, and CV are for reference only. 76.8 kHz Crystal CG 12 to 30 pF 32.768 kHz Crystal CGM 12 to 30 pF Ch 1.5 V VDD CV 0.1 mF 1.0 mF 0.1 mF 0.1 mF OSC0 XT0 XT1 XTM0 XTM1 VDDH MSM63P238 P2 PC PD VDD Key Matrix LED Vibrator UART VSS OSC1 VDDR SIGIN BS1 BS2 VDD RF Section VSS ROS 1.0 mF CB1 CB2 VDDL VDD2 XTSEL0 XTSEL1 RESET TST1 TST2 TST3 Cb12 Cl C2 VDDI VDD P4-7 P9, PA P8.0 P8.1 P3 A15-0 D7-0 LCD Module ROM RD SRAM WR EEPROM External Memory VSS 5.0 V Push SW Open VSS Note: VDDI is the power supply pin for the input, output, and input-output ports. VDDR is the interface power supply pin for SIGIN, BS1, and BS2. Be sure to connect the VDDI and VDDR pins either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup 26/28 ¡ Semiconductor MSM63P238 APPLICATION CIRCUITS (continued) • Ceramic oscillation is selected as high-speed oscillation. • Ports and RF section are powered from external memory power source. • CV is an IC power supply bypass capacitor. • Values of Cl, C2, CG, CV, CL0, and CL1 are for reference only. CL0 30 pF 32.768 kHz Crystal CG 12 to 30 pF OSC0 XT0 OSC1 XT1 VDDR XTM0 XTM1 VDDH VDD MSM63P238 P2 PC PD SIGIN BS1 BS2 Ceramic Resonator CL1 30 pF VDD RF Section VSS 3.0 V VDD Key Matrix LED Vibrator UART VSS CV 0.1 mF Open Cl C2 0.1 mF 0.1 mF CB1 CB2 VDDL VDD2 XTSEL0 XTSEL1 RESET TST1 TST2 TST3 VSS VDDI VDD P4-7 P9, PA A15-0 D7-0 LCD Module ROM RD SRAM WR EEPROM External Memory VSS Push SW Open P8.0 P8.1 P3 Note: VDDI is the power supply pin for the input, output, and input-output ports. VDDR is the interface power supply pin for SIGIN, BS1, and BS2. Be sure to connect the VDDI and VDDR pins either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup 27/28 ¡ Semiconductor MSM63P238 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 28/28